TWI782075B - 絕緣層覆矽基板、半導體裝置及其製造方法 - Google Patents
絕緣層覆矽基板、半導體裝置及其製造方法 Download PDFInfo
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Abstract
本發明一些實施例揭露一種絕緣層覆矽(SOI)基板,其包含一半導體基板及一多層多晶矽結構。該多層多晶矽結構經放置於該半導體基板上方。該多層多晶矽結構包含:複數個多晶矽層,其等彼此堆疊;及一原生氧化物層,其在多晶矽層之各相鄰對之間。
Description
本發明實施例係有關絕緣層覆矽基板、半導體裝置及其製造方法。
藉由各種製造操作(諸如沉積、光微影、蝕刻、植入或類似物)在一半導體基板上製造半導體晶粒。近年來,已經開發絕緣層覆矽(SOI)基板作為一替代基板。SOI基板係具有藉由一絕緣層與一底層處置矽晶圓分離之一裝置矽層之一基板。SOI基板具有諸如減小之寄生電容、減小之功率消耗、減小之電流洩漏及在更高溫下操作的增大能力之優點。 處置矽晶圓具有高電阻率,此允許滿足一些應用要求(諸如裝置間隔離、被動裝置品質因數等)。歸因於處置矽晶圓之低摻雜物,載子趨於鄰近處置矽晶圓與絕緣層之間之介面累積。施加至上覆裝置之電壓可與累積的載子相互作用,從而劣化上覆裝置之效能。在一些應用(諸如RF應用)中,RF訊號可遭受串擾及非線性失真。
本發明的一實施例揭露一種絕緣層覆矽(SOI)基板,其包括:一半導體基板;及一多層多晶矽結構,其在該半導體基板上方,該多層多晶矽結構包括:複數個多晶矽層,其等彼此堆疊;及一原生氧化物層,其在該複數個多晶矽層之各相鄰對之間。 本發明的一實施例揭露一種半導體裝置,其包括:一絕緣層覆矽(SOI)基板;及一半導體組件,其在該SOI基板上方。該絕緣層覆矽(SOI)基板包括:一高電阻率處置基板;一多層富阱結構,其在該高電阻率處置基板上方;一絕緣層,其在該多層富阱結構上方。其中,該多層富阱結構包括:複數個富阱層,其等彼此堆疊;及一阻障層,其在該複數個富阱層之各相鄰對之間。 本發明的一實施例揭露一種用於製造一絕緣層覆矽(SOI)基板之方法,其包括:接納一半導體基板;使一多層多晶矽結構形成於該半導體基板上方;及使一埋入氧化物層及一主動層形成於該多層多晶矽結構上方。其中,該多層多晶矽結構包括:複數個多晶矽層,其等彼此堆疊;及一原生氧化物層,其在該複數個多晶矽層之各相鄰對之間。
下列揭露提供用於實施所提供標的物之不同構件之許多不同實施例或實例。下文描述元件及配置之特定實例以簡化本揭露。當然,此等僅為實例且不旨在限制。舉例而言,在下列描述中之一第一構件形成於一第二構件上方或上可包含其中該第一構件及該第二構件經形成為直接接觸之實施例,且亦可包含其中額外構件可形成在該第一構件與該第二構件之間,使得該第一構件及該第二構件可不直接接觸之實施例。另外,本揭露可在各個實例中重複參考數字及/或字母。此重複係用於簡單及清楚之目的且本身並不指示所論述之各項實施例及/或組態之間之一關係。 此外,為便於描述,可在本文中使用空間相對術語(諸如「在……下方」、「在……下」、「下」、「在……上」、「上」、「在……上方」及類似者)以描述如圖中所繪示之一個元件或構件與另一(若干)元件或構件之關係。空間相對術語旨在涵蓋使用或操作中之裝置除在圖中描繪之定向以外之不同定向。設備可經另外定向(旋轉90度或以其他定向),且因此可同樣解釋本文中所使用之空間相對描述詞。 如本文中所使用,術語(諸如「第一」、「第二」及「第三」)描述各種元件、組件、區域、層及/或區段,此等元件、組件、區域、層及/或區段不應受限於此等術語。此等術語可僅用以區分一個元件、組件、區域、層或區段與另一者。諸如「第一」、「第二」及「第三」之術語當在本文中使用時,並非意指一序列或順序,除非上下文清楚指示。 如本文中所使用,術語「近似」、「實質上」、「實質的」及「約」用於描述並考量小變化。當結合一事件或狀況使用時,該等術語可指代其中確切地發生該事件或狀況之例項以及其中近似發生該事件或狀況之例項。例如,當結合一數值使用時,該等術語可指代小於或等於該數值之±10%(諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%、或小於或等於±0.05%)之變化之一範圍。例如,若兩個數值之間之一差小於或等於該等值之一平均值之±10%(諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%),則該等值可被視為「實質上」相同或相等。例如,「實質上」平行可指代相對於0°之小於或等於±10°(諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°)之角度變化之一範圍。例如,「實質上」垂直可指代相對於90°之小於或等於±10°(諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°)之角度變化之一範圍。 在本揭露之一或多項實施例中,提供具有一多層富阱結構之一複合基板,該多層富阱結構包含複數個富阱層及一或多個阻障層。在一些實施例中,複合基板可包含一絕緣層覆矽(SOI)基板;富阱層可包含多晶矽層;且一或多個阻障層可包含氧化矽層。多層富阱結構之富阱層包含具有差排之晶體缺陷,其等用以捕獲一半導體基板中之載子。藉由將載子捕獲在多層富阱結構之晶體缺陷內,可減輕可導致對RF訊號之非線性失真之寄生表面傳導。多層富阱結構之阻障層可阻擋富阱層之晶粒彼此鄰接,且因此可幫助抑制晶粒之再生長。憑藉阻障層,可將富阱層之晶粒控制為具有較小晶粒尺寸及微粒結構,且因此可增大多層富阱結構之陷阱密度。 圖1係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一絕緣層覆矽(SOI)基板之一方法之一流程圖。方法100開始於其中接納一半導體基板之操作110。方法100繼續進行其中使一多層多晶矽結構形成於半導體基板上方之操作120。多層多晶矽結構可包含:複數個多晶矽層,其等彼此堆疊;及一原生氧化物層,其在多晶矽層之各相鄰對之間。方法100繼續進行其中使一埋入氧化物層及一主動層形成於多層多晶矽結構上方之操作130。 方法100僅係一實例,且並不意欲將本揭露限制於發明申請專利範圍中明確敘述之內容。可在方法100之前、期間及之後提供額外操作,且可針對方法之額外實施例替換、消除或移動所描述之一些操作。 圖2係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一多層多晶矽結構之一操作之一流程圖。操作120開始於其中使一第一多晶矽層形成於半導體基板上方之子操作122。操作120繼續進行其中使一原生氧化物層形成於第一多晶矽層上方之子操作124。操作120繼續進行其中使一第二多晶矽層形成於原生氧化物層上方之子操作126。在一些實施例中,子操作122、124及126可經多次循環以形成多晶矽層及原生氧化物層之更多堆疊。在一些實施例中,多晶矽層之數目係在2與6之間,但不限於此。 圖3A、圖3B、圖3C、圖3D、圖3E、圖3F及圖3G係根據本揭露之一或多項實施例之製造一絕緣層覆矽(SOI)基板之各種操作之一者處之示意圖。如圖3A中所示及圖1中之操作110所示,接納一半導體基板10。半導體基板10具有一第一表面101及與第一表面101相對之一第二表面102。在一些實施例中,半導體基板10係經組態為用於處置並建立待形成之上覆層之一基底之一處置基板。在一些實施例中,半導體基板10係一高電阻率處置基板。藉由實例,半導體基板10可具有大於1 KΩ-cm之一電阻率,但不限於此。在一些實施例中,半導體基板10包含一矽晶圓(諸如一單晶矽基板),但不限於此。在一些實施例中,半導體基板10之材料可包含其他半導體材料(諸如III-V半導體材料、碳化矽、矽鍺、鍺、砷化鎵或類似物)。 如圖3B中所示及圖2中之子操作122所示,使一第一多晶矽層201形成於半導體基板10上方。在一些實施例中,第一多晶矽層201係由一沉積操作(諸如一化學氣相沉積(CVD)、一低壓化學氣相沉積(LPCVD)或類似物)形成。在一些實施例中,在沉積操作期間引入反應氣體(諸如矽烷(SiH4
)或二氯矽烷(H2
SiCl2
)及氫氣(H2
))。在一些實施例中,在低溫下執行用於形成第一多晶矽層201之沉積操作,以防止第一多晶矽層201之晶粒尺寸過生長。在一些實施例中,用於形成第一多晶矽層201之沉積操作之製程溫度低於950℃。藉由實例,用於形成第一多晶矽層201之沉積操作之製程溫度實質上在自約600℃至約900℃之範圍內,但不限於此。在一些實施例中,第一多晶矽層201之晶粒尺寸小於或等於0.1微米。藉由實例,第一多晶矽層201之晶粒尺寸實質上在自0.03微米至0.1微米之範圍內,但不限於此。第一多晶矽層201可經組態為一富阱層。在一些實施例中,第一多晶矽層201可包含經組態以捕獲半導體基板10中之載子之晶體缺陷。 在一些實施例中,第一多晶矽層201可為無摻雜的。在一些實施例中,第一多晶矽層201可經摻雜以形成N型材料、P型材料或兩者。在一些實施例中,第一多晶矽層201可與半導體基板10電接觸。在一些替代實施例中,不干擾第一多晶矽層201與半導體基板10之間之載子轉移之一中間層可存在於第一多晶矽層201與半導體基板10之間。 如圖3C中所示及圖2中之子操作124所示,使一原生氧化物層22形成於第一多晶矽層201上方。在一些實施例中,原生氧化物層22可包含可由一熱操作形成之一熱氧化物層(諸如氧化矽層)。在一些實施例中,藉由將半導體基板10放置於一含氧環境中而形成原生氧化物層22。在一些實施例中,藉由將半導體基板10放置於一大氣環境中而形成原生氧化物層22。在一些實施例中,藉由將半導體基板10放置於一惰性氣體環境(其中引入惰性氣體(諸如氮氣)及氧氣)中而形成原生氧化物層22。在一些實施例中,可在自約10 ppm至約300 ppm之一流速下引入氮氣及氧氣,但不限於此。在一些實施例中,原生氧化物層22之厚度實質上在自0.5奈米至1.5奈米之範圍內,但不限於此。 在一些實施例中,可以一原位方式形成第一多晶矽層201及原生氧化物層22。藉由實例,第一多晶矽層201可經形成於一LPCVD設備之一沉積室中,而原生氧化物層22可經形成於同一LPCVD設備之另一室中。在一些實施例中,原生氧化物層22可經形成於同一CVD設備之一承載室中。在一些實施例中,在形成第一多晶矽層201之後,可將半導體基板10自沉積室遞送至承載室。承載室係處於低於沉積室之一低真空度中,且因此一些氧氣可保留於承載室中。保留在承載室中之氧氣可用作一氧化源,以在一高溫下形成原生氧化物層22。在一些實施例中,可以一異位方式形成第一多晶矽層201及原生氧化物層22。藉由實例,第一多晶矽層201可經形成於一CVD設備之一沉積室中,而原生氧化物層22可經形成於另一製造設備之另一室中。在一些實施例中,氧氣及其他惰性氣體(諸如氮氣)可經引入至室,以形成原生氧化物層22。 如圖3D中所示及圖2中之子操作126所示,使一第二多晶矽層202形成於原生氧化物層22上方。在一些實施例中,第二多晶矽層202係由一沉積操作(諸如一化學氣相沉積(CVD)、一低壓化學氣相沉積(LPCVD)或類似物)形成。在一些實施例中,在沉積操作期間引入一反應氣體(諸如矽烷(SiH4
)或二氯矽烷(H2
SiCl2
)及氫氣(H2
))。在一些實施例中,在低溫下執行用於形成第二多晶矽層202之沉積操作,以防止第二多晶矽層202之晶粒尺寸生長。在一些實施例中,用於形成第二多晶矽層202之沉積操作之製程溫度低於950℃。藉由實例,用於形成第二多晶矽層202之沉積操作之製程溫度實質上在自約600℃至約900℃之範圍內,但不限於此。在一些實施例中,第二多晶矽層202之晶粒尺寸小於或等於0.1微米。藉由實例,第二多晶矽層202之晶粒尺寸實質上在自0.03微米至0.1微米之範圍內,但不限於此。第二多晶矽層202可經組態為一富阱層。在一些實施例中,第二多晶矽層202可包含經組態以捕獲半導體基板10中之載子之晶體缺陷。 在一些實施例中,第二多晶矽層202可為無摻雜的。在一些實施例中,第二多晶矽層202可經摻雜以形成N型材料、P型材料或兩者。 在一些實施例中,插置於第一多晶矽層201與第二多晶矽層202之間之原生氧化物層22可經組態為一阻障層或一阻擋層。原生氧化物層22可阻擋第一多晶矽層201及第二多晶矽層202之晶粒彼此鄰接,且因此可幫助抑制晶粒之再生長。可將第一多晶矽層201及第二多晶矽層202之晶粒控制為具有較小晶粒尺寸、較精細結構及高陷阱密度。 如圖3E中所示及圖2中之操作120所示,子操作122、124及126可經多次循環以形成另一或多個多晶矽層及原生氧化物層,以使一多層多晶矽結構20形成於半導體基板10上方。在一些實施例中,多層多晶矽結構20可包含插置於多晶矽層之各相鄰對之間之四個多晶矽層及三個原生氧化物層22。例如,隨後使一第三多晶矽層203及一第四多晶矽層204形成於第二多晶矽層202上方。在多晶矽層之各相鄰對之間形成原生氧化物層22。在一些實施例中,可藉由與第一多晶矽層201及第二多晶矽層202類似的操作而形成第三多晶矽層203及第四多晶矽層204。第三多晶矽層203及第四多晶矽層204可具有與第一多晶矽層201及第二多晶矽層202類似的特性。在一些實施例中,可藉由與原生氧化物層22類似的操作形成額外原生氧化物層22。在一些實施例中,第三多晶矽層203或第四多晶矽層204之晶粒尺寸可小於或等於0.1微米。例如,第三多晶矽層203或第四多晶矽層204之晶粒尺寸可實質上在自0.03微米至0.1微米之範圍內,但不限於此。在一些實施例中,多層多晶矽結構20之厚度小於或等於3微米。藉由實例,多層多晶矽結構20之厚度實質上在自0.6微米至3微米之範圍內,但不限於此。在一些實施例中,多層多晶矽結構20之多晶矽層之數目係在2與6之間,但不限於此。在一些實施例中,多層多晶矽結構20之多晶矽層之數目可超過6。在一些實施例中,多層多晶矽結構20之多晶矽層之厚度經組態以抑制晶粒之生長。例如,多層多晶矽結構20之各多晶矽層之厚度實質上在自約0.1微米至約1.5微米之範圍內,但不限於此。 在一些實施例中,可對多層多晶矽結構20執行於一平坦化操作(諸如一化學機械拋光(CMP)操作),以平坦化多層多晶矽結構20之表面。 如圖3F中所示及圖1中之操作130所示,使一埋入氧化物層30形成於多層多晶矽結構20上方。在一些實施例中,埋入氧化物層30係埋入氧化矽層(諸如一熱氧化矽層)。在一些實施例中,可藉由一熔爐中之氧化或藉由其他適合氧化操作而形成埋入氧化物層30。在一些實施例中,埋入氧化物層30可經組態為一絕緣層。埋入氧化物層30將待形成之一主動半導體層與半導體基板10電隔離。在一些實施例中,可對埋入氧化物層30執行一平坦化操作(諸如一CMP操作),以平坦化埋入氧化物層30之表面。 如圖3G中所示及圖1中之操作130所示,可使一主動層40形成於埋入氧化物層30上方以形成一SOI基板1。在一些實施例中,主動層40可包含一主動半導體層(諸如一表面矽層或其他半導體層),但不限於此。在一些實施例中,可藉由將一半導體晶圓(諸如一矽晶圓)接合至埋入氧化物層30而形成主動層40。在一些實施例中,半導體晶圓可藉由(例如)研磨或拋光而經薄化至一適合厚度。在一些實施例中,主動層40可經組態為用於製造一半導體組件(諸如一被動裝置及/或一主動裝置)之一主動區。在一些實施例中,半導體組件可包含一射頻(RF)裝置。 在本揭露之一些實施例中,多層多晶矽結構20經組態為一多層富阱結構。多層多晶矽結構20之多晶矽層包含具有差排之晶體缺陷。晶體缺陷經組態以捕獲半導體基板10及/或埋入氧化物層30中之載子。藉由將載子捕獲在多層多晶矽結構20之晶體缺陷內,可減輕可導致對RF訊號之非線性失真之寄生表面傳導。在裝置(諸如RF開關)之製造期間,SOI基板1可經歷一些退火操作或經歷高溫。多層多晶矽結構20之原生氧化物層22經組態以阻擋多晶矽層之晶粒彼此鄰接,且因此可幫助在退火操作期間或在高溫下抑制晶粒之再生長。憑藉原生氧化物層22,可將多晶矽層之晶粒控制為具有較小晶粒尺寸及微粒結構,且因此可增大多層多晶矽結構20之陷阱密度。 本揭露之絕緣層覆矽(SOI)基板及半導體裝置不限於上文提及之實施例,且可具有其他不同實施例。為了簡化描述,並為了方便本揭露之實施例之各者之間之比較起見,以下實施例之各者中之相同組件由相同元件符號標記。為使更容易比較實施例之間之差異,下文描述將詳述不同實施例之間之不同之處,且相同特徵將不再贅述。 圖4係根據本揭露之一些實施例之一半導體裝置之一示意圖。如圖4中所示,半導體裝置60可包含一絕緣層覆矽(SOI)基板2及一半導體組件50。在一些實施例中,SOI基板2可類似於如圖3G中所繪示之SOI基板1。半導體組件50經放置於SOI基板2上方。在一些實施例中,半導體組件50可包含一RF電晶體或類似者。在一些實施例中,半導體組件50可包含一閘極電極52、一閘極絕緣層54、源極/汲極區56及間隔結構58。閘極電極52可經放置於主動層40上方。閘極絕緣層54可經放置於閘極電極52與主動層40之間。源極/汲極區56可在閘極電極52之相對側處形成於主動層40中。間隔結構58可經放置於閘極電極52之相對側上。在一些替代實施例中,半導體組件50可包含一RF裝置(諸如一RF開關或類似者)。 若一RF訊號之週期短於多數(majority)載子緩衝時間,則接著半導體基板10中之多數載子可不回應於RF訊號。多數載子可呈現被固著,且半導體基板10可表現為一介電質。然而,矽具有可在一些RF應用中產生不期望的行為之特定特性。例如,高電阻率半導體基板10中之摻雜位準係非常低的或不存在的。因此,半導體基板10之表面處之氧化物電荷或半導體基板10中之一弱電場可誘發一反轉或累積層,該反轉或累積層可用作半導體基板10之表面處之一表面傳導層。在半導體基板10之表面上方橫穿之RF訊號可調變表面傳導層,其可導致非線性電容、非線性傳導性或兩者,影響半導體基板10與其他上覆層之間之RF相互作用。非線性特性可引入RF訊號中可超過可允許限制之諧波失真。多層多晶矽結構20可經組態為一多層富阱結構。多層多晶矽結構20之多晶矽層包含具有差排之晶體缺陷。晶體缺陷經組態以捕獲半導體基板10及/或埋入氧化物層30中之載子。藉由將載子捕獲在多層多晶矽結構20之晶體缺陷內,可減輕可導致對RF訊號之非線性失真之寄生表面傳導。在一些實施例中,SOI基板2可經歷一些退火操作或經歷高溫。多層多晶矽結構20之原生氧化物層22經組態以阻擋多晶矽層之晶粒彼此鄰接,且因此可幫助在退火操作期間或在高溫下抑制晶粒之再生長。憑藉原生氧化物層22,可將多晶矽層之晶粒控制為具有較小晶粒尺寸及微粒結構,且因此可增大多層多晶矽結構20之陷阱密度。 在本揭露之一些實施例中,SOI基板之多層多晶矽結構可經組態為可實質上在射頻(RF)頻率下將一表面傳導層固定在半導體基板之表面處之一多層富阱結構。多層富阱結構可具有捕獲來自表面傳導層之載子之一高密度陷阱。來自陷阱之平均釋放時間可長於RF訊號之週期,藉此有效地固定表面傳導層,其可實質上防止歸因於RF訊號之電容及電感變化。因此,可減小或減輕RF訊號之諧波失真。原生氧化物層可經組態為可阻擋富阱層之晶粒彼此鄰接之一阻障層。因此,阻障層可幫助抑制多晶矽之晶粒之再生長,並增大多層富阱結構之陷阱密度。 在一項例示性態樣中,一絕緣層覆矽(SOI)基板包含一半導體基板及一多層多晶矽結構。多層多晶矽結構經放置於半導體基板上方。多層多晶矽結構包含彼此堆疊之複數個多晶矽層,及在多晶矽層之各相鄰對之間之一原生氧化物層。 在另一態樣中,一半導體裝置包含一絕緣層覆矽(SOI)基板及SOI基板上方之一半導體組件。SOI基板包含一高電阻率處置基板、一多層富阱結構及一絕緣層。多層富阱結構係在高電阻率處置基板上方。多層富阱結構包含彼此堆疊之複數個富阱層,及在富阱層之各相鄰對之間之一或多個阻障層。絕緣層係在多層富阱結構上方。 在又另一態樣中,用於製造一絕緣層覆矽(SOI)基板之一方法包含以下操作。接納一半導體基板。使一多層多晶矽結構形成於半導體基板上方。多層多晶矽結構包含彼此堆疊之複數個多晶矽層,及在多晶矽層之各相鄰對之間之一原生氧化物層。使一埋入氧化物層及一主動層形成於多層多晶矽結構上方。 前文概述數項實施例之結構,使得熟習此項技術者可更佳理解本揭露之態樣。熟習此項技術者應明白,其等可容易將本揭露用作設計或修改用於實行本文中介紹之實施例之相同目的及/或達成相同優點之其他程序及結構之一基礎。熟習此項技術者亦應認識到,此等等效構造未脫離本揭露之精神及範疇,且其等可在不脫離本揭露之精神及範疇之情況下在本文中進行各種改變、置換及更改。
1‧‧‧絕緣層覆矽(SOI)基板2‧‧‧絕緣層覆矽(SOI)基板10‧‧‧半導體基板20‧‧‧多層多晶矽結構22‧‧‧原生氧化物層30‧‧‧埋入氧化物層40‧‧‧主動層50‧‧‧半導體組件52‧‧‧閘極電極54‧‧‧閘極絕緣層56‧‧‧源極/汲極區58‧‧‧間隔結構60‧‧‧半導體裝置100‧‧‧方法101‧‧‧第一表面102‧‧‧第二表面110‧‧‧操作120‧‧‧操作122‧‧‧子操作124‧‧‧子操作126‧‧‧子操作130‧‧‧操作201‧‧‧第一多晶矽層202‧‧‧第二多晶矽層203‧‧‧第三多晶矽層204‧‧‧第四多晶矽層
在結合附圖閱讀時,自以下詳細描述最佳理解本揭露之實施例之態樣。應注意,根據產業中之標準實踐,各個結構未按比例繪製。實際上,為了論述的清楚起見,可任意增大或減小各個結構之尺寸。 圖1係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一絕緣層覆矽(SOI)基板之一方法之一流程圖。 圖2係繪示根據本揭露之一或多項實施例之各種態樣之用於製造一多層多晶矽結構之一操作之一流程圖。 圖3A、圖3B、圖3C、圖3D、圖3E、圖3F及圖3G係根據本揭露之一或多項實施例之製造一絕緣層覆矽(SOI)基板之各種操作之一者處之示意圖。 圖4係根據本揭露之一些實施例之一半導體裝置之一示意圖。
1‧‧‧絕緣層覆矽(SOI)基板
10‧‧‧半導體基板
20‧‧‧多層多晶矽結構
22‧‧‧原生氧化物層
30‧‧‧埋入氧化物層
40‧‧‧主動層
101‧‧‧第一表面
102‧‧‧第二表面
201‧‧‧第一多晶矽層
202‧‧‧第二多晶矽層
203‧‧‧第三多晶矽層
204‧‧‧第四多晶矽層
Claims (10)
- 一種絕緣層覆矽(SOI)基板,其包括:一半導體基板;一多層多晶矽結構,其在該半導體基板上方,該多層多晶矽結構包括:複數個多晶矽層,其等彼此堆疊,其中該等多晶矽層包括N型摻雜多晶矽層或P型摻雜多晶矽層,該等多晶矽層包括接近該半導體基板的一第一多晶矽層;及一原生氧化物層,其在該複數個多晶矽層之各相鄰對之間;一中間層,其在該第一多晶矽層與該半導體基板之間,其中該中間層不干擾該第一多晶矽層與該半導體基板之間之載子轉移;及一埋入氧化物層和一主動層,其在該多層多晶矽結構上方,其中該主動層鄰接該埋入氧化物層。
- 如請求項1之SOI基板,其進一步包括一半導體組件,其放置於該主動層上方。
- 如請求項1之SOI基板,其中該等多晶矽層之一數目在自2至6之範圍內。
- 如請求項1之SOI基板,其中該等多晶矽層之各者之一晶粒尺寸小於或等於0.1微米。
- 如請求項4之SOI基板,其中該等多晶矽層之各者之該晶粒尺寸實質上在自0.03微米至0.1微米之範圍內。
- 如請求項1之SOI基板,其中該多層多晶矽結構之一厚度小於或等於3微米。
- 如請求項6之SOI基板,其中該多層多晶矽結構之該厚度實質上在自0.6微米至3微米之範圍內。
- 如請求項1之SOI基板,其中該一或多個原生氧化物層之一厚度實質上在自0.5奈米至1.5奈米之範圍內。
- 一種半導體裝置,其包括:一絕緣層覆矽(SOI)基板,其包括:一高電阻率處置基板;一多層富阱結構,其在該高電阻率處置基板上方,該多層富阱結構包括:複數個富阱層,其等彼此堆疊,其中該等富阱層不摻雜碳,該等富阱層包括接近該高電阻率處置基板的一第一富阱層;及一阻障層,其在該複數個富阱層之各相鄰對之間;一中間層,其在該第一富阱層與該高電阻率處置基板之間,其中該中間層不干擾該第一富阱層與該高電阻率處置基板之間之載子轉 移;一絕緣層及一主動層,其在該多層富阱結構上方,其中該主動層鄰接該絕緣層;及一半導體組件,其在該SOI基板上方。
- 一種用於製造一絕緣層覆矽(SOI)基板之方法,其包括:接納一半導體基板;使一多層多晶矽結構及一中間層形成於該半導體基板上方,其中該多層多晶矽結構包括:複數個多晶矽層,其等彼此堆疊,其中該等多晶矽層包括N型摻雜多晶矽層或P型摻雜多晶矽層,該等多晶矽層包括接近該半導體基板的一第一多晶矽層,其中該中間層在該第一多晶矽層與該半導體基板之間,該中間層不干擾該第一多晶矽層與該半導體基板之間之載子轉移;及一原生氧化物層,其在該複數個多晶矽層之各相鄰對之間;及使一埋入氧化物層及一主動層形成於該多層多晶矽結構上方,其中該主動層鄰接該埋入氧化物層。
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