TWI775235B - 橫向雙擴散金氧半電晶體以及n型通道橫向雙擴散金氧半電晶體 - Google Patents

橫向雙擴散金氧半電晶體以及n型通道橫向雙擴散金氧半電晶體 Download PDF

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TWI775235B
TWI775235B TW109143358A TW109143358A TWI775235B TW I775235 B TWI775235 B TW I775235B TW 109143358 A TW109143358 A TW 109143358A TW 109143358 A TW109143358 A TW 109143358A TW I775235 B TWI775235 B TW I775235B
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ldmos
ldmos transistor
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愛德華 約翰 柯伊尼
艾倫 布蘭尼克
約翰 Ｐ 梅斯凱爾
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愛爾蘭商亞德諾半導體國際無限公司
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Abstract

本發明提供一種n型通道LDMOS電晶體之改良結構，用以避免閘極氧化層於LDMOS電晶體操作過程中發生破斷。該LDMOS電晶體包含一介電隔離結構，其可於實體上將包含一寄生NPN電晶體之區域與因弱碰撞電離(impact ionization)而產生電洞電流之區域隔離，後者即為該LDMOS電晶體之延伸汲極區域。於本發明之一種實施例中，係於上述二區域間設置一垂直深溝而達成實體隔離。本發明之其他實施例亦關於藉由減少該寄生NPN電晶體之增益及該背閘極電阻，而進一步改善該LDMOS電晶體之強健度。

Description

橫向雙擴散金氧半電晶體以及n型通道橫向雙擴散金氧半電晶 體 相關申請之交互引用
本發明主張於2019年12月12日提出之美國臨時專利申請案No.62/947,452之優先權，於此以參考文獻方式全部合併入本文中。
本發明係關於一種橫向雙擴散金氧半(lateral double-diffused metal oxide semiconductor，LDMOS)電晶體。更詳而言之，本發明係關於一種具有改良結構而能改善其操作期間的強健度之n型通道LDMOS電晶體。
高電壓積體電路或HVIC主要用於電源轉換應用。橫向雙擴散MOS電晶體或LDMOS係HVIC之常用組件。然而，實需一種經改良的LDMOS電晶體的強健元件結構，使其在操作期間具有較佳的可靠性。
本發明係有關於一種具有改良結構的n型通道LDMOS電晶體，以改善電晶體於其操作期間的強健度。特別地，本發明有關於一種具有改良結構的n型通道LDMOS電晶體，而能完全避免或至少減少電晶體於操作期間的閘極氧化層破斷現象。
一種橫向n型通道LDMOS電晶體之改良結構被提供，以可避免電晶體在其操作期間發生閘極氧化層破斷之現象。所述LDMOS電晶體所包含之一介電隔離結構，其可在實體上使包含一寄生NPN電晶體之區域與會因弱碰撞電離(impact ionization)而產生電洞電流之區域(即LDMOS電晶體之延伸汲極區域)隔開。根據本發明之一實施例，可於上述二區域之間設置垂直深溝而達成。本發明之其他實施例亦透過降低寄生NPN電晶體之增益以及背閘極電阻而進一步改善LDMOS電晶體的強健度。
根據本發明之一實施例，一種LDMOS電晶體包含：一汲極；一閘極；一源極；以及一背閘極；其中，該LDMOS電晶體進一步包含一隔離結構，該隔離結構係配置為實體上將包含該LDMOS電晶體之該汲極之一第一區域與於使用時具有一寄生雙極接面電晶體之一第二區域隔離。
根據本發明之另一實施例，一種橫向n型通道LDMOS電晶體包含：一汲極；一閘極；一源極；以及一背閘極；其中該橫向n型通道LDMOS電晶體進一步包含：一場區氧化區域，橫向延伸於該汲極與該閘極間；一閘極氧化區域，橫向延伸於該場區氧化區域之一側邊緣與該源極之間；一p型摻雜區域，可於使用時減少寄生雙極電晶體之增益，該p型摻雜區域係嵌入於位在該源極及該背閘極下方之一p型井區域內，其中，該p型摻雜區域包含由該p型井區域之剩餘部分而與該源極及該背閘極隔離之一內埋p型摻雜層，以及其中，該內埋 p型摻雜層之一側邊緣係對齊於該閘極接近位於該場區氧化區域與該閘極氧化區域間之過渡區域之一側邊緣。
根據本發明之又一實施例，一種橫向n型通道LDMOS電晶體包含：一第一區域，配置為於使用時操作如同一虛擬之接面場效電晶體(JFET)；一一第二區域，配置為於使用時操作如同一虛擬之金氧半場效電晶體(MOSFET)；其中，該第一區域於使用中因弱碰撞電離而產生一第一電流，其中，該第二區域於使用中因第二區域內之寄生NPN電晶體而產生一第二電流，以及其中，該第一區域與該第二區域隔離，使得該第一電流不與該第二電流成正比。
100:LDMOS元件
101:氧化層上覆矽基板
101a:塊狀矽晶圓
101b:內埋氧化層/BOX層
102:摻雜矽區域
102a:內埋p型摻雜矽層
102b:p型摻雜磊晶生長矽層
103:n型井區域
103a:內埋n型摻雜區域
103b:n型摻雜區域
104:p型井區域
105:閘極
106:背閘極
106a:p型摻雜區域
106b:背閘極端子
107:源極
107a:n型摻雜區域
107b:金屬孔
107b:源極端子
108:汲極
108a:n型摻雜區域
108b:金屬孔
110:介電區域
110a,110b:LOCOS場區氧化區域
110c:閘極氧化區域
112:降低表面電場結構
112a:第一場板
112b:第二場板
114:導電通道
300:測試電路
301:n型通道LDMOS電晶體
302:NPN雙極接面電晶體/寄生NPN雙極接面電晶體
303:電容器
304:電阻器
305:PNP雙極接面電晶體
400:LDMOS元件
401:第一區域
401a:p型基板
401b:n型井區域
401c:汲極
401d:第二n型摻雜區域
401e:多晶矽結構
401f:p型摻雜背閘極
401g:降低表面電場結構
402:第二區域
402a:p型基板
402b:p型井區域
402c:第一n型摻雜區域
402d:第二n型摻雜區域/源極
402e:閘極結構
402e(i):多晶矽閘極層
402e(ii):閘極氧化層
402f:p型摻雜背閘極
403:垂直深溝
404:第一側
405:LOCOS氧化層
500:LDMOS元件
500a:第一側
500b:第二側
501:內埋氧化層/BOX層
502a:p型摻雜矽層
502b:p型磊晶層
503:n型井區域
503a:內埋n型摻雜區域
503b:n型摻雜區域
504:p型井區域
504a:內埋p型摻雜區域
504b:p型摻雜區域
505:深溝
506:汲極
507:源極
508:背閘極
509:閘極
510a:LOCOS場區氧化區域
510b:過渡區域
510c:薄閘極氧化區域
511:接面
600:LDMOS元件
601:內埋氧化層/BOX層
602a:p型摻雜矽層
602b:p型摻雜磊晶生長矽層
603:n型井區域
604a:內埋p型摻雜區域
604b:p型井區域
604c:p型埋置區域
607:源極
608:背閘極
圖1A係本發明之n型通道LDMOS元件之剖視圖。
圖1B係於圖1A之元件操作時發生的閘極氧化層破斷之示意圖。
圖2係顯示圖1A之元件之不同區域之摻雜物濃度分布。
圖3A係LDMOS元件之參考電路圖，其寄生NPN雙極電晶體為關斷狀態。
圖3B係LDMOS元件之電路圖，以啟動寄生NPN雙極電晶體。
圖3C(i)係LDMOS元件之剖視圖，說明於LDMOS元件之暫態模式操作期間，以PNP電晶體做為背閘極電流之源極之概念。
圖3C(ii)係圖3C(i)所述概念之電路圖。
圖4A係本發明第一實施例之n型通道LDMOS元件之剖視圖。
圖4B係顯示圖4A之LDMOS元件之電性連接。
圖5A係本發明另一實施例之n型通道LDMOS元件之剖視圖。
圖5B係顯示圖5之LDMOS元件中不同區域之摻雜物濃度分布。
圖6係本發明又一實施例之n型通道LDMOS元件之剖視圖。
發明人已經認識到，當n型通道LDMOS元件工作時，該元件中可能發生閘極氧化層破斷，並且可導致元件的最終故障。這種類型的破斷不同於作為製造缺陷的閘極氧化層破斷，這是因為前者係發生在元件的操作期間。因此，實需一種經改良的強健元件結構，以解決n在型通道LDMOS元件的操作期間閘極氧化層破斷的問題。
本發明係關於一種n型通道LDMOS電晶體，其具有改良結構而能夠改善該電晶體於操作期間的強健度。詳言之，本發明係關於一種n型通道LDMOS電晶體，其具有改良結構而能完全避免或至少減少該電晶體於操作期間的閘極氧化層破斷現象。藉由修改LDMOS電晶體中個別結構之尺寸及/或準齊狀態，可減少閘極氧化層破斷之發生。但本發明之發明人發現此種解決方案在設計製造方面極受侷限。本發明之發明人發現閘極氧化層破斷之發生係與LDMOS電晶體在暫態模式操作時寄生NPN雙極電晶體之啟動有關。詳言之，在不受任何理論的拘束下，本發明之發明人發現，在暫態模式下，由於弱碰撞電離之作用，電洞電流密度會與來自寄生NPN雙極電晶體之電流成正比，而正是一在高電場下穿隧閘極氧化層之電洞電流，導致氧化層破斷。本發明之發明人更發現，在LDMOS電晶體之暫態操作模式期間(例如在脈衝干擾(glitch)期間)，因弱碰撞電離產生之電洞電流可理解為是由一PNP電晶體之射極發射而出。此PNP雙極性接面電晶體可理解為與該寄生NPN雙極性接面電晶體共同作用，而產生與寄生NPN雙極性接面電晶體所產生之電流INPN成正比之電流IPNP。
為避免或至少減少在暫態模式下閘極氧化層之破斷，本發明之發明人對LDMOS電晶體之結構進行改良，從而預防上述機制或至少降低其發生之可能性。
LDMOS電晶體之結構可經改良，使得當LDMOS電晶體於暫態模式下操作並因例如電源供應器中之尖波或脈衝干擾而啟動的寄生NPN雙極接面電晶體，其增益減少。在本發明之一實施例中，上述結構是在LDMOS電晶體之源極及背閘極下方之一p型井區域內提供一內埋p型摻雜區域。所述內埋p型摻雜區域可將摻雜物添加至寄生NPN雙極接面電晶體之基極，藉此減少寄生NPN雙極接面電晶體之增益。加入上述之內埋p型摻雜區域亦有助於降低背閘極電阻，從而降低寄生NPN雙極接面電晶體在暫態模式下啟動之可能性。
在另一實施例中，係將經高度摻雜之p型摻雜區域直接設置於源極及背閘極下方，使其形成與源極之n型摻雜區域及背閘極之p型摻雜區域之接面。如此修改之LDMOS電晶體結構亦能夠減少寄生NPN雙極電晶體之增益並降低背閘極電阻，從而降低寄生雙極電晶體在暫態模式下啟動之可能性。
然更重要者，本發明之發明人設計出一種改良方式，透過將包含寄生NPN電晶體之區域與產生電洞電流之區域(即LDMOS電晶體之延伸汲極區域)實體上隔離，達到避免閘極氧化層破斷之功效。根據本發明之一種實施例，可藉由在該二區域之間設置一垂直深溝而達到隔離之目的。此實施例之另一優點在於所述該第二區域並不必須鄰接該第一區域，且可設置於實現LDMOS元件之晶片上之理想位置，藉此予以更高之晶片設計自由度，特別是在嘗試優化已知晶片面積之利用時。
如在此所稱，「上」、「下」、「於其一側」等等用語，意指如圖式中所設定方向之組件或區域，且不應構成對於實際元件之限制。
圖1A為在氧化層上覆矽基板101之一n型通道LDMOS元件100之剖視圖。二氧化矽介電層101b(內埋氧化層或BOX層)覆蓋於塊狀矽晶圓101a上。經摻雜矽區域102，在圖1A中為p型摻雜區域或p型基板，覆蓋於該內埋氧化層101b上。所述p型基板可為多層基板，包含直接設置於內埋氧化層101b上方之一內埋p型摻雜矽層102a以及直接設置於內埋p型摻雜矽層102a上方之一p型摻雜磊晶生長矽層102b。LDMOS元件進一步包含一部份內嵌於該p型基板中之一n型摻雜區域或一n型井區域103。所述元件亦包含一p型摻雜區域或一p型井區域104，其亦內嵌於該p型基板中，其中該p型井區域係與該n型井區域103橫向毗鄰。如下文將詳述者，n型井區域103形成該n型通道LDMOS元件之延伸汲極漂移區域。n型井區域103可為多層區域，包含位於該p型基板中之一內埋n型摻雜區域103a及位於該內埋n型摻雜層103a上方之一n型摻雜區域103b。圖2顯示圖1A之元件中不同區域之摻雜物濃度分布。
所述元件更包括至少在該元件之一側的一介電深溝，其中該介電深溝係與該元件之塊狀矽區域隔離。在圖1A中，所述元件包含一接近p型井區域104之介電深溝。
所述元件包含一閘極105、一背閘極106、一源極107及一汲極108。
如圖1A所示，源極107及汲極108位於閘極105之橫向對立兩側。背閘極106係與源極107橫向毗鄰。源極107包含內嵌於p型井區域104之頂部表面中之一n型摻雜區域107a，其中n型摻雜區域107a之整體摻雜物濃度高於該n型井區域103。背閘極106包含內嵌於p型井區域104之頂部表面中且與n型摻雜區域 107a橫向毗鄰之一p型摻雜區域106a，其中p型摻雜區域106a之整體摻雜物濃度高於p型井區域104。汲極108包含內嵌於n型井區域103之頂部表面中之一n型摻雜區域108a。n型摻雜區域108a之整體摻雜物濃度高於n型井區域103。
所述元件亦包括在頂部表面的一介電區域110。對源極107之電接點及對汲極108之電接點係分別以金屬孔107b、108b所構成，所述金屬孔107b、108b延伸通過介電層中之孔隙，分別接觸源極107之區域107a及汲極108之區域108a。介電區域110，較佳者包括氧化層，包含LOCOS場區氧化區域110a、110b及閘極氧化區域110c。
閘極105包含延伸在該n型井區域103一部份及該p型井區域104一部份上方之一多晶矽閘極層，LOCOS場區氧化區域110a及閘極氧化區域110c將該多晶矽閘極層與該n型井區域及該p型井區域分離。
圖1A亦顯示一降低表面電場(resurf)結構(場板結構)，其所包含之一第一場板112a具有一預設長度，內嵌於該介電區域110內，且電性連接於延伸通過介電區域110而接觸該多晶矽閘極層之一金屬孔。所述resurf結構進一步包含一第二場板112b，其在介電區域110表面具有一預設長度。第二場板112b係位於該第一場板112a上方，且經由延伸通過該介電區域110之金屬孔而連接於該第一場板112a。圖1A之第一場板112a亦具備閘極接點之功能。
圖1A中之LOCOS場區氧化區域110a具有一預設橫向距離，延伸於汲極與閘極之間。LOCOS場區氧化區域110a具有一預設深度，垂直延伸通過該元件之頂部表面進入n型井區域103。該閘極氧化區域110c在該元件表面上方橫向延伸於LOCOS場區氧化區域110a之一端(鳥嘴)與源極107之n型摻雜區域107a之間。所述閘極氧化區域厚度小於該場區氧化區域。該閘極氧化區域110c 之厚度可較該LOCOS場區氧化區域110a之厚度小至少兩個數量級。例如，若閘極氧化區域之厚度為至少15nm，則LOCOS場區氧化區域110a之厚度可為至少400nm。
於特定應用中，源極端子107b係與背閘極端子106b為電性短路，如圖1A所示，且此二端子係保持於相同電位，以免一寄生NPN雙極電晶體啟動。
如可見於圖1A者，於閘極施加電位可在源極107與汲極108之間形成一導電反轉層或一導電通道114。後將汲極108相對於源極107偏置，可使得多數載體或電子自源極107經由導電通道114移動至汲極108。圖1A亦顯示一空乏區域產生，其延伸進入通道區域，且亦通過輕度摻雜延伸漂移區域，稀釋內部電場區，並藉此允許高電壓操作。
空乏區域所產生之內部電場區低於啟動碰撞電離鏈反應進而定義該元件之崩潰電壓VBD所需之臨界電場。但通道電流與延伸漂移區域上方電場區之結合會造成弱碰撞電離，因此於一n型通道LDMOS元件產生多數載體或電洞；此電洞電流或背閘極電流Ibg自該汲極漂移區域延朝向該源極/背閘極之方向流動。
閘極氧化層之破斷取決於上述電洞電流之密度及閘極氧化區域110c上電場區之強度。閘極氧化層在LDMOS元件的暫態模式操作時因其上之電場而遭來自背閘極電流之電洞鑿通進而破斷，如圖1B所示。
於該LDMOS元件之特定應用中，源極端子107b對背閘極端子106b之短路可預防寄生NPN雙極接面電晶體啟動。然而，即便有此短路連接，寄生NPN雙極電晶體仍可能因脈衝干擾(例如因電源供應電壓中尖波所造成之 電壓過衝)而啟動。在LDMOS元件操作之暫態模式期間，因弱碰撞電離而產生之電洞電流會與注入至汲極之電子數量成正比。
本發明之發明人利用圖3A及3B所示之測試電路300模擬LDMOS電晶體，以重現LDMOS元件在暫態模式操作期間發生之閘極氧化層破斷。此測試電路300包含一n型通道LDMOS電晶體301，其耦接於一NPN雙極接面電晶體302，其中，電晶體302代表於n型通道LDMOS電晶體操作時可啟動之寄生NPN雙極電晶體。測試電路300亦包含用於模擬背閘極電容之一電容器303以及用於模擬背閘極電阻之一電阻器304。圖3A顯示測試電路300中之寄生NPN雙極電晶體處於「關斷(off)」模式，即並未啟動。圖3B顯示測試電路300中之寄生NPN雙極電晶體為「開通(on)」模式，亦即，圖3B表示n型通道LDMOS電晶體中之寄生NPN雙極電晶體於元件操作期間被啟動。
利用測試電路300，本發明之發明人啟動寄生NPN雙極電晶體302並觀察到電洞密度相較於參考電路中之對應電洞密度而大幅增加，特別是在場區氧化區域110a與閘極氧化區域110c(如圖1A所示)間之過渡區域。在利用圖3B之測試電路300進行測試時，本發明之發明人發現寄生NPN雙極接面電晶體若遭強制啟動，會使場區氧化層到閘極氧化層間之過渡區域電洞密度較圖3A參考電路中寄生雙極接面電晶體為關斷狀態時增加三個數量級。於圖3B之測試電路中，本發明觀察到由場區氧化層至閘極氧化層之過渡區域中發生閘極氧化層破斷現象。
圖3C(i)為圖1A所示LDMOS電晶體之簡化剖視圖。本發明之發明人之重要發現為，LDMOS元件於暫態操作模式下(例如於脈衝干擾發生時)，可將因弱碰撞電離而產生之電洞電流理解為由一PNP電晶體之射極所發出，如 圖3C(i)之剖視圖所示。圖3C(ii)之測試電路300可用於模擬LDMOS元件之暫態模式操作。如圖3C(ii)所示，可將PNP雙極接面電晶體305理解為與寄生NPN雙極接面電晶體302共同運作而產生流IPNP，其流向與寄生NPN雙極接面電晶體302所產生之電流INPN相反。PNP雙極電晶體305之射極因此可視為電洞之射極，且此二雙極接面電晶體302、305共同作用，如圖3C(ii)所示，使得導致少數載子流向源極之弱碰撞電離效應與INPN成正比。
本發明之發明人發現該元件於暫態模式操作期間會發生閘極氧化層破斷，特別是當此二雙極電晶體之增益積超過1時。為解決此一問題，本發明之發明人對LDMOS元件進行修改，如下文詳述。
以下將參照圖4-6說明本發明之各種實施例，其中LDMOS電晶體結構係經改良，以於LDMOS電晶體之暫態模式操作時避免或至少減少閘極氧化層之破斷現象。
圖4A係根據本發明LDMOS元件400之第一實施例。圖4A所描繪LDMOS元件之設計目的在於避免暫態模式操作時發生上述之閘極氧化層破斷問題。LDMOS元件400具有一第一區域401及一第二區域402，其中，該第一區域401與該第二區域402係由一垂直深溝403隔開。深溝403與此二區域為介電隔離，且其中填充有一介電層，較佳者為氧化層。
第一區域401形成於一氧化層上覆矽基板(圖未示)之上。第一區域包含一p型基板401a，其與上述圖1A元件之p型基板相仿。第一區域401更包含位在該p型基板401a上方之一n型井區域401b，其係與上述圖1A元件之n型井區域結構相仿。
於圖4A中，汲極401c接近元件之第一側404。第一區域401更包含接近該深溝之一第二n型摻雜區域401d。n型井區域401b自該汲極401c橫向延伸至該第二n型摻雜區域401d。汲極401c及第二n型摻雜區域401d均內嵌於n型井區域401b之頂部表面。
第一區域401亦包含具有預設長度之一多晶矽結構401e，且由一介電層，較佳者為一LOCOS氧化層405，將多晶矽結構401e與元件之頂部表面隔開，特別是與n型井區域401b之頂部表面隔開。第一區域401進一步包含一p型摻雜背閘極401f，其中該p型摻雜背閘極401f橫向位於多晶矽結構401e與第二n型摻雜區域401d之間，p型摻雜背閘極401f經由介電區域而在橫向上與多晶矽結構401e及第二n型摻雜區域401d分離，所述介電區域例如可為LOCOS氧化層405。
第二區域402亦形成於該氧化層上覆矽基板(圖未示)上。第二區域402包含一p型基板402a。第二區域402之p型基板402a在厚度上大於第一區域401之p型基板401a。於圖4A之元件中，分屬第一區域401及第二區域402之p型基板401a、402a各包含一位於BOX層上之內埋p型摻雜矽層，以及直接設置於內埋p型摻雜矽層上方之一磊晶生長p型摻雜矽層。在圖4A中，第二區域402之p型基板402a之磊晶生長p型摻雜層較第一區域401之p型基板401a之磊晶生長p型摻雜層更厚。第二區域402進一步包含直接設置於p型基板402a上方之p型摻雜區域或p型井區域402b。
第二區域402在一閘極結構402e之橫向對立兩側具有一第一n型摻雜區域402c及一第二n型摻雜區域或源極402d，該閘極結構402e包含設於閘極氧化層402e(ii)上之多晶矽閘極層402e(i)，其中，該多晶矽閘極層402e(i) 係由閘極氧化層402e(ii)而與p型井區域402b的表面隔開，與圖1A中元件之閘極相仿。第二區域402之第一n型摻雜區域402c係橫向位於深溝403與閘極結構402e之間。源極402d橫向位於閘極結構402e與一p型摻雜背閘極402f之間，其中，該源極402d係經由介電區域而橫向與閘極結構402e及p型摻雜背閘極402f隔開，所述介電區域例如可為LOCOS氧化層。
所述元件亦包含設於元件頂部表面及多晶矽結構上方之介電層(圖未示)，與圖1A所示元件相仿。上述LOCOS氧化層亦構成介電層之一部份。連通二區域中汲極、多晶矽結構、背閘極及n型摻雜區域之電接點可利用通過介電層中的孔隙而延伸之金屬孔所形成。該元件亦可包含一降低表面電場結構(場板結構)401g，其與圖1A中元件之降低表面電場結構112相仿。
圖4B為圖4A之LDMOS電晶體之簡化圖，顯示圖4A中LDMOS電晶體之不同區域間的電性連接。圖4B顯示第二區域402之背閘極402f電性耦接於第一區域401之背閘極401f、第一區域401之p型基板401a、第一區域之多晶矽結構401e以及第一區域401中降低表面電場結構401g之場板。第一區域401之第二n型摻雜區域401d電性耦接於第二區域402之第一n型摻雜區域402c。圖4B中LDMOS電晶體之背閘極端子位於第二區域402之背閘極402f，如圖4B所示。圖4B中LDMOS電晶體之汲極端子位於第一區域401之汲極401c，如圖4B所示。圖4B中LDMOS電晶體之閘極端子位於第二區域402之閘極402e(i)，如圖4B所示。圖4B中LDMOS電晶體之源極端子位於第二區域402之源極402d，如圖4B所示。在某些實施例中，源極端子與背閘極端子可為短路。
圖4A亦顯示在LDMOS電晶體之操作期間，第一區域401之作用如同一有效高電壓接面場效電晶體(JFET)，且第二區域402之作用如同一有效 低電壓金氧半場效電晶體(MOSFET)。此高電壓JFET之下閘極即是該p型基板401a之磊晶生長p型摻雜矽層(P型磊晶層)，且是與作為有效高電壓JFET之上閘極之背閘極401f保持在相同電位。如圖4A中之虛線所示，空乏區域與有效高電壓JFET之上電極方及下閘極隔開。空乏區域可配置為以一夾止電壓(pinch-off voltage)使該汲極401c夾止(pinch-off)於JFET之第二n型摻雜區域401d或有效源極，所述夾止電壓係由n型井區域401b之摻雜物濃度所定義。如此能夠保護JFET之有效源極401d，使其不受施用於汲極之高電壓電位影響，且使n型井區域產生分壓器之作用。電子流(藍色虛線)自該JFET源極端子(或第一區域401之第二n型摻雜區域401d)至該汲極端子在空乏區域之間流動，如圖4B所示。
本發明發現圖4A之元件結構並不會出現如上所述，電洞電流與暫態模式下寄生NPN雙極接面電晶體之電流INPN成正比之問題。究其原因，首先是由於，在圖4A之元件，垂直深溝403使寄生NPN雙極電晶體與可能因弱碰撞電離而產生電洞電流之n型井區域相互隔離。其次，在圖4A之元件中，因弱碰撞電離所產生之電洞電流從背閘極接點降至地端。因此，圖4A之元件結構能夠克服在n型通道LDMOS元件於暫態模式操作期間發生閘極氧化層破斷之問題。
在實施圖4A之LDMOS元件之晶片中，第二區域402並不必須在位置上毗鄰第一區域401，即是使用深溝403使第二區域402之實體結構與第一區域401介電隔離，因此，只要此二區域間仍能構成如上所述之外部電性連接，第二區域402可視需要(例如優化晶片面積之利用)而設置於其他位置，如此一來，在設計上具有更大之自由度。
圖5A顯示本發明LDMOS元件500之另一實施例。此元件結構與圖1A之LDMOS元件相仿，但在圖5A之元件中，n型井區域503及p型井區域504皆為多層區域。n型井區域503包含一內埋n型摻雜區域503a及位在該內埋n型摻雜區域上方之另一n型摻雜區域503b。多層p型井區域504包含直接設置於p型磊晶層502b上方之內埋p型摻雜區域504a，以及位在該內埋p型摻雜區域504a上方之一p型摻雜區域504b。n型井區域503接近該元件之第一側500a。p型井區域504接近設於該元件之第二側500b(與第一側500a對立)之深溝505。在圖5A之元件500中，內埋n型摻雜區域503a及內埋p型摻雜區域504a是直接位於p型基板之p型磊晶層502b上方。該n型摻雜區域503b在內埋p型摻雜區域504a與內埋n型摻雜區域503a區域間之接面511上，沿朝向深溝505之方向延伸一預設長度。
圖5B顯示圖5A之元件中不同p型摻雜區域之摻雜物濃度分布。
本發明之發明人發現加設內埋p型摻雜區域504a有助於使可在LDMOS元件暫態模式操作期間被啟動之寄生NPN雙極電晶體的增益降低。內埋p型摻雜區域504a能夠將摻雜物加入寄生NPN雙極電晶體之基極，從而降低其增益。有鑑於上述關於閘極氧化層在暫態模式中破斷問題之討論，可知若降低NPN電晶體之增益，即能夠使與NPN電晶體所產生電流成比例關係之電洞電流密度降低。加設內埋p型摻雜區域504a之另一優點在於該埋層有助於降低背閘極電阻。如此可避免電源供應器中之任何暫態脈衝干擾造成寄生雙極電晶體之啟動，藉此提升元件之強健度。由於上述圖5A元件結構之優點，LDMOS元件於暫態模式操作時，較不易發生閘極氧化層破斷之現象。
於特定應用中，如亦可見於圖5A者，內埋p型摻雜區域504a之一側邊緣，或說內埋n型摻雜區域503a與內埋p型摻雜層區域之接面511，是對齊靠近由LOCOS場區氧化區域510a所定義之鳥嘴的閘極多晶矽層之一側邊緣，其中該鳥嘴亦形成LOCOS場區氧化區域510a與薄閘極氧化區域510c間之過渡區域510b。上述對齊可於製造該元件時達成，具體方法是將內埋p型摻雜區域504a之邊緣，或說是內埋n型摻雜區域503a與內埋p型摻雜區域之接面511，對齊於閘極光罩之一側邊緣。本發明之發明人發現，如此使內埋p型摻雜區域504a之邊緣對齊於閘極光罩可進一步提升減少寄生NPN雙極電晶體增益之效果。本發明之發明人發現，若將內埋p型摻雜區域504a邊緣與閘極光罩之一側邊緣對齊時之公差控制在約0.5μm至1μm，且更佳者為約1μm，可避免自內埋p型摻雜區域504a發生擴散。
圖6為根據本發明LDMOS元件600之又一實施例。圖6之剖視圖為圖5A剖視圖之簡化版本，然不同處在於，圖6包含位於該LDMOS元件之源極及背閘極下方之一p型埋置區域604c。該埋置區域之摻雜物濃度高於周圍p型井區域604b，較佳者，該埋置區域之整體摻雜物濃度為1E18cm-3。埋置區域604c可如圖6所示般與內埋p型摻雜區域604a結合使用，或以其本身單獨使用。藉由利用動能在n型通道LDMOS元件600之源極607及背閘極608下方埋置摻雜物，本發明之發明人發現，透過調整P型埋置區域604c之位置，能夠使得沿反轉通道(見圖1A之導電通道114)之MOS作用在橫向上不受影響。但在寄生NPN電晶體之基極中額外p型摻雜物之作用下，暫態模式期間之垂直寄生雙極作用可大幅減少。再者，源極607上之高度摻雜區域使其不致因暫態背閘極電 流所造成之電位下降受到影響。如此一來，由於埋置區域亦有助於減少背閘極電阻，寄生雙極電晶體可避免因暫態脈衝干擾而啟動。
實施例
以下將藉由實施例1至實施例7說明用以製造上開所述LDMOS電晶體之方法。
實施例1為一LDMOS電晶體之製造方法，其係包含：提供一晶圓；形成一汲極、一閘極、一源極及一背閘極；以及形成一隔離結構，該隔離結構配置為實體上將包含該汲極之一第一區域與一於使用時具有寄生雙極接面電晶體之一第二區域隔開。
實施例2為根據實施例1之LDMOS電晶體之製造方法，其中該方法包含形成一n型通道LDMOS電晶體。
實施例3為根據實施例1之LDMOS電晶體之製造方法，其中該方法包含形成一p型通道LDMOS電晶體。
實施例4為根據實施例1之LDMOS電晶體之製造方法，其中形成一隔離結構之步驟包含形成一介電深溝。
實施例5為一橫向n型通道LDMOS電晶體之製造方法，其係包含：提供一晶圓；形成一汲極、一閘極、一源極；及一背閘極；形成橫向延伸於該汲極與該閘極間之一場區氧化區域；形成橫向延伸於該場區氧化區域邊緣與該源極間之一閘極氧化區域；形成一p型摻雜區域，其中該p型摻雜區域係配置為於使用時減少一寄生雙極電晶體之增益；在該p型摻雜區域內形成一內埋p型摻雜層，使得該內埋p型摻雜層由p型摻雜區域之剩餘部分而與該源極及該背閘極分離，其中，形成一內埋p型摻雜層之步驟進一步包含將該內埋p型摻雜層 之一側邊緣對齊該閘極接近於該場區氧化區域與該閘極氧化區域間之過渡區域之一側邊緣。
實施例6為根據實施例5之橫向n型通道LDMOS電晶體之製造方法，其中，形成該內埋p型摻雜層之步驟包含：埋置該內埋p型摻雜層，該內埋p型摻雜層之摻雜物濃度高於該p型摻雜區域之剩餘部分。
實施例7為根據實施例5或6之橫向n型通道LDMOS電晶體之製造方法，其中，形成該p型摻雜區域之步驟包含：在一p型磊晶層上方形成該內埋p型摻雜層；並在該內埋p型摻雜層上方形成一p型井區域，其中該源極及該背閘極係形成於該p型井區域內。
本發明在此透過特定實施例加以描述，然所述實施例可經結合而提供更多實施例。此外，一實施例所示之特定功能亦可納入另一實施例中。雖本發明係以n型通道LDMOS電晶體為例說明，本發明之教示同樣適用於p型通道LDMOS電晶體。
100:LDMOS元件
101:氧化層上覆矽基板
101a:塊狀矽晶圓
101b:內埋氧化層/BOX層
102:摻雜矽區域
102a:內埋p型摻雜矽層
102b:p型摻雜磊晶生長矽層
103:n型井區域
103a:內埋n型摻雜區域
103b:n型摻雜區域
104:p型井區域
105:閘極
106:背閘極
106a:p型摻雜區域
106b:背閘極端子
107:源極
107a:n型摻雜區域
107b:金屬孔
107b:源極端子
108:汲極
108a:n型摻雜區域
108b:金屬孔
110:介電區域
110a,110b:LOCOS場區氧化區域
110c:閘極氧化區域
112:降低表面電場結構
112a:第一場板
112b:第二場板
114:導電通道

Claims (12)

  1. 一種橫向雙擴散金氧半(lateral double-diffused metal oxide semiconductor，LDMOS)電晶體，包含：一汲極；一閘極；一源極；以及一背閘極，包括位在一第一區域之一p型摻雜結構以及位在一第二區域的一p型摻雜結構；其中，該LDMOS電晶體進一步包含一隔離結構，配置為實體上將包含該LDMOS電晶體之該汲極在內之該第一區域與在使用時具有一寄生雙極接面電晶體之該第二區域隔開。
  2. 如請求項1之LDMOS電晶體，其中，該LDMOS電晶體包含一n型通道LDMOS電晶體，以及其中，該寄生雙極接面電晶體包含一寄生NPN雙極接面電晶體。
  3. 如請求項1之LDMOS電晶體，其中，該LDMOS電晶體包含一p型通道LDMOS電晶體，以及其中，該寄生雙極接面電晶體包含一寄生PNP雙極接面電晶體。
  4. 如請求項1之LDMOS電晶體，其中，該隔離結構係為一介電深溝。
  5. 如請求項1之LDMOS電晶體，其中，該閘極包含位在該第二區域中之一氧化層上多晶矽結構。
  6. 如請求項2之LDMOS電晶體，其中，位在該第一區域中之該p型摻雜結構於使用時係耦接於位於該第一區域中之一氧化層上多晶矽結構、位於該第一區域中之一p型摻雜基板以及位於該第二區域中之該p型摻雜結構。
  7. 如請求項2之LDMOS電晶體，其中，該第二區域進一步包含該源極，且位於該第一區域中之一第一n型摻雜井區域係耦接於位於該第二區域中之一第二n型摻雜井區域。
  8. 如請求項1之LDMOS電晶體，其中，該源極係耦接於該背閘極。
  9. 如請求項1之LDMOS電晶體，其中，該第一區域進一步包含一場板結構，其配置為在使用時控制該第一區域中之電荷分布。
  10. 如請求項9之LDMOS電晶體，其中，該場板結構包含：一第一場板；以及一第二場板；其中，該第二場板係位於該第一場板上方，其中，該第二場板係平行於該第一場板，以及其中，該第二場板係配置為耦接該第一場板。
  11. 如請求項1之LDMOS電晶體，更包括一LOCOS氧化層，其中，該背閘極與該源極由該LOCOS氧化層隔開。
  12. 一種n型通道橫向雙擴散金氧半(lateral double-diffused metal oxide semiconductor，LDMOS)電晶體，包含：一第一區域，配置為於使用時操作如同一虛擬之接面場效電晶體(JFET)；一第二區域，配置為於使用時操作如同一虛擬之金氧半場效電晶體(MOSFET)；以及 一背閘極，包括位在該第一區域之一p型摻雜結構以及位在該第二區域的一p型摻雜結構；其中，該第一區域因弱碰撞電離而產生一第一電流，其中，該第二區域因該第二區域中之一寄生NPN電晶體而產生一第二電流，以及其中，該第一區域係配置為與該第二區域隔離，使得該第一電流不與該第二電流成正比。
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