TWI771723B - 具有光子和垂直功率傳遞的asic封裝 - Google Patents

具有光子和垂直功率傳遞的asic封裝 Download PDF

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TWI771723B
TWI771723B TW109125385A TW109125385A TWI771723B TW I771723 B TWI771723 B TW I771723B TW 109125385 A TW109125385 A TW 109125385A TW 109125385 A TW109125385 A TW 109125385A TW I771723 B TWI771723 B TW I771723B
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asic
package
substrate
photonic
die
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TW202111898A (zh
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權雲星
楠勳 金
澤圭 姜
涼平 浦田
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美商谷歌有限責任公司
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Abstract

本發明係關於一種積體電路(IC)封裝。該IC封裝可包含一基板。一IC晶粒可安裝至該基板。一或多個光子模組可附接至該基板且一或多個串列器/解串列器(SerDes)介面可將該IC晶粒連接至該一或多個光子模組。該IC晶粒可為一專用積體電路(ASIC)晶粒，且該一或多個光子模組可包含一光子積體電路(PIC)及光纖陣列。該一或多個光子模組可安裝至一或多個額外基板，該一或多個額外基板可經由一或多個插座附接至該基板。

Description

具有光子和垂直功率傳遞的ASIC封裝
包含一或多個ASIC晶粒之專用積體電路封裝變得越來越能夠高速處理。隨著ASIC晶粒之處理速度不斷提高，連接ASIC封裝與其他組件之輸入/輸出(I/O)系統會成為一瓶頸。在此方面，I/O系統可能沒有足夠頻寬來處置ASIC晶粒所需之資料通量，藉此限制ASIC晶粒盡其所能操作。
本發明之一態樣提供一種積體電路(IC)封裝，其包括：一基板；一IC晶粒，其安裝至該基板；一或多個光子模組，其等附接至該基板；及一或多個串列器/解串列器(SerDes)介面，其等將該IC晶粒連接至該一或多個光子模組。該一或多個SerDes介面可包含複數個銅跡線且該等銅跡線可沈積於該基板上。在一些例項中，該IC晶粒可為一專用積體電路(ASIC)晶粒。在一些例項中，該IC封裝可經組態以連接至一平台柵格陣列(LGA)插座。功率可經由該LGA插座傳遞至該IC封裝。
在一些例項中，該一或多個光子模組可包含一控制器。該控制器管理其各自光子模組與該IC晶粒之間的資料傳輸。該一或多個光子 模組之各者可進一步包含一光子積體電路(PIC)及光纖陣列。該一或多個SerDes介面之各者可包含連接至一各自光子模組之一第一側及連接至該IC晶粒之一第二對置側。在一些實例中，該一或多個光子模組可安裝至一或多個額外基板且該一或多個額外基板可經由一或多個插座附接至該基板。
本發明之另一態樣提供一種專用積體電路(ASIC)封裝，其包括：一基板；一ASIC晶粒，其安裝至該基板；一或多個光子模組，其等附接至該基板；一或多個串列器/解串列器(SerDes)介面，其等將該ASIC晶粒連接至該一或多個光子模組；及一電壓調節器。在一些例項中，該電壓調節器可安裝至其中安裝該ASIC晶粒之該基板之對置側。該一或多個SerDes介面可包含複數個銅跡線且該等銅跡線可沈積於該基板上。在一些實例中，該基板可經組態以連接至一平台柵格陣列(LGA)插座且功率可經由該LGA插座傳遞至該電壓調節器。
在一些例項中，該ASIC封裝中之該一或多個光子模組之各者可包含一控制器，其管理其各自光子模組與該ASIC晶粒之間的資料傳輸。該一或多個光子模組之各者可進一步包含一光子積體電路(PIC)及光纖陣列。該一或多個SerDes介面可包含一第一側及一第二對置側，其中對於該等SerDes介面之各者，該第一側連接至一各自光子模組且該第二對置側連接至該ASIC晶粒。該一或多個光子模組可安裝至一或多個額外基板且其中該一或多個額外基板可經由一或多個插座附接至該基板。
201:專用積體電路(ASIC)封裝
202:基板
203:插座
207:外殼
210:ASIC晶粒
214:接針
215:接點
220A:光子模組
220B:光子模組
222A:控制器
222B:控制器
224A:光子積體電路(PIC)
224B:PIC
226A:光纖陣列
226B:光纖陣列
228A:支撐件
228B:支撐件
230:電壓調節器
231:提供功率
232:傳遞功率
240:散熱器
250:散熱片
280:平台柵格陣列(LGA)插座
290A:SerDes介面
290B:SerDes介面
291A:跡線
291B:跡線
293A:串列器
293B:串列器
294A:解串列器
294B:解串列器
301:ASIC封裝
331:接收功率
401:ASIC封裝
402:基板
403A:基板
403B:基板
410:ASIC晶粒
415A:插座
415B:插座
420A:光子模組
420B:光子模組
431:接收功率
440:散熱器
450:散熱片
480:平台柵格陣列(LGA)插座
490A:串列器/解串列器(SerDes)介面
490B:SerDes介面
501:ASIC封裝
530:電壓調節器
531:提供功率
701:ASIC封裝
702:基板
710:ASIC晶粒
714:焊料球
715:墊
716:球柵陣列(BGA)
720A:光子模組
720B:光子模組
731:傳遞功率
780:基板
圖1係根據本發明之態樣之具有一整合式I/O介面之一ASIC包裝之一俯視圖。
圖2係根據本發明之態樣之具有一整合式I/O介面及電壓調節器之一ASIC封裝之一側剖視圖。
圖3係根據本發明之態樣之具有一整合式I/O介面之一ASIC封裝之一側剖視圖。
圖4係根據本發明之態樣之具有一單獨基板上之一整合式I/O介面之一ASIC封裝之一側剖視圖。
圖5係根據本發明之態樣之具有一單獨基板上之一整合式I/O介面及整合式電壓調節器之一ASIC封裝之一側剖視圖。
圖6係根據本發明之態樣之一串列器/解串列器介面之一說明圖。
圖7係經由一球柵陣列連接至一基板之一ASIC封裝之一側剖視圖。
本發明大體上係關於一種具有一整合式光子模組及垂直整合式功率調節器之專用積體電路(ASIC)封裝。如先前所描述，連接一ASIC封裝與其他組件之I/O系統可能沒有足夠頻寬來處置ASIC晶粒所需之資料通量。為解決此問題，可使用具有約100Gbps頻寬之I/O系統來減小I/O系統瓶頸。然而，此等I/O系統通常經由介面經由一外部連接連接至ASIC封裝。隨著介面頻寬增大以處置I/O系統之通量，在I/O系統與ASIC晶粒之間載送信號之介面跡線會引起信號損失，諸如透過高頻衰減。信號損失可由自ASIC晶粒至外部定位之I/O系統之介面之跡線長度加劇。
為減少一介面上之信號損失量，介面之跡線行進穿過之基板可由具有低介電常數(Dk)及介電損失(Df)之材料製成。而且，可減小跡 線表面之粗糙度以進一步限制信號損失量。然而，即使使用低Dk及Df材料及平滑跡線，亦僅可實現信號損失量之最低限度改良。
為消除或進一步補救信號損失之問題，可將包含光子模組之I/O系統整合至ASIC封裝中。可藉由整合光子模組來減小將光子模組連接至ASIC晶粒之跡線之長度，藉此最小化信號損失量。在此方面，介面之跡線之長度可整合至一低Dk及Df PCB中。可將ASIC晶粒連接至一外部I/O系統之跡線可約為10英寸。在以100Gbps操作期間，10英寸跡線會遭受約20dB之一信號損失。
如圖1中ASIC封裝201之俯視剖視圖中所展示，可藉由將光子模組整合至ASIC封裝中且將光子模組220A及220B附接至相同於ASIC晶粒210之基板來減小跡線291A及291B之長度。在此方面，自ASIC晶粒210至整合式光子模組220A及220B之介面中之跡線291A及291B可減小至約40mm至約50mm。因此，在100Gbps之操作速度處，信號損失量可相對於連接一ASIC晶粒與ASIC封裝外部之一I/O系統之介面上之信號損失減少約10dB。因而，其中整合介面之跡線之PCB可具有較高Dk及Df值，其可節省材料成本、生產成本，同時仍提供改良信號傳輸。此等益處可在甚至更高操作速度(諸如200Gbps或更大)處繼續實現。
圖2至圖5繪示具有整合式光子模組之ASIC封裝組態之實例。例如且如圖2中所展示，ASIC封裝201包含經由一插座203安裝至一基板202之一ASIC晶粒210。插座可為一球柵陣列(BGA)、平台柵格陣列(LGA)、接針柵格陣列(PGA)或其他此等插座連接。ASIC封裝201進一步包含展示為虛線框220A及220B之光子模組，其包含可操作為ASIC封裝之一I/O系統之光纖陣列226A、226B、光子積體電路(PIC)224A、224B及控 制器222A、222B。光子模組220A及220B可附接至一基板，諸如圖2中進一步所展示之基板202。光子模組220A及220B之附接可為永久的或經由一可移除連接，如本文中所描述。由圖2中之雙側箭頭線290A及290B展示之一介面(諸如一串列器/解串列器(SerDes)介面(如本文中所描述))將光子模組220A及220B連接至ASIC晶粒210。
ASIC封裝201亦可包含一電壓調節器230，其安裝至其中安裝ASIC晶粒210之基板202之對置側。功率可由電壓調節器230傳遞至ASIC晶粒210，如由圖2中之虛線箭頭232所展示。ASIC封裝201可經組態以連接至一插座(諸如LGA插座280)，來自一外部源之功率可透過插座提供至電壓調節器230，如由雙側虛線箭頭231所展示。ASIC封裝201可包含其中定位ASIC封裝201之組件之一外殼，諸如外殼207。
一光子模組(諸如光子模組220A及220B)可包含任何數目個組件，其包含光纖陣列226A、226B、光子積體電路(PIC)224A、224B及/或控制器222A、222B。一光子模組中之組件可為離散元件及/或元件之組合。例如，一光纖陣列可經整合至一PIC中及/或一PIC可經整合至一控制器中。
一光纖陣列(諸如光纖陣列226A及226B)可為能夠將光信號傳入或傳出ASIC封裝(諸如ASIC封裝201)之一或多個光纜之一集合。光纖陣列可為光纖電纜之一維(1D)陣列或二維(2D)陣列。光纖陣列可經由一側或垂直耦合來耦合至PIC。
光纖陣列可安裝至支撐件上。例如且如圖2中所展示，光纖陣列226A安裝至支撐件228A上且光纖陣列226B安裝至支撐件228B上。支撐件可將光纖陣列附接至一基板(諸如基板202)。可根據支撐件之 形狀及大小來調整光纖陣列之實體高度及定位。例如，藉由增大一支撐件(諸如支撐件228A)之高度，附接至支撐件之光纖陣列226A可定位成更遠離基板202且在ASIC封裝201中更高。在一些例項中，支撐件228A、228B可經組態以依相對於基板之特定角度定位光纖陣列226A、226B。
一光子積體電路(諸如PIC 224A及224B)可經組態以將電信號轉換成光信號及/或將光信號轉換成電信號。例如且參考圖2，ASIC封裝201包含兩個光子模組220A及220B，其中各光子模組包含一PIC 224A及224B。第一PIC 224A可經組態以自經附接光纖陣列226A接收光信號且將光信號轉換成電信號。接著，第一PIC可將電信號傳至經附接控制器222A。第二PIC 224B可經組態以自經附接控制器222B接收電信號且將電信號轉換成光信號以由經附接光纖陣列226B傳出ASIC封裝。在一些例項中，PIC可包含一或多個波導用於在PIC與光纖陣列之間引導光信號。
一控制器可用於指導ASIC晶粒與PIC之間的電信號流動。例如且如圖2中所展示，ASIC封裝201包含兩個控制器222A及222B。控制器222A及222B可為經組態以調變或解調變信號之一轉阻放大器(TIA)及/或積體電路(IC)。例如，控制器222A可自PIC 224A接收一調變信號，諸如已使用4階脈衝振幅調變(PAM4)或某種其他類型之調變來調變之一信號。控制器222A可解調變信號且透過一介面(諸如SerDes介面290A)將其傳至ASIC晶粒210。控制器222B可透過SerDes介面290B自ASIC晶粒210接收一未調變信號。控制器222B可使用PAM4或某種其他調變來調變信號且將經調變信號傳至PIC 224A。在一些例項中，控制器可放大信號或對信號執行其他數位信號處理。
光子模組可經由一介面(諸如一SerDes介面)連接至ASIC晶 粒。例如且如圖2中所展示，SerDes介面(由雙側箭頭290A及290B繪示)將ASIC晶粒210連接至兩個光子模組220A及220B。再次參考圖1，SerDes介面可包含將ASIC晶粒210連接至光子模組220A及220B之跡線之一集合，諸如跡線291A及291B(跡線291A及291B諸如為銅跡線)。跡線291A及291B可直接印刷至基板上及/或經由導線實施。
在介面跡線之各端處可為可連接至晶粒及/或光子模組之一串列器及/或一解串列器。在此方面，跡線之各端可包含一串列器及一解串列器以允許在跡線上雙向通信。例如且如圖6中之SerDes介面290A之分解圖中所展示，一些跡線291A之一第一端上之串列器293A連接至跡線291A之對置側上之一解串列器294B。類似地，串列器293B發現於與解串列器294A對置之跡線之側上。儘管各SerDes介面290A及290B中僅展示9條跡線，但在一介面中可具有任何數目個跡線。在一些例項中，串列器及解串列器可整合至控制器及/或ASIC中。在一些實例中，串列器及解串列器可整合至一經組合串列器/解串列器中。
在操作中，串列器293A、293B可將並行信號轉換成串列信號以在跡線291A上傳輸。接著，跡線291A之另一端上之解串列器294A、294B可將串列信號轉換回並行信號。
一光子模組之組件可安裝至相同於ASIC晶粒之基板及/或一不同基板。例如且如圖2及圖3中所展示，光子模組220A、220B之組件安裝至相同於ASIC晶粒210至基板(基板202)。可藉由將光子模組220A、220B安裝至相同於ASIC晶粒之基板來避免基板之間的SerDes介面290A、290B之垂直過渡，藉此減小可引起信號損失之阻抗。
在圖4及圖5中，兩個光子模組420A及420B之組件(其可與 光子模組220A、220B比較)分別安裝至不同基板403A及403B。此等兩個基板403A及403B各不同於其上安裝ASIC晶粒410之基板402。
如圖4及圖5中進一步所展示，其上安裝光子模組之基板403A及403B可連接至其上安裝ASIC晶粒410之基板402。連接可經由一高速插座及/或焊接(諸如將基板403A連接至基板402之插座415A及將基板403B連接至基板402之插座415B)形成。儘管圖4及圖5展示光子模組420A及420B分別安裝至不同基板403A及403B，但光子模組420A及420B可安裝於相同基板。基板可為印刷電路板(PCB)或其他適合材料。
在不同於ASIC晶粒之基板上具有光子模組之ASIC封裝可包含透過基板將光子模組連接至ASIC晶粒之介面。例如且分別如圖4及圖5中之ASIC封裝401及501中所展示，由雙箭頭線490A及490B展示之SerDes介面可連接光子模組420A及420B與ASIC晶粒410。在此方面，SerDes介面490A可透過插座415A行進以連接基板403A上之光子模組420A與基板402上之ASIC晶粒410。類似地，SerDes介面490B可透過插座415B行進以連接基板403B上之光子模組420B與基板402上之ASIC晶粒410。
藉由將光子模組420A及420B安裝於不同基板上(諸如圖4及圖5之ASIC封裝401及501中所展示)，SerDes介面中之跡線之長度可比光子模組安裝於相同於ASIC晶粒之基板上(諸如圖2及圖3之ASIC封裝201及301中所展示)時更長。當光子模組位於不同基板上時，SerDes介面之增大長度可隨著一信號沿SerDes跡線行進而增加信號損失，且可增加組件之間的信號行進時間之行進時間。然而，可相對於ASIC封裝201及301提高ASIC封裝401及501之生產良率，因為可換出破損組件(例如一破損光子模 組、破損ASIC晶粒等等)而無需替換整個ASIC封裝。
一ASIC晶粒(諸如ASIC晶粒210及410)之處理速度提高亦會增加操作ASIC晶粒所需之功率量。在此方面且如圖7中所展示，一ASIC封裝701可經由一球柵陣列(BGA)716連接至一電源(未展示)。BGA 716可包含形成於ASIC封裝701之基底上之複數個焊料球，諸如焊料球714。焊料球可與形成於其中將安裝ASIC封裝701之基板780上之對應墊(諸如銅墊715)對準。焊料球經焊接至其對應墊以將ASIC封裝701永久安裝至基板780。例如，焊料球714焊接至對應墊715上以形成一焊點。一電源可透過BGA 716之焊點及基板702內之導線及/或其他此等連接(未展示)將功率傳遞至ASIC晶粒710且在一些例項中傳遞至光子模組720A及720B，如由虛線箭頭731所繪示。
由一ASIC晶粒710汲取之一功率增加可導致ASIC封裝內之一熱增加，其歸因於由透過ASIC封裝701及基板702將功率載送至ASIC晶粒710之導線及/或其他此等連接產生之銅損。銅損(亦稱為「I2R損失」(其中「I」係流動通過佈線中之銅之電流且「R」係佈線之電阻))係在電流通過佈線時耗散之熱量。由ASIC晶粒710之增加功率汲取產生之溫度升高可導致BGA焊料電遷移及一或多個焊點之潛在失效。溫度升高亦會影響ASIC晶粒710之熱效能以潛在地導致ASIC晶粒710或ASIC封裝701之其他組件失效。
為減少由透過ASIC封裝將功率載送至ASIC晶粒之導線、平面(例如銅平面)及/或其他此等連接產生之銅損量，可將一電壓調節器整合至ASIC封裝中。例如，一電壓調節器230安裝至其中安裝ASIC晶粒210之基板202之對置側，如圖2之ASIC封裝201中所展示。且如圖5之ASIC封 裝501中所展示，一電壓調節器530安裝至其中安裝ASIC晶粒410之基板402之對置側。功率可自一外部電源傳遞至電壓調節器230、530。在此方面，外部電源可透過ASIC封裝安裝至其之一插座將功率提供至電壓調節器230、530，如分別由圖2及圖5中之虛線雙側箭頭231及531所展示。接著，電壓調節器230、530可經由基板上或基板內之一或多個導線、平面(例如銅平面)及/或其他此等連接將功率提供至ASIC晶粒210、410。
電壓調節器可維持來自外部電源之一致功率汲取，藉此防止或減少由基板上或基板內之導線、跡線及/或其他此等連接載送之功率增加數。此外，可相對於由ASIC晶粒210及410直接自外部電源接收功率(分別如圖3及圖4中之虛線箭頭331及431所展示)時減小電壓調節器與ASIC晶粒(諸如ASIC晶粒210及410)之間的導線、跡線及/或其他此等連接之長度。由於ASIC封裝上之插座接點(諸如ASIC封裝201之接點215)通常具有高接觸電阻，因此流動通過接點215之功率產生之熱損失可能很大。可藉由將電壓調節器移動至ASIC封裝中來減少流動通過接點215之功率量。因此，可減少由銅損產生之ASIC封裝201及501內之熱。儘管電壓調節器230及530展示為直接位於ASIC晶粒210及410下方，但電壓調節器可自ASIC晶粒偏移。
可透過使用散熱片及散熱器來進一步減少熱。例如且如圖2及圖3中所展示，散熱器240可圍繞ASIC晶粒210定位以將由ASIC晶粒210產生之熱帶離ASIC晶粒210。類似地，散熱器440可圍繞ASIC晶粒410定位以將由ASIC晶粒410產生之熱帶離ASIC晶粒410。
散熱片可定位於ASIC封裝之內部內以自封裝之內部帶走熱(諸如由光子模組及ASIC晶粒產生之熱)且推動其朝向ASIC封裝之外殼。 例如且如圖2及圖3中所展示，散熱片250可定位於ASIC晶粒210及散熱器240上方。散熱片250可自ASIC晶粒210及散熱器240帶走熱。類似地，散熱片450可自ASIC晶粒410及散熱器440帶走熱。
如上文所論述，一典型ASIC封裝可經由焊接至一球柵陣列(BGA)上之接針連接至一電源。然而，鑑於具有整合式光子模組及/或電壓調節器之一ASIC封裝之大尺寸，可使用一LGA插座作為圖2至圖5之LGA插座280及480。參考圖2，LGA插座280可包含與形成於基板202上之接點215對準之接針214。當ASIC封裝201經配置使得接點215與接針214對準時，ASIC封裝201可固定至LGA插座280。在一些例項中，接針214可焊接至接點215。然而，接針214可提供與ASIC封裝之接點215之足夠接觸以減少焊點需求且藉此降低焊料電遷移之風險。作為焊接之替代或附加，一閂鎖或其他此鎖定組件亦可使ASIC封裝201保持固定於LGA插座280中。在其中ASIC封裝201未焊接至LGA插座280之例項中，ASIC封裝201可自LGA插座280移除。
儘管圖2至圖5中所展示之實例ASIC封裝201、301、401及501僅包含一單一ASIC晶粒210或410，但各ASIC封裝可包含任何數目個ASIC晶粒。此外，各ASIC封裝可包含任何數目個光子模組、光子模組內之組件、電壓調節器或其他組件。另外，儘管本文中所描述之封裝經描述為具有ASIC晶粒之ASIC封裝，但可使用任何類型之晶粒，諸如一積體電路晶粒。
本文中所描述之特徵允許將光子模組整合至一ASIC封裝中。藉此，可減小或移除I/O系統瓶頸。此外，可減少光子模組與ASIC晶粒之間的連接介面上之信號損失。另外，可藉由將一電壓調節器整合至 ASIC封裝中來減少由透過ASIC封裝將功率載送至ASIC晶粒之導線、跡線及/或其他此等連接產生之銅損。將ASIC封裝組態成安裝至一LGA插座可降低破損焊點及焊料電遷移之風險及提供根據需要移除ASIC封裝之能力。
儘管已參考特定實施例描述本發明，但應瞭解，此等實施例僅繪示本發明之原理及應用。因此，應瞭解，可在不背離由隨附申請專利範圍界定之本發明之精神及範疇的情況下對繪示性實施例作出各種修改且可設計其他配置。
401:專用積體電路(ASIC)封裝
402:基板
403A:基板
403B:基板
410:ASIC晶粒
415A:插座
415B:插座
420A:光子模組
420B:光子模組
431:接收功率
440:散熱器
450:散熱片
480:平台柵格陣列(LGA)插座
490A:串列器/解串列器(SerDes)介面
490B:SerDes介面

Claims (18)

  1. 一種積體電路(IC)封裝，其包括：一基板；一IC晶粒，其安裝至該基板之一第一表面；一或多個光子模組，其等附接至該基板之該第一表面；一或多個串列器/解串列器(SerDes)介面，其等將該IC晶粒直接地連接至該一或多個光子模組；及一電壓調節器，其安裝至該IC晶粒正下方(directly under)之該基板之一第二表面上，其中該基板之該第二表面係對置於該基板之該第一表面。
  2. 如請求項1之IC封裝，其中該一或多個SerDes介面包含複數個銅跡線；且其中該等銅跡線沈積於該基板上。
  3. 如請求項1之IC封裝，其中該一或多個光子模組之各者包含一控制器，其中各控制器管理其各自光子模組與該IC晶粒之間的資料傳輸。
  4. 如請求項3之IC封裝，其中該一或多個光子模組之各者進一步包含一光子積體電路(PIC)及光纖陣列。
  5. 如請求項4之IC封裝，其中該一或多個SerDes介面之各者包含一第一 側及一第二對置側，其中對於該等SerDes介面之各者，該第一側連接至一各自光子模組且該第二對置側連接至該IC晶粒。
  6. 如請求項1之IC封裝，其中該IC封裝經組態以連接至一平台柵格陣列(LGA)插座。
  7. 如請求項6之IC封裝，其中功率經由該LGA插座傳遞至該IC封裝。
  8. 如請求項1之IC封裝，其中該一或多個光子模組安裝至一或多個額外基板。
  9. 如請求項8之IC封裝，其中該一或多個額外基板經由一或多個插座附接至該基板。
  10. 一種專用積體電路(ASIC)封裝，其包括：一基板；一ASIC晶粒，其安裝至該基板之一第一表面；一或多個光子模組，其等附接至該基板之該第一表面；一或多個串列器/解串列器(SerDes)介面，其等將該ASIC晶粒直接地連接至該一或多個光子模組；及一電壓調節器，其安裝至該ASIC晶粒正下方之該基板之一第二表面上，其中該基板之該第二表面係對置於該基板之該第一表面。
  11. 如請求項10之ASIC封裝，其中該一或多個SerDes介面包含複數個銅跡線；且其中該等銅跡線沈積於該基板上。
  12. 如請求項10之ASIC封裝，其中該一或多個光子模組之各者包含一控制器，其中各控制器管理其各自光子模組與該ASIC晶粒之間的資料傳輸。
  13. 如請求項12之ASIC封裝，其中該一或多個光子模組之各者進一步包含一光子積體電路(PIC)及光纖陣列。
  14. 如請求項13之ASIC封裝，其中該一或多個SerDes介面之各者包含一第一側及一第二對置側，其中對於該等SerDes介面之各者，該第一側連接至一各自光子模組且該第二對置側連接至該ASIC晶粒。
  15. 如請求項10之ASIC封裝，其中該基板經組態以連接至一平台柵格陣列(LGA)插座。
  16. 如請求項15之ASIC封裝，其中功率經由該LGA插座傳遞至該電壓調節器。
  17. 如請求項10之ASIC封裝，其中該一或多個光子模組安裝至一或多個額外基板。
  18. 如請求項17之ASIC封裝，其中該一或多個額外基板經由一或多個插座附接至該基板。
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