TWI771021B - Method of forming a semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure is provided in some embodiments of the present disclosure, including: providing a substrate; forming a first hard mask on the substrate; forming a second hard mask on the first hard mask; forming a plurality of mask patterns on the second hard mask, in which the mask patterns are separated by a plurality of trenches, and the trenches expose the second hard mask and have a first depth; forming a barrier layer in the trenches connecting neighboring trenches of the second hard mask; removing the mask patterns by using an etchant; and performing a cleaning process and removing the barrier layer.

Description

Methods of forming semiconductor structures

Some embodiments of the present disclosure relate to methods of forming semiconductor structures. Specifically, some embodiments of the present disclosure are methods of forming semiconductor structures with hard masks.

Conventionally, in order to form trenches in a semiconductor substrate, a mask pattern is usually first formed on a hard mask on the substrate to define the positions of the trenches. Then, according to the mask pattern, grooves are etched on the hard mask; then, using the hard mask as a protective layer, the substrate material not covered by the hard mask is further etched to form grooves on the substrate.

However, after the trenches are etched on the hard mask, the mask pattern needs to be removed. Generally speaking, removing the mask pattern is easy to erode the hard mask layer containing oxide at the bottom, causing the hard mask layer to show a concave phenomenon, thus increasing the critical dimension of the columnar structure spacing of the hard mask layer, and even the hard mask layer cannot Bearing and breaking, reducing the yield of finished products.

Therefore, there is a need to provide a method for forming a semiconductor structure that avoids erosion of the bottom oxide-containing hard mask layer when removing the mask pattern.

Some embodiments of the present disclosure provide a method of forming a semiconductor structure, comprising: providing a substrate; forming a first hard mask layer on the substrate, wherein the first hard mask layer includes an oxide; forming a second hard mask layer on the first hard mask layer on the mask layer; forming a plurality of mask patterns on the second hard mask layer, wherein the mask patterns are separated by a plurality of grooves, and the grooves expose the second hard mask layer and have a first depth along a specific direction, wherein the direction is vertical on the upper surface of the substrate in contact with the first hard mask layer; the first hard mask layer not covered by the mask pattern and the second hard mask layer not covered by the mask pattern are removed, so that the groove exposes the second hard mask The plurality of sidewalls of the layer, the plurality of sidewalls of the first hard mask layer and the upper surface of the substrate, and the trench is deepened from the first depth to the second depth; a barrier layer is formed in the trench, and the barrier layer is connected to the adjacent second hard cover layer. using an etchant to remove the mask pattern, wherein the barrier layer blocks the etchant from contacting the first hard mask layer; and performing a cleaning process to remove the barrier layer.

In some embodiments, the step of forming the barrier layer in the trench includes that the barrier layer only connects the sidewalls of the adjacent second hard mask layers, and does not extend to fill the trench in a specific direction.

In some embodiments, the step of forming the barrier layer in the trench includes forming the barrier layer to extend toward the specific direction to fill the trench, so that the barrier layer connects the sidewalls of the adjacent first hard mask layers and the upper surface of the substrate. surface contact.

In some embodiments, the top surface of the barrier layer is horizontally flush with the top surface of the second hardmask layer.

In some embodiments, the top surface of the barrier layer is horizontally lower than the top surface of the second hard cap layer.

In some embodiments, the first hard cap layer and the second hard cap layer comprise different materials.

In some embodiments, if the etchant contacts the second hardmask layer, the etchant does not etch the second hardmask layer.

In some embodiments, the first hard mask layer includes silicon oxide, and the second hard mask layer includes silicon nitride.

In some embodiments, removing the mask pattern using an etchant is a dry etching process, and the etchant includes carbon tetrafluoride, carbon difluoride, oxygen, or a combination thereof.

In some embodiments, the barrier layer is carbon or a carbon-containing material, and the cleaning process is ashing.

It is to be understood that both the foregoing general description and the following detailed description are examples and are intended to provide further explanation of the disclosure as claimed.

It will be appreciated that different implementations or examples provided in the following may implement different features of the subject matter of the present disclosure. The embodiments of specific components and arrangements are used to simplify the disclosure and not to limit the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the description below that the first feature is formed on the second feature includes the two being in direct contact, or there are other additional features between the two that are not in direct contact. Furthermore, the present disclosure may repeat reference numerals and/or symbols in the various embodiments. Such repetition is for simplicity and clarity and does not represent a relationship between the various embodiments and/or configurations discussed.

Terms used in this specification generally have their ordinary meanings in the art and in the context in which they are used. The examples used in this specification, including examples of any terms discussed herein, are illustrative only and do not limit the scope and meaning of the disclosure or any exemplified terms. Likewise, the present disclosure is not limited to some of the implementations provided in this specification.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present embodiments.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the terms "comprising", "including", "having" and the like should be construed as open ended, ie, meaning including but not limited to.

FIG. 1 exemplarily depicts a method 100 of forming a semiconductor structure in some embodiments in accordance with the present disclosure. Please refer to FIG. 1, including steps S110 to S180, respectively: step S110, providing a substrate; step S120, forming a first hard mask layer on the substrate; step S130, forming a second hard mask layer on the first hard mask layer Step S140, forming a plurality of mask patterns on the second hard mask layer; Step S150, removing the first hard mask layer not covered by the mask pattern and the second hard mask layer not covered by the mask pattern; Step S160 , forming a barrier layer in the trench, and the barrier layer is connected to the sidewall of the adjacent second hard mask layer; step S170 , using an etchant to remove the mask pattern; and step S180 , performing a cleaning process to remove the barrier layer.

In order to facilitate the description of steps S110 to S180 in FIG. 1 , please refer to FIGS. 2 to 10 at the same time to exemplarily describe the method 100 for forming a semiconductor structure in some embodiments of the present disclosure, and the cross-sections of the steps at each stage. Schematic diagrams (FIGS. 2 to 9) and a top view of the resulting semiconductor structure 300 (FIG. 10).

First, referring to step S110 in FIG. 1 and FIG. 2 , the substrate 210 is provided. In some embodiments, the substrate 210 may comprise monocrystalline silicon, or generally refer to a semiconductor substrate or a portion thereof. In FIG. 2, although the substrate 210 is shown as being uniform and homogeneous, it is only a schematic diagram. In fact, the substrate 210 may also include different materials, such as different materials related to the manufacture of integrated circuits, including but not limited to metals, resistors, etc. Barrier materials, diffusion materials or insulating materials, etc. For example, the substrate 210 can be a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a semi-finished substrate in other different semiconductor process stages, but not limited thereto.

Next, referring to step S120 in FIG. 1 and FIG. 3 , the first hard mask layer 220 is formed on the substrate 210 . In some embodiments, the first hard mask layer 220 includes an oxide, such as silicon dioxide, silicon oxynitride, or a combination thereof, but is not limited thereto.

Referring to step S130 in FIG. 1 and FIG. 4 , the second hard mask layer 230 is formed on the first hard mask layer 220 . In some embodiments, the second hard mask layer 230 comprises a different material than the first hard mask layer 220, and if the second hard mask layer 230 is exposed to an etchant with high selectivity to oxides, the second hard mask layer 230 is The hard mask layer 230 is not etched. In some embodiments, the second hard cap layer 230 includes silicon nitride, silicon carbonitride, or a combination thereof, but is not limited thereto.

Next, referring to step S140 in FIG. 1 and FIG. 5 , a plurality of mask patterns 240 are formed on the second hard mask layer 230 . In some embodiments, the step S140 of forming the plurality of mask patterns 240 on the second hard mask layer 230 includes: forming a photoresist layer on the second hard mask layer 230; The layer is subjected to an exposure and development process, so that the pattern on the photomask is transferred to the photoresist layer, forming a mask pattern 240 . In one embodiment, multiple photoresist layers can be formed on the second hard mask layer 230 along the Z-axis direction as required, and then the multiple photoresist layers can be patterned to form multiple mask patterns 240 , wherein the Z-axis is perpendicular to the substrate 210 . In the upper surface 212 in contact with the first hard mask layer 220, the X axis is the coordinate axis in any direction in the upper surface 212 of the substrate 210, in addition, the coordinate axis perpendicular to both the Z axis and the X axis is defined as Y shaft (not shown).

In some embodiments, the mask patterns 240 are separated by a plurality of trenches T, which expose the second hard mask layer 230 and have a first depth D1 along the Z-axis direction. Those skilled in the art can form an appropriate thickness of the mask pattern 240 (that is, the thickness of the mask pattern 240 along the Z-axis direction) and the width of the trench between the mask patterns 240 (that is, the trench T along the X-axis) as required. direction width). In one embodiment, the mask pattern 240 is a columnar body uniformly distributed on the second hard mask layer 230 , such as a cylindrical body or a rectangular columnar body.

Next, please refer to step S150 of FIG. 1 and FIG. 6 , using the mask pattern 240 as a protective layer, perform an etching process to remove the first hard mask layer 220 not covered by the mask pattern 240 and the mask pattern 240 not covered by the mask pattern 240 The second hard mask layer 230 is covered so that the trench T exposes the sidewall 232 of the second hard mask layer 230 , the sidewall 222 of the first hard mask layer 220 and the upper surface 212 of the substrate 210 , and the trench T is formed by the first depth D1, along the Z-axis direction, is further deepened to a second depth D2. In some embodiments, one or more etchants may be selected to have high selectivity to the first hard mask layer 220 and the second hard mask layer 230, and low or even no selectivity to the mask pattern 240, to etch the first The hard mask layer 220 and the second hard mask layer 230 deepen the trench T.

In other embodiments, multiple mask patterns 240 composed of photoresist layers of different materials can also be used, and multiple etchants with different etching selectivities can be flexibly matched to optimize the removal of the first hard mask layer 220 and the second hard mask layer 240. The effect of the hard cap layer 230. For example, when the second hard mask layer 230 not covered by the mask pattern 240 can be removed by the first etchant, the first etchant can remove the upper mask pattern 240 . However, the first etchant has poor or no etch selectivity for the lower mask pattern 240 and the first hard mask layer 220 , so the lower mask pattern 240 and the first hard mask layer 220 can be retained , thereby defining the position of the first hard mask layer 220 not covered by the underlying mask pattern 240 , and then using another second etchant to remove the first hard mask layer not covered by the mask pattern 240 Step 220 , making the trench T penetrate into the first hard mask layer 220 .

Next, referring to step S160 of FIG. 1 and FIGS. 7A to 7C , a barrier layer 250 is formed in the trench T, and the barrier layer 250 is connected to the sidewalls 232 of the adjacent second hard mask layers 230 .

In some embodiments, the barrier layer 250 is carbon or an underlayer material, and the underlayer material includes, but is not limited to, carbon-containing substances, such as organic polymer materials.

It should be noted that the blocking layer 250 here is used as a protective layer for the first hard mask layer 220 , and the purpose is to block the first hard mask layer 220 and the etchant used to remove the mask pattern 240 later (for example, as described later). the third etchant and the fourth etchant) to prevent the first hard mask layer 220 from being etched by the etchant.

Therefore, in some embodiments, please refer to FIG. 7A , the barrier layer 250 may be a high-viscosity material, or simultaneously include high-viscosity additives, and only connect the sidewalls 232 of the adjacent second hard mask layers 230 , and The trenches T are not extended in the Z-axis direction. In some other embodiments, although the barrier layer 250 does not extend to fill the trench T, in addition to connecting the sidewalls 232 of the adjacent second hard mask layers 230 , it may also partially contact the sidewalls 232 of the first hard mask layers 230 .

In other embodiments, please refer to FIG. 7B and FIG. 7C , the barrier layer 250 may also extend toward the Z-axis direction to fill the trench T, so that the barrier layer 250 is connected to the sidewalls of the adjacent first hard mask layers 220 222 and in contact with the upper surface 212 of the substrate 210 . For example, in FIG. 7B , the barrier layer 250 fills the trench T, and the barrier layer 250 is coplanar with the second hard mask layer 230 in the X-axis and Y-axis directions, that is, the top surface 252 of the barrier layer 250 and the second hard mask layer 230 are coplanar. The top surface 234 of the hard mask layer 230 is flush, or for example in FIG. 7C, although the barrier layer 250 fills the trench T, the top surface 252 of the barrier layer 250 is lower than the second hard mask layer in the X-axis direction The top surface 234 of the second hard mask layer 230 is thus partially exposed and does not contact the barrier layer 250 .

Next, referring to step S170 of FIG. 1 and FIGS. 8A to 8C , the mask pattern is removed using a third etchant, wherein the barrier layer 250 blocks the third etchant from contacting the first hard mask layer 220 . FIGS. 8A to 8C correspond to cross-sectional schematic diagrams of removing the mask pattern 240 in FIGS. 7A to 7C using the third etchant, respectively.

In some embodiments, the third etchant does not etch the barrier layer 250 , so the barrier layer 250 can physically block the third etchant and the first hard mask layer 220 even if the mask pattern is completely removed. In some embodiments, if the third etchant contacts the first hard mask layer 220 , the third etchant etches the first hard mask layer 220 , and if the third etchant contacts the second hard mask layer 230 , the third etchant etches the first hard mask layer 220 . The second hard mask layer 230 is not etched.

In some embodiments, using the third etchant to remove the mask pattern is a dry etching process, for example, the third etchant uses carbon tetrafluoride, carbon difluoride, oxygen or a combination thereof, but not limited thereto.

For example, the first hard mask layer 220 is silicon oxide (for example, including silicon dioxide), and the second hard mask layer 230 is silicon nitride. If there is no barrier layer 250, carbon tetrafluoride gas is used as the first Three etchants, removing the mask pattern 240, the first hard mask layer 220 located below will be eroded due to the high selectivity of carbon tetrafluoride to silicon oxide and extremely low selectivity to silicon nitride As a result, the sidewalls 222 are concave and the critical dimension of the spacing between the columnar structures of the first hard mask layer 220 is increased, which may cause insufficient bottom support and even the first hard mask layer 220 to be broken.

In some embodiments, a variety of etchants and other chemical treatments can be flexibly selected according to requirements, and multi-step removal is performed on the mask pattern to optimize the removal effect of the mask pattern. Considering that some types of etchants may interact with the negative oxides remaining on the mask pattern 240 to form oxides (not shown) deposited on the top surface of the mask pattern or the top surface 234 of the second hard mask layer 230, In order to improve the etching effect, in one embodiment, a third etchant may be used to first remove the negative oxide and preliminarily remove the mask pattern 240 (eg, dry gas etching using carbon tetrafluoride), and then another fourth etching may be used. agent to further remove the mask pattern 240 and remove the residue on the top surface 234 of the second hard mask layer 230 . The negative oxide is first removed by the third etchant, which can prevent other fourth etchants used to remove the mask pattern 240 from reacting with the negative oxide to generate oxide, which is deposited on the mask pattern or the second hard mask Top surface 234 of layer 230 .

Next, please refer to step S180 of FIG. 1 , FIG. 9 , and FIG. 10 , perform a cleaning process, remove the barrier layer, and obtain the first hard mask layer 220 that is not affected by etchants (such as the third etchant and the fourth etchant). The semiconductor structure 300 etched by etchant), wherein FIG. 9 is a schematic cross-sectional view, and FIG. 10 is a top view.

In some embodiments, if the barrier layer is carbon or a carbonaceous material (eg, organic), the cleaning process may use an ashing process to remove the barrier layer.

It should be noted that, after the conventional step of removing the mask pattern, an ashing process is generally followed to remove the organic matter remaining on the surface. Therefore, if carbon or a carbon-containing substance is used for the barrier layer, the existing ashing process after etching can be directly followed to remove the barrier layer without adding another cleaning agent to remove the barrier layer.

In other embodiments, other non-ashable materials that cannot be removed by the ashing process can be selected for the barrier layer according to the process requirements. However, it should be noted that if the barrier layer is selected from non-ashable materials, the An additional cleaning process is performed with other cleaning agents, and after removing the barrier layer, an ashing process is performed. In addition, the cleaning agent must avoid corroding the substrate 210 , the first hard mask layer 220 , the second hard mask layer 230 , and avoid remaining in the top surface 234 of the second hard mask layer 230 or the trench T.

Some embodiments of the present disclosure provide a method of forming a semiconductor structure that avoids removing the mask by disposing a barrier layer to block the third etchant and the first hard mask layer before using the third etchant to remove the mask pattern. In the mask patterning step, the first hard mask layer is removed together, the first hard mask layer is concave, the critical dimension of the spacing between the columnar structures of the first hard mask layer is increased, and the extension support force is insufficient or even broken, and the finished product is Defective phenomena such as yield drop.

While the present disclosure has been described in detail in terms of certain implementations, other implementations are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

100: Method

210: Substrate

212: Upper surface

220: First hard cover layer

222: Sidewall

230: Second hard cover

232: Sidewall

234: Top Surface

240: Mask Pattern

250: Barrier

252: Top Surface

300: Semiconductor Structure

S110, S120, S130, S140, S150, S160, S170, S180: Steps

D1: first depth

D2: Second depth

T: groove

X: X axis

Y: Y axis

Z: Z axis

A more complete understanding of the present disclosure can be obtained by reading the following detailed description of embodiments with reference to the accompanying drawings. FIG. 1 exemplarily depicts a method of forming a semiconductor structure in some embodiments of the present disclosure; FIGS. 2 to 9 exemplarily describe a method for forming a semiconductor structure in some embodiments of the present disclosure, and are schematic cross-sectional views of each step, wherein FIGS. 8A to 8C are correspondingly removed from FIGS. 7A to 8C , respectively. A schematic cross-sectional view of the mask pattern in Figure 7C; and FIG. 10 exemplarily depicts a top view of a semiconductor structure obtained in some embodiments of the present disclosure.

100: Method

S110, S120, S130, S140, S150, S160, S170, S180: Steps

Claims (10)

A method of forming a semiconductor structure, comprising the steps of: providing a substrate; forming a first hard mask layer on the substrate, wherein the first hard mask layer comprises an oxide; forming a second hard mask layer on the first hard mask layer on the hard mask layer; forming a plurality of mask patterns on the second hard mask layer, wherein the mask patterns are separated by a plurality of grooves, the grooves expose the second hard mask layer, and have a a first depth, wherein the direction is perpendicular to an upper surface of the substrate in contact with the first hard mask layer; removing the first hard mask layer not covered by the mask patterns and not covered by the mask patterns the second hard mask layer, so that the grooves expose the plurality of sidewalls of the second hard mask layer, the plurality of sidewalls of the first hard mask layer and the upper surface of the substrate, and the grooves are formed by the first hard mask layer. A depth is deepened to a second depth; a barrier layer is formed in the trenches, and the barrier layer is connected to the sidewalls of the adjacent second hard mask layer; the mask patterns are removed using an etchant , wherein the barrier layer blocks the etchant from contacting the first hard mask layer; and a cleaning process is performed to remove the barrier layer. The method of claim 1, wherein in the step of forming the barrier layer in the trenches, the barrier layer only connects the adjacent first The sidewalls of the two hard mask layers do not extend toward the direction to fill the trenches. The method of claim 1, wherein the step of forming the barrier layer in the trenches includes forming the barrier layer to extend in the direction to fill the trenches, so that the barrier layer is connected to the adjacent first trenches. The sidewalls of a hard mask layer are in contact with the upper surface of the substrate. The method of claim 3, wherein a top surface of the barrier layer is flush with a top surface of the second hard cap layer in a horizontal direction. The method of claim 3, wherein a top surface of the barrier layer is lower than a top surface of the second hard mask layer in a horizontal direction. The method of claim 1, wherein the first hardmask layer and the second hardmask layer comprise different materials. The method of claim 6, wherein if the etchant contacts the second hard mask layer, the etchant does not etch the second hard mask layer. The method of claim 6, wherein the first hard mask layer comprises silicon oxide, and the second hard mask layer comprises silicon nitride. The method of claim 1, wherein the etching is used The removal of the mask patterns is a dry etching process, and the etchant includes carbon tetrafluoride, carbon difluoride, oxygen, or a combination thereof. The method of claim 1, wherein the barrier layer is carbon or a carbon-containing substance, and the cleaning process is an ashing process.

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