TW201631628A - Method of forming semiconductor device - Google Patents

Abstract

A method of forming a semiconductor structure, comprise following steps. First of all, a dielectric layer is provided. Next, a bilayer mask layer is formed on the dielectric layer, wherein the bilayer mask layer comprises two metal nitride layers having different metal concentration. Finally, a first opening is formed in the dielectric layer through the bilayer mask layer. Also, another method of forming a semiconductor structure comprises forming a mask layer having a metal concentration in a gradient.

Description

Method of forming a semiconductor component

The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming an opening in a dielectric layer using a nitrogen-rich mask layer.

An integrated circuit (IC) is constructed by means of patterned features formed in a substrate or different layers of film and an interconnect structure. For example, a damascene technique as a major multi-level interconnects technique in a semiconductor integrated circuit is to etch a circuit pattern in a dielectric material layer and then fill a conductive material such as copper into the circuit. The pattern is flattened to complete the fabrication of the metal interconnect.

With the continued miniaturization of semiconductor components and advances in semiconductor fabrication technology, double patterning lithography (DPL) or multiple patterning lithography (MPL) is often used in the industry to overcome the original exposure technology. limit. That is, by more than one lithography and etching process, a more complex and dense pattern is defined in a particular region of the target layer (eg, a layer of dielectric material).

However, after each lithography and etching process, some damage to the mask layer or changes in surface properties may occur, and then the mask layer is contacted again for subsequent The cleaning solution, etchant or chemical solvent used in the lithography and etching process may cause deformation or denaturation of the mask pattern of the mask layer, or expose and damage the surface of the target layer, thereby affecting the accuracy of the mask pattern. Degree, which will be detrimental to the subsequent process or lead to a decrease in the yield of subsequently completed semiconductor components.

Therefore, how to improve the patterning technology to obtain a complete patterned structure is a subject that the related art desires to improve.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a semiconductor element which can avoid deformation and denaturation of a mask layer and facilitate formation of a semiconductor element having better reliability.

To achieve the above object, an embodiment of the present invention provides a method of forming a semiconductor device, comprising the following steps. First, a dielectric layer is provided. Next, a double layer mask layer is formed on the dielectric layer, wherein the double layer mask layer comprises a two metal nitride layer having different metal concentrations. Finally, a first opening is formed in the dielectric layer through the double layer mask layer.

In order to achieve the above object, another embodiment of the present invention provides a method of forming a semiconductor device, comprising the following steps. A dielectric layer is first provided. Then, the dielectric layer is formed into a mask layer, wherein the mask layer comprises a metal nitride having a metal concentration in a gradient distribution. Finally, a first opening is formed in the dielectric layer through the mask layer.

A method of forming a semiconductor device of the present invention, which is formed on a dielectric layer The nitrogen-rich metal mask layer can prevent the etchant used in the etching process from excessively consuming the nitrogen component thereof through the metal mask layer, thereby effectively preventing deformation and denaturation of the metal mask layer.

100‧‧‧Base

101‧‧‧ Conductive layer

110‧‧‧ dielectric layer

111, 112‧‧‧ dielectric material layer

130‧‧‧Metal Nitride Layer

131, 133‧‧‧ first floor

132, 134‧‧‧ second floor

140‧‧‧ patterned mask layer

141‧‧‧ opening pattern

150‧‧‧Double mosaic structure

151, 152‧‧ ‧ openings

160‧‧‧ plug structure

170‧‧‧ patterned mask layer

171, 172‧‧‧ opening pattern

180‧‧‧ openings

190‧‧‧ plug structure

200‧‧‧ patterned photoresist layer

210‧‧‧Organic Dielectric Layer

220‧‧‧with hard cover

230‧‧‧ photoresist layer

231‧‧‧ opening pattern

400‧‧‧ patterned sacrificial mask

H1, H2‧‧‧ thickness

H‧‧‧thickness

1 to 5 are schematic views showing the steps of a method of forming a semiconductor device in a first embodiment of the present invention.

Figure 6 is a schematic view showing the steps of a method of forming a semiconductor device in a second embodiment of the present invention.

7 to 9 are schematic views showing the steps of a method of forming a semiconductor device in a third embodiment of the present invention.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 5, which are schematic diagrams showing the steps of a method for forming an embodiment of the present invention. First, as shown in FIG. 1, a substrate 100 is provided, and at least one conductive layer 101 is formed on or in the substrate 100. The substrate 100 may be a substrate having a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or A silicon-on-insulator (SOI) substrate or the like may also be a substrate having a non-semiconductor material, such as a glass substrate, but not limited thereto. In an embodiment, the conductive layer 101 may be various conductive elements or metal contacts, such as a gate, a contact plug, and a via plug formed on the substrate 100. A plug or a wire or the like, or a drain, a source, or the like formed in the substrate 100. However, in other embodiments, other semiconductor components (not shown) may alternatively be included in the substrate 100.

Then, as shown in FIG. 1 , a dielectric layer 110 , a metal mask layer 130 and a patterned mask layer 140 are sequentially formed on the substrate 100 to cover the conductive layer 101 of the substrate 100 . In an embodiment, the dielectric layer 110 may comprise a plurality of layers of dielectric material 111, 112, such as silicon oxide (SiO), silicon oxynitride (SiNO), silicon tantalum nitride (silicon). Carbonitride, SiCN) and other low dielectric constant materials (dielectric constant value less than 3.9) layer, but not limited to this. In another embodiment, an etch stop layer (not shown) may be formed in the dielectric layer 110, for example, formed between the two dielectric material layers 111, 112 to form a stop when the subsequent openings are formed. The layer may alternatively be formed to form a dielectric layer (not shown) having only a single layer structure.

In addition, it is particularly noted that, in an embodiment, the metal mask layer 130 is a nitrogen-rich metal nitride layer, and preferably has a two-layer structure, and at least the top layer of the two-layer structure is rich. A metal nitride layer of nitrogen. As shown in FIG. 1, the metal mask layer 130 includes a first layer 131 and a second layer 132 on the first layer, wherein the first layer 131 and the second layer 132 may optionally contain the same metal nitrogen. The compound includes, for example, titanium nitride (TiN) or tantalum nitride (TaN), but only the second layer 132 has a nitrogen-rich metal nitride layer, but limit. In another embodiment, both the first layer 131 and the second layer 132 may have a nitrogen-rich metal nitride layer, but respectively contain different concentrations of titanium nitride (or tantalum nitride). That is, in an embodiment, the second layer 132 can be relative to the first layer 131 has a lower titanium (or yttrium) or, in other words, the second layer 132 has a higher concentration of nitrogen relative to the first layer 131. For example, the ratio of titanium (or cerium) to nitrogen in the first layer 131 is, for example, 0.8 to 0.9, preferably 0.87; and the ratio of titanium (or cerium) to nitrogen in the second layer 132 is, for example, 0.6 to 0.8, preferably 0.7, but not limited to this. In addition, in another embodiment, the first layer 131 may have a larger thickness relative to the second layer 132. For example, the thickness H1 of the first layer 131 is substantially from about 30 nm to 400 nm. Preferably, the thickness of the second layer 132 (nitrogen-rich metal nitride layer) H2 is substantially no greater than 10 angstroms, preferably about 1 angstrom to 10 angstroms. The patterned mask layer 140 has an opening pattern 141, for example, a material having an etching selectivity ratio with the metal mask layer 130, such as yttrium oxide, silicon nitride, niobium oxynitride, niobium carbonitride, etc. , but not limited to this.

Next, as shown in FIG. 2, a patterned photoresist layer 200 is formed on the substrate 100 to cover the patterned mask layer 140. The patterned photoresist layer 200 has at least one opening pattern 231. Specifically, in an embodiment, the patterned photoresist layer 200 may have a three-layer structure including an organic dielectric layer (ODL) 210, for example, I- of a wavelength of 365 nanometers (nm). A line photoresist material or a novolac resin; a silicon-containing hard mask (SHB) layer 220, for example, an organo-silicon polymer or A polysilicon layer is formed; and a photoresist layer 230 is formed, for example, of a photoresist material having a wavelength of 248 nm or 193 nm, such as a KrF photoresist layer, as shown in FIG. . However, the patterned photoresist layer 200 of the present invention is not limited to the foregoing structure or material. In another embodiment, the patterned photoresist layer 200 may alternatively have a double layer structure or include other materials, such as additional A bottom anti-reflective coating (BARC, not shown) is formed.

It should be further noted that the present invention is described as a "dual damascene process" of "trench first", for example, including an opening pattern 141 defined by the patterned mask layer 140. a trench, and an opening pattern 231 of the photoresist layer 230 (patterned photoresist layer 200) is used to define a via hole or a contact hole partially overlapping the contact trench, such as Figure 2 shows. However, it should be readily understood by those skilled in the art that in other embodiments of the present invention, it can also be applied to a "dual damascene process" of "via first", using a patterned mask layer 140 first. The opening pattern defines a dielectric hole/contact hole, and then a trench is defined by the opening pattern of the photoresist layer 230; or is applied to other dual damascene processes well known in the art, such as "self-aligned" Double mosaic process, etc.

Subsequently, as shown in FIG. 3, an etching process may be directly performed to form at least one opening 151 in the dielectric layer 110 through the patterned photoresist layer 200. The etching process is, for example, a dry etching process, a wet etching process, or a dry etching process and a wet etching process to transfer the pattern of the patterned photoresist layer 200 directly to the underlying metal mask layer 130 and The electrical layer 110 (comprising dielectric material layers 112, 111) forms an opening 151 that penetrates the dielectric layer 110 and directly contacts the conductive layer 101. Then, as shown in FIG. 4, the patterned photoresist layer 200 is completely removed. In addition, in an embodiment, after the etching process, a cleaning process may be performed, for example, the surface of the previously formed opening 151 is cleaned with argon (Ar) to remove the etching residue. However, the etching process is not limited to the foregoing manner. In other embodiments, the pattern of the patterned photoresist layer 200 may be transferred to the underlying metal mask layer 130, and the patterned photoresist layer is removed. 200. Subsequent to the patterned metal mask layer as an etch mask, the dielectric layer 110 is etched to form an opening 151.

It should be particularly noted that since the method of the present invention forms a nitrogen-rich metal mask layer 130 (such as the second layer 132 described above), it can be avoided when the etching process is performed to remove the patterned photoresist layer 200. The etchant used in the etching process includes, for example, oxygen (O ₂ ), ozone (O ₃ ), carbon monoxide (CO), carbon dioxide (CO ₂ ), carbonic acid chloride (COCl ₂ ), or a combination thereof, and the like. The metal mask layer 130 reacts to consume nitrogen of the metal mask layer 130 to cause deformation and denaturation. In addition, in another embodiment, when the opening pattern 231 is defined by the patterned photoresist layer 200, if the after-develop-inspection (ADI) process is completed, it is found that the patterned light needs to be removed. The resist layer 200 is found after redefining a new opening pattern (not shown), or after completing the after-etch-inspection (AEI) process of forming the opening pattern 141 of the patterned mask layer 140. When the patterned mask layer 140 needs to be removed for reworking, the present invention can utilize the nitrogen-rich metal mask layer 130 to block the etchant used in the removal process, thereby avoiding excessive reaction and consumption of the etchant. The nitrogen in the metal mask layer 130 effectively prevents deformation and denaturation of the metal mask layer 130.

Finally, the patterned mask layer 140 is further used as an etch mask to remove the exposed portion of the metal mask layer 130 (including the second layer 132 and the first layer 131) to form an opening in the dielectric layer 110. 152, as shown in Figure 5. Specifically, the opening 152 is formed, for example, only in the dielectric material layer 112 and partially overlaps the opening 151 to form a dual damascene structure (opening) 150 in the dielectric layer 110, as shown in FIG. Show. Subsequently, the patterned mask layer 140 can be completely removed, and a plug structure 160 is formed within the dual damascene structure 150 to directly contact and electrically connect the conductive regions 101 of the substrate 100. In an embodiment, the plug structure 160 may include a barrier layer (not shown), such as a titanium (Ti) layer, a titanium nitride layer, a tantalum (Ta) layer, or a tantalum nitride layer; And a contact metal layer (not shown), such as tungsten (W) or aluminum (Al), but not limited thereto. And, in another embodiment, the plug structure 160 The forming method is, for example, after the patterned mask layer 140 is completely removed, a barrier material layer (not shown) and a metal material layer (not shown) are sequentially formed in the dual damascene structure 150, and Removing a portion of the metal material layer and the barrier material layer through a planarization process, such as a chemical mechanical polishing process, an etching process, or a combination of the two, to form a plug structure including the barrier layer and the contact metal layer 160, while completely removing the metal mask layer 130.

The formation method of the first embodiment of the present invention is completed by the foregoing steps. Wherein, the formation method is to form a nitrogen-rich metal mask layer on the dielectric layer, and the metal mask layer can prevent the etchant used in the etching process from excessively consuming the nitrogen component thereof, thereby effectively preventing the metal mask. Deformation and denaturation of the cover layer. Accordingly, the method of the present invention can be applied to the aforementioned dual damascenes process to avoid excessive etchant, cleaning solution or chemical solvent used in the second patterning/etching process or the subsequent cleaning process. The nitrogen component in the mask layer is reacted or consumed. Alternatively, after an after-develop-inspection (ADI) process or an after-etch-inspection (AEI) process, it is found that another work is required to remove the patterned photoresist layer 200. To redefine a new opening pattern (not shown), the etchant used in the removal process may be avoided, or the cleaning solution or chemical solvent used in the subsequent cleaning process may overreact or consume nitrogen in the mask layer. ingredient. Therefore, the formation method of the present invention mainly utilizes a nitrogen-rich metal mask layer to prevent deformation and denaturation of the mask layer.

However, those of ordinary skill in the art will also appreciate that the method of forming the present invention is not limited to the foregoing, and may include other steps or embodiments. Other embodiments or variations of the method of forming a semiconductor device of the present invention will be described below. In order to simplify the description, the following description mainly focuses on the differences of the embodiments, and is no longer the same. The details are repeated. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Referring to FIG. 6, there is shown a schematic diagram of the steps of a method of forming a semiconductor device in a second embodiment of the present invention. The forming method of the present embodiment is substantially the same as the first embodiment described above, and the difference is as shown in FIG. 6, mainly because the metal mask layer 130 of the present embodiment also has a double-layer nitrogen-rich metal nitride layer. And including a first layer 133 and a second layer 134. However, in the present embodiment, the concentration of the metal contained in the second layer 134 is gradually decreasing from the bottom toward the top, that is, the nitrogen content of the second layer 134 is gradually increasing from the bottom toward the top, as in the first step. Figure 6 shows. In one embodiment, the top portion of the second layer 134 having the highest nitrogen concentration has a thickness h that is substantially no greater than 10 angstroms, preferably from about 1 angstrom to 10 angstroms. The other steps of the embodiment are the same as those of the foregoing embodiment except for the foregoing differences, and therefore will not be described again. However, the present invention is not limited thereto. In another embodiment, a nitrogen-rich metal nitride layer (not shown) having a single layer structure may be selected, and the nitrogen-rich metal nitride layer is included. The metal concentration is gradually decreasing from the bottom toward the top (that is, the nitrogen content of the metal is gradually increasing from the bottom toward the top). Wherein, the nitrogen-rich metal nitride layer has a thickness substantially, for example, between 30 nm and 400 nm, wherein the top portion having the highest nitrogen concentration has a thickness of not more than 10 angstroms. Preferably, it is about 1 angstrom to 10 angstroms.

Next, please refer to FIGS. 7 to 9. FIG. 9 is a schematic view showing the steps of a method of forming a semiconductor device in a third embodiment of the present invention. Although the formation method of this embodiment defines the contact groove pattern by a double exposure technique, the front stage process is substantially the same as that of the first embodiment of the first embodiment. Specifically, the main difference is that the double-layer metal mask layer 130 (including the first layer 131 and the second layer 132) as shown in FIG. 1 is formed. Thereafter, a patterned mask layer 170 as shown in FIG. 7 is formed. In one embodiment, the patterned mask layer 170 has an opening pattern 171 to define a portion of the dielectric via/contact hole pattern. In addition, the patterned mask layer 170 preferably includes a material having an etching selectivity ratio with the metal mask layer 130, such as hafnium oxide, silicon nitride, hafnium oxynitride, niobium carbonitride, etc., but not This is limited to this.

Next, as shown in FIG. 7, a patterned sacrificial mask layer 400 is formed on the substrate 100 to fill the opening pattern 171 of the patterned mask layer 170 to define another portion of the dielectric hole/contact hole pattern. Subsequently, an etching process is performed, such as a dry etching process, a wet etching process, or a dry etching process and a wet etching process to transfer the pattern of the patterned sacrificial mask layer 400 to the patterned mask layer below. 170, an opening pattern 172 is formed. The patterned sacrificial mask layer 400 is then completely removed.

Referring to FIG. 8 , after the opening pattern 172 is formed, another etching process is directly performed, such as a dry etching process, a wet etching process, or a sequential dry etching process and a wet etching process to pattern the mask. The opening patterns 171, 172 of the layer 170 are directly transferred to the underlying metal mask layer 130 (including the second layer 134 and the first layer 133), and the dielectric layer 110 (including the dielectric material layers 112, 111) is formed to be worn. The opening 180 of the conductive layer 101 is directly contacted through the dielectric layer 110. Thereafter, a cleaning process may be selectively performed, for example, by cleaning the surface of the opening 180 formed as described above with argon gas to remove etching residues.

In this embodiment, although the operation mode of the photolithography-photolithography-etch (2P1E) is described, for example, the opening patterns 171 and 172 are formed in the patterned mask layer 170, and at the same time The opening patterns 171, 172 are transferred to the dielectric layer 110 to form the opening 180, but the present invention does not limit. In another embodiment, the operation may be performed by a photolithography-etch-photolithography-etch (2P2E) operation, for example, after forming the opening pattern 171, an etching process is performed. The opening pattern 171 is transferred to the dielectric layer 110 to form a portion of the opening 180, and the opening pattern 172 and the other portion of the opening 180 are sequentially formed.

Finally, as shown in FIG. 9, the patterned mask layer 170 is completely removed, and a plug structure 190 is formed in the opening 180 to directly contact and electrically connect the conductive layer 101 of the substrate 100. The method for forming the plug structure 190 is, for example, after the patterned mask layer 170 is completely removed, a barrier material layer (not shown) and a metal material layer are sequentially formed in the opening 180 (not drawn). And removing a portion of the metal material layer and the barrier material layer through a planarization process, such as a chemical mechanical polishing process, an etching process, or a combination of the two, to form a barrier layer (not shown) And a plug structure 190 contacting the metal layer (not shown) while completely removing the metal mask layer 130.

The formation method of the third embodiment of the present invention is completed by the foregoing steps, wherein the formation method is to form a nitrogen-rich metal mask layer on the dielectric layer. Accordingly, the method of the present invention can be used in a double exposure technique to define a dielectric via/contact hole pattern to avoid etchants, cleaning solutions or chemical solvents used in the second patterning/etching process or subsequent cleaning processes. Excessive reaction or consumption of nitrogen in the mask layer, or after completion of the post-development (ADI) process or post-etch inspection (AEI) process, a rework step is required to remove the patterned photoresist layer To redefine the new opening pattern to prevent deformation and denaturation of the mask layer.

In addition, in other embodiments, a double-layered metal mask layer may be selected, but only the bottom layer thereof has a nitrogen-rich metal nitride layer (not shown), whereby the pattern may be omitted. The mask layer 170 is formed to directly form the opening pattern on the metal mask layer, and directly as the top layer of the metal mask layer as an etching mask for forming the dielectric hole/contact hole. At the same time, the underlying layer (nitrogen-rich metal nitride layer) of the metal mask layer is used to block the patterning/etching process or the etchant, cleaning solution or chemical solvent used in the subsequent cleaning process to avoid excessive reaction or consumption of the mask. The nitrogen content in the layer. The metal mask layer having only the bottom layer and the nitrogen-rich metal nitride layer may be further applied to the first and second embodiments described above, and details are not described herein.

In summary, the method of forming a semiconductor device of the present invention is mainly to form a metal mask layer comprising a nitrogen-rich metal mask layer on a dielectric layer. Wherein, the metal mask layer may have a metal nitride of a two-layer structure, such as including titanium nitride or tantalum nitride; and the top layer of the double layer structure preferably has a lower metal concentration relative to the bottom layer. (That is, its top layer can have a higher nitrogen concentration relative to the bottom layer) and a thinner thickness (less than 10 angstroms, preferably about 1 angstrom to 10 angstroms). For example, the ratio of the metal concentration in the underlayer to the nitrogen concentration is, for example, 0.8 to 0.9, preferably 0.87, and the ratio of the metal concentration of the top layer to the nitrogen concentration is, for example, 0.6 to 0.8. Conversely, the bottom layer can also have a lower metal concentration relative to the top layer (i.e., have a higher nitrogen concentration). In addition, the concentration of the metal contained in the top layer may also be selected to be a gradient, for example, decreasing from the bottom of the bottom layer toward the top (that is, the concentration of nitrogen contained in the top layer may also be selected from the bottom of the bottom layer toward The top is in increasing gradient). Alternatively, the metal mask layer may have a single layer structure, and the metal concentration of the single layer metal mask layer is gradually decreased from the bottom to the top of the bottom layer (that is, the nitrogen content thereof is from The bottom portion is progressively increasing toward the top; and the top portion of the metal mask layer having the highest nitrogen concentration has a thickness of substantially no more than 10 angstroms, preferably about 1 angstrom = 10 angstroms. By forming the aforementioned nitrogen-rich metal mask layer, the formation method of the present invention can prevent the etchant used in the etching process from excessively consuming the nitrogen component therein to avoid deformation and denaturation of the metal mask layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Base

101‧‧‧ Conductive layer

110‧‧‧ dielectric layer

111, 112‧‧‧ dielectric material layer

130‧‧‧Metal Nitride Layer

133‧‧‧ first floor

134‧‧‧ second floor

140‧‧‧ patterned mask layer

141‧‧‧ opening pattern

H‧‧‧thickness

Claims (16)

A method of forming a semiconductor device, comprising the steps of: providing a dielectric layer; forming a double layer mask layer on the dielectric layer, wherein the double layer mask layer comprises a dimetal nitride layer having a different metal concentration; A first opening is formed in the dielectric layer through the double layer mask layer. The method of forming a semiconductor device according to claim 1, wherein the two metal nitride layer comprises a first layer and a second layer disposed on the first layer, and the metal of the second layer The concentration is less than the metal concentration of the first layer. The method of forming a semiconductor device according to claim 2, wherein the metal concentration of the second layer is a gradient distribution. The method of forming a semiconductor device according to claim 3, wherein the metal concentration of the second layer is gradually decreasing from the bottom toward the top. The method of forming a semiconductor device according to claim 2, wherein a ratio of a metal concentration of the second layer to a nitrogen concentration is substantially between 0.6 and 0.8. The method of forming a semiconductor device according to claim 2, wherein the first layer and the second layer each comprise titanium nitride or tantalum nitride. The method of forming a semiconductor device according to claim 2, wherein the second layer has a thickness of from 1 angstrom to 10 angstroms. The method of forming a semiconductor device according to claim 1, wherein the first opening comprises a dual damascene structure. The method of forming a semiconductor device according to claim 8, wherein the forming step of the first opening comprises: forming a trench in the dielectric layer; and forming a dielectric hole in the dielectric layer or A contact hole. The method of forming a semiconductor device according to claim 1, further comprising: forming a second opening in the dielectric layer through the double-layer mask layer, wherein the first opening and the second opening are utilized A double exposure technique is formed. A method of forming a semiconductor device, comprising the steps of: providing a dielectric layer; forming a mask layer on the dielectric layer, wherein the mask layer comprises a metal nitride layer having a metal concentration in a gradient distribution; A first opening is formed in the dielectric layer through the mask layer. The method of forming a semiconductor device according to claim 11, wherein the top of the mask layer has a minimum metal concentration. The method of forming a semiconductor device according to claim 12, wherein the ratio of the metal concentration to the nitrogen concentration is substantially between 0.6 and 0.8. The method of forming a semiconductor device according to claim 12, wherein the top portion has a thickness ranging from 1 angstrom to 10 angstroms. The method of forming a semiconductor device according to claim 11, wherein the mask layer comprises titanium nitride or tantalum nitride. The method of forming a semiconductor device according to claim 11, wherein the mask layer has a thickness ranging from 30 nm to 400 nm.