TWI769789B - 陣列開關電路及系統晶片封裝結構 - Google Patents
陣列開關電路及系統晶片封裝結構 Download PDFInfo
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Abstract
陣列開關電路包括基板、多個訊號導電墊以及多個訊號擴展引腳,該些訊號導電墊互相間隔地設置於基板且排列成訊號導電墊陣列,每一訊號導電墊於訊號導電墊陣列中具有一列位置及一行位置,對應同一列位置的二相鄰的訊號導電墊之間設有列訊號開關,對應同一行位置的二相鄰的訊號導電墊之間設有行訊號開關。該些訊號擴展引腳分別透過多個訊號擴展開關與位在訊號導電墊陣列的側邊的訊號導電墊相連接。
Description
本發明有關於一種系統晶片封裝結構,尤指一種可程式化的系統晶片封裝結構。
傳統的晶片系統封裝是將多顆晶片一起封裝成一個積體電路(IC),其中積體電路中晶片與晶片之間的連接以及封裝的輸入/輸出腳位(IO pin)之間的連接都是透過導線重佈層(Re-distribution Layer;RDL)進行繞線,當RDL的繞線設計完成後,再交由封裝廠進行製造與封裝。最後,封裝完後在交由測試場進行IC測試。由於所有的RDL皆為封裝廠進行客製化生產,所以當封裝後之IC經過測試場測試後,發現需要修改RDL的繞線或更換IC中的晶片時,則必須重新設計RDL,如此一來將增加產品開發時間以及增加研發成本。需要較長的研發時間。再者,若是遇到產量較少的產品,將會遭遇到封裝場不接單的問題。
有鑑於此,目前有需要一種改良的系統晶片封裝架構,可改善上述缺失。
本發明提供一種陣列開關電路、電路開關元件及系統晶片封裝結構,使系統晶片封裝結構中各晶片之間的連接以及封裝的I/O腳位之間的連接具備可程式化之功能,達到減少產品開發時間以及降低研發成本的目標。
依據本發明的一實施例,提供一種陣列開關電路,包括基板、多個訊號導電墊、以及多個訊號擴展引腳,該些訊號導電墊互相間隔地設置於基板,該些訊號導電墊排列成訊號導電墊陣列,每一訊號導電墊於訊號導電墊陣列中具有一列位置及一行位置,對應同一列位置的二相鄰的訊號導電墊之間設有列訊號開關,對應同一行位置的二相鄰的訊號導電墊之間設有行訊號開關。該些訊號擴展引腳分別透過多個訊號擴展開關與位在訊號導電墊陣列的側邊的訊號導電墊相連接。
依據本發明的一實施例,提供一種開關元件,包括電晶體、第一反相器以及第二反相器。其中電晶體包含閘極端、汲極端、源極端以及基體端,閘極端用於接收控制訊號,電晶體依據控制訊號之電壓位準決定汲極端與源極端之間處於導通狀態或截止狀態。第一反相器具有第一輸入端及第一輸出端,第一輸入端連接於汲極端。第二反相器具有第二輸入端及第二輸出端,第二輸入端連接於第一輸出端,而第二輸出端連接於基體端。
依據本發明的一實施例,提供一種系統晶片封裝結構,包含導線重佈層、多個晶片、陣列開關電路以及矽穿孔層。該些晶片連接於導線重佈層,陣列開關電路的訊號導電墊透過導線重佈層連接於該些晶片,且導線重佈層位於陣列開關電路之上方。矽穿孔層連接於訊號導電墊,且矽穿孔層位於陣列開關電路之下方。
當系統晶片封裝結構中的各晶片之間的連接或者封裝的I/O腳位之間的連接,因為用途上的需求要進行修改時,只需調整列控制訊號之位準使列訊號開關處於導通狀態或截止狀態,或者調整行控制訊號之位準使行訊號開關處於導通狀態或截止狀態,便可達到重新設計各晶片之間的繞線或者封裝的I/O腳位之間的繞線,無須重新設計導線重佈層,達到減少產品開發時間以及降低研發成本的目標。此外,本發明的開關元件可作為陣列開關電路中的列訊號開關或
者行訊號開關,透過改變開關元件之電晶體的基體端電壓來降低電晶體的臨界電壓。當電晶體的臨界電壓降低且電晶體的汲極電壓不變時,流經電晶體的電流上升且電晶體的通道電阻下降。當通道電阻下降時,訊號的時間常數下降,達到提高訊號傳輸速度的技術效果。
100~500、400A:陣列開關電路
11:基板
12:訊號導電墊
13:列訊號開關
14:行訊號開關
15:訊號擴展引腳
16:訊號擴展開關
S:訊號導電墊陣列
S11:第一側邊
S12:第二側邊
S13:第三側邊
S14:第四側邊
A:系統晶片封裝結構
A1:導線重佈層
A2:陣列開關電路
A3:矽穿孔層
C1:第一晶片
C11:第一訊號接腳
C12:第一電源接腳
C2:第二晶片
C21:第二訊號接腳
C22:第三訊號接腳
C23:第二電源接腳
C24:第三電源接腳
11:基板
12、12A~12D:訊號導電墊
13、13A~13B:列訊號開關
14、14A:行訊號開關
15:訊號擴展引腳
16:訊號擴展開關
17:列訊號傳輸捷徑
18:行訊號傳輸捷徑
21、21A~21D:電源導電墊
22、22A~22B:列電源開關
23、23A:行電源開關
24:電源擴展引腳
25:電源擴展開關
S:訊號導電墊陣列
P:電源導電墊陣列
P1~P2:側邊
31:第一基板
41:第二基板
32:第一訊號導電墊
33:第一列訊號開關
34:第一行訊號開關
35:第一訊號擴展引腳
36:第一訊號擴展開關
SA:第一訊號導電墊陣列
SA1~SA4:側邊
42:第二訊號導電墊
43:第二列訊號開關
44:第二行訊號開關
45:第二訊號擴展引腳
46:第二訊號擴展開關
SB:第二訊號導電墊陣列
SB1~SB4:側邊
600:開關元件
61:第一電晶體
611:第一閘極端
612:第一汲極端
613:第一源極端
614:基體端
62:第一反相器
621:第二電晶體
6211:第二閘極端
6212:第二汲極端
6213:第二源極端
622:第三電晶體
6221:第三閘極端
6222:第三汲極端
6223:第三源極端
63:第二反相器
631:第四電晶體
6311:第四閘極端
6312:第四汲極端
6313:第四源極端
632:第五電晶體
6321:第五閘極端
6322:第五汲極端
6333:第五源極端
Vdd:電壓源
700:開關元件
71:第一電晶體
711:第一閘極端
712:第一汲極端
713:第一源極端
714:基體端
72:第一反相器
721:第二電晶體
722:第三電晶體
73:第二反相器
731:第四電晶體
732:第五電晶體
圖1為本發明一實施例的系統晶片封裝結構的示意圖;圖2為本發明第一實施例的陣列開關電路的示意圖;圖3為圖2的陣列開關電路的運作示意圖;圖4為圖2的陣列開關電路的另一運作示意圖;圖5為本發明第二實施例的陣列開關電路的示意圖;圖6為本發明第三實施例的陣列開關電路的示意圖;圖7為圖6的陣列開關電路的運作示意圖;圖8為圖6的陣列開關電路的另一運作示意圖;圖9為本發明第四實施例的陣列開關電路的示意圖;圖10為本發明第五實施例的陣列開關電路的示意圖;圖11為本發明第六實施例的陣列開關電路的示意圖;圖12為本發明第一實施例的開關元件的示意圖;以及圖13為本發明第二實施例的開關元件的示意圖。
圖1為本發明一實施例的系統晶片封裝結構的示意圖,如圖1所示,系統晶片封裝結構A包含第一晶片C1、第二晶片C2、導線重佈層A1(Re-
distribution layer;RDL)、陣列開關電路A2、以及矽穿孔層A3(through silicon via;TSV),第一晶片C1以及第二晶片C2設置於導線重佈層A1的上表面A11,且陣列開關電路A2設置於導線重佈層A1與矽穿孔層A3之間。第一晶片C1例如可設有第一訊號接腳C11及第一電源接腳C12,第二晶片C2例如可具有第二訊號接腳C21、第三訊號接腳C22、第二電源接腳C23以及第三電源接腳C24,而第一訊號接腳C11、第一電源接腳C12、第二訊號接腳C21、第三訊號接腳C22、第二電源接腳C23以及第三電源接腳C24分別透過導線重佈層A1的多條互不相連的導線線路與陣列開關電路A2的多個不同位置的導電墊相連接,該些訊號導電墊連接於矽穿孔層A3,至於陣列開關電路A2的詳細架構將於後續闡述。
圖2為本發明第一實施例的陣列開關電路的示意圖。如圖2所示,第一實施例之陣列開關電路100包括一基板11、多個訊號導電墊12、多個列訊號開關13、多個行訊號開關14、多個訊號擴展引腳15以及多個訊號擴展開關16,該些訊號導電墊12互相間隔地設置於基板11且於基板11上排列成訊號導電墊陣列S。訊號導電墊陣列S包含第一側邊S11、第二側邊S12、第三側邊S13以及第四側邊S14,第一側邊S11相對於第三側邊S13,而第二側邊S12相對於第四側邊S14。每一訊號導電墊12於訊號導電墊陣列S中具有一列位置及一行位置。關於該些列訊號開關13以及該些行訊號開關14於基板11上的配置,對應同一列位置的任二相鄰的訊號導電墊12之間設置一個列訊號開關13,至於對應同一行位置的任二相鄰的訊號導電墊12之間設置一個行訊號開關14。每一列訊號開關13以及每一行訊號開關14常態處於截止狀態,當列訊號開關13接收到導通的列控制訊號時,列訊號開關13從截止狀態切換為導通狀態。當行訊號開關14接收到導通的行控制訊號時,行訊號開關14從截止狀態切換為導通狀態。
該些訊號擴展引腳15間隔地設置於基板11且靠近於訊號導電墊陣列S的第一側邊S11、第二側邊S12、第三側邊S13以及第四側邊S14。該些訊號
擴展引腳15中對應同一列位置的兩者分別靠近第一側邊S11及第三側邊S13,而該些訊號擴展引腳15中對應同一行位置的兩者分別靠近第二側邊S12及第四側邊S14。
該些訊號擴展開關16間隔地設置於基板11且靠近於訊號導電墊陣列S之第一側邊S11、第二側邊S12、第三側邊S13以及第四側邊S14。該些訊號擴展開關16中對應同一列位置的兩者分別靠近第一側邊S11及第三側邊S13,而該些訊號擴展開關16中對應同一行位置的兩者分別靠近第二側邊S12及第四側邊S14。該些訊號擴展開關16使得該些訊號擴展引腳15分別與佈置在第一側邊S11、第二側邊S12、第三側邊S13以及第四側邊S14的該些訊號導電墊12可為相互連接。
圖3為圖2的陣列開關電路的運作示意圖。共同參閱圖1及圖3,訊號導電墊12A對應於訊號導電墊陣列S的第一列位置以及第二行位置,且電性連接於第一晶片C1的第一訊號接腳C11。訊號導電墊12B對應於訊號導電墊陣列S的第一列位置以及第三行位置。訊號導電墊12C對應於訊號導電墊陣列S的第二列位置以及第三行位置且電性連接於第二晶片C2的第二訊號接腳C21。訊號導電墊12D對應於訊號導電墊陣列S的第一列位置以及第四行位置且電性連接於第二晶片C2的第三訊號接腳C22。列訊號開關13A連接於訊號導電墊12A與訊號導電墊12B之間,列訊號開關13B連接於訊號導電墊12B與訊號導電墊12D之間,而行訊號開關14A連接於訊號導電墊12B與訊號導電墊12C之間。
假設用途上的需求,第一晶片C1的第一訊號接腳C11需要電性連接於第二晶片C2的第二訊號接腳C21,只需分別提供導通的列控制訊號及行控制訊號至列訊號開關13A以及行訊號開關14A,以使列訊號開關13A以及行訊號開
關14A處於導通狀態,如此一來,第一晶片C1的第一訊號接腳C11電性連接於第二晶片C2的第二訊號接腳C21。
圖4為圖2的陣列開關電路的另一運作示意圖。共同參閱圖1及圖4,假設因為用途上的需求,第一晶片C1的第一訊號接腳C11電性連接於第二晶片C2的第三訊號接腳C22,只需分別提供導通的列控制訊號至兩個列訊號開關13A以及13B,以使兩個列訊號開關13A以及13B處於導通狀態,如此一來,第一晶片C1的第一訊號接腳C11電性連接於第二晶片C2的第三訊號接腳C22。
圖5為本發明第二實施例的陣列開關電路的示意圖。第二實施例之陣列開關電路200相較於第一實施例之陣列開關電路100,第二實施例之陣列開關電路200更包括多個列訊號傳輸捷徑17以及多個行訊號傳輸捷徑18。該些訊號擴展引腳15互相間隔地設置於基板11且圍繞於訊號導電墊陣列S之外側,該些訊號擴展引腳15中對應同一列位置之兩者之間連接有一個列訊號傳輸捷徑17,該些訊號擴展引腳15中對應同一行位置之兩者之間連接有一個行訊號傳輸捷徑18。
關於圖5的實施例,列訊號傳輸捷徑17以及行訊號傳輸捷徑18分別為東西向以及南北向的高速傳輸通道。假設訊號要從靠近訊號導電墊陣列S的第一側邊S11的訊號導電墊12傳送到靠近訊號導電墊陣列S的第三側邊S13的訊號導電墊12,走普通路徑需要經過大量的列訊號開關13,訊號會有較大的延遲,且降低訊號完整性。但透過東西向的高速傳輸通道之設置,列訊號只需經過一個列訊號開關13抵達訊號擴展引腳15,再由訊號擴展引腳15通過高速傳輸通道抵達另一個訊號擴展引腳15後再經過另一個列訊號開關13,有效提升訊號傳輸性能。同理,假設訊號要從訊號導電墊陣列S的第二側邊S12的訊號導電墊12傳送
到訊號導電墊陣列S的第四側邊S14的訊號導電墊12,若走普通路徑需要經過大量的行訊號開關14,訊號會有較大的延遲,且會降低訊號完整性。但透過南北向的高速傳輸通道之設置,行訊號只需經過一個行訊號開關14抵達訊號擴展引腳15,再由訊號擴展引腳15通過高速傳輸通道抵達另一個訊號擴展引腳15後再經過另一個行訊號開關14,有效提升訊號傳輸性能。
圖6為本發明第三實施例的陣列開關電路的示意圖。如圖6所示,第三實施例之陣列開關電路300相較於圖5之陣列開關電路200,第三實施例之陣列開關電路300更包括多個電源導電墊21、多個列電源開關22、多個行電源開關23、多個電源擴展引腳24以及多個電源擴展開關25,因此第三實施例之陣列開關電路300為一種混合型的開關電路。該些電源導電墊21互相間隔地設置於基板11且排成電源導電墊陣列P,電源導電墊陣列P與訊號導電墊陣列S彼此電性隔絕,且每一電源導電墊21於電源導電墊陣列P都具有一列位置及一行位置。
關於該些列電源開關22與該些行電源開關23於基板11上的配置,其中對應電源導電墊陣列P的同一列位置的任二相鄰的電源導電墊21之間設置一個列電源開關22,對應電源導電墊陣列P的同一行位置的二相鄰的電源導電墊21之間設置一個行電源開關23。每一列電源開關22以及每一行電源開關23常態處於截止狀態,當列電源開關22接收到導通的列控制訊號時,列電源開關22從截止狀態切換為導通狀態。當行電源開關23接收到導通的行控制訊號時,行電源開關23從截止狀態切換為導通狀態。
該些電源擴展引腳24互相間隔地設置於基板11且靠近於電源導電墊陣列P之兩個相對的側邊P1及P2,而該些電源擴展引腳24中對應同一列位置的兩者分別靠近該兩側邊P1及P2。
該些電源擴展開關25互相間隔地設置於基板11且靠近於電源導電墊陣列P之該兩側邊P1及P2,而該些電源擴展開關25中對應同一列位置的兩者分別位於靠近該兩側邊P1及P2的電源導電墊21與電源擴展引腳24之間。該些電源擴展開關25使得該些電源擴展引腳24分別與佈置在該兩側邊P1及P2的該些電源導電墊21可為相互連接。
關於圖6的實施例,屬於一種混合型開關陣列,其區分為訊號型開關矩陣以及電源型開關矩陣,如此可以分別針對用途來提升各種開關之性能。例如,使用在電源傳輸的列電源開關與行電源開關需要較小的導通電阻,故通常選擇較大尺寸的電晶體來製作。使用在訊號傳輸的列訊號開關與行訊號開關通常選擇較小尺寸的電晶體來製作,以便降低寄生電容。
圖7為圖6的陣列開關電路的運作示意圖。共同參閱圖1及圖7,電源導電墊21A對應於電源導電墊陣列P的第一列位置以及第二行位置,且電性連接於第一晶片C1的第一電源接腳C12。電源導電墊21B對應於電源導電墊陣列P的第一列位置以及第三行位置。電源導電墊21C對應於電源導電墊陣列P的第二列位置以及第三行位置,且電源導電墊21C電性連接於第二晶片C2的第二電源接腳C23。電源導電墊21D對應於電源導電墊陣列P的第一列位置以及第四行位置,且電源導電墊21D電性連接於第二晶片C2的第三電源接腳C24。列電源開關22A連接於電源導電墊21A與電源導電墊21B之間,列電源開關22B連接於電源導電墊21B與電源導電墊21D之間,而行電源開關23A連接於電源導電墊21B與電源導電墊21C之間。假設用途上的需求,第一晶片C1的第一電源接腳C12需要電性連接於第二晶片C2的第二電源接腳C23,只需提供導通的列控制訊號至列電源開關22A,以及提供導通的行控制訊號至行電源開關23A時,可使列電源開關22A以
及行電源開關23A均處於導通狀態。如此一來,第一晶片C1的第一電源接腳C12電性連接於第二晶片C2的第二電源接腳C23。
圖8為圖6的陣列開關電路的另一運作示意圖。共同參閱圖1及圖8,假設用途上的需求,第一晶片C1的第一電源接腳C12電性連接於第二晶片C2的第三電源接腳C24,只需提供導通的列控制訊號至兩個列電源開關22A以及22B,便可使列電源開關22A以及22B均處於導通狀態。如此一來,第一晶片C1的第一電源接腳C12電性連接於第二晶片C2的第三電源接腳C24。
圖9為本發明的陣列開關電路的第四實施例的示意圖。陣列開關電路400包括第一基板31及第二基板41,第一基板31與第二基板41共平面且彼此相連接。第一基板31上設有多個第一訊號導電墊32、多個第一列訊號開關33、多個第一行訊號開關34、多個第一訊號擴展引腳35、以及多個第一訊號擴展開關36,其中該些第一訊號導電墊32互相間隔地設置於第一基板31且排列成第一訊號導電墊陣列SA,而每一第一訊號導電墊32於第一訊號導電墊陣列SA中具有一列位置及一行位置。第一訊號導電墊陣列SA的結構、連結關係與運作都類似於圖2中的訊號導電墊陣列S,在此不再贅述。
第一訊號導電墊陣列SA具有四個側邊SA1-SA4,而該些第一訊號擴展引腳35間隔地設置於第一基板31且靠近於該些側邊SA1~SA4。該些第一訊號擴展引腳35中對應同一列位置的兩者分別靠近該兩側邊SA1及SA2,而該些第一訊號擴展引腳35中對應同一行位置的兩者分別靠近該兩側邊SA3及SA4。
第一訊號擴展開關36間隔地設置於第一基板31且靠近該些側邊SA1~SA4。該些第一訊號擴展開關36中對應同一列位置的兩者分別靠近該兩側邊SA1及SA2,而該些第一訊號擴展開關36中對應同一行位置的兩者分
別靠近該兩側邊SA3及SA4。該些第一訊號擴展開關36使得該些第一訊號擴展引腳35分別與佈置在該些側邊SA1~SA4的該些第一訊號導電墊32可為相互連接。
第二基板41上設有多個第二訊號導電墊42、多個第二列訊號開關43、多個第二行訊號開關44、多個第二訊號擴展引腳45、以及多個第二訊號擴展開關46。該些第二訊號導電墊42互相間隔地設置於第二基板41且排列成第二訊號導電墊陣列SB,第二訊號導電墊陣列SB具有四個側邊SB1-SB4,而每一第二訊號導電墊42於第二訊號導電墊陣列SB中具有一列位置及一行位置。至於第二列訊號開關43、第二行訊號開關44、第二訊號擴展引腳45、以及第二訊號擴展開關46於第二基板41上的配置方式類似於第一列訊號開關33、第一行訊號開關34、第一訊號擴展引腳35、以及第一訊號擴展開關36於第一基板31上的配置方式。
為了使第一基板31與第二基板41相互電性連接,第一基板31上佈置在靠近第一訊號導電墊陣列SA的側邊SA2的該些第一訊號擴展引腳35分別與第二基板41上佈置在第二訊號導電墊陣列SB的側邊SB1的該些第二訊號擴展引腳45相互連接。
關於圖9的實施例,表示兩個訊號型陣列開關透過設置於邊緣的訊號擴展引腳,可在二維平面上進行東西向的擴展。然而圖9的兩個訊號型陣列開關之擴展僅為一個範例,根據使用上的需求,本發明的其他實施例亦可透過多於兩個的訊號型陣列開關在二維平面上進行東西向及/或南北向的擴展,或者可透過兩個以上的混合型陣列開關在二維平面上進行東西向及/或南北向的擴展。由此可知,本發明的陣列開關電路擁有極大的設計彈性。
圖10為本發明第五實施例的陣列開關的示意圖。第五實施例的陣列開關電路400A與第四實施例的陣列開關電路400大致相同,差異在於將靠近第一訊號導電墊陣列SA之該兩側邊SA2及SA4的第一訊號擴展開關36去除而改為短路線路,以及將靠近第二訊號導電墊陣列SB的該兩側邊SB2及SB4的第二訊號擴展開關46去除而改為短路線路。如此一來,當訊號從第一基板31上的第一訊號導電墊32傳送至第二基板41上的第二訊號導電墊42、或者從第二基板41上的第二訊號導電墊42傳送至第一基板31上的第一訊號導電墊32,不需連續通過第一訊號擴展開關36及第二訊號擴展開關46,只需通過第二訊號擴展開關46,藉此可提高訊號的傳輸速度。
圖11為本發明第六實施例的陣列開關電路的示意圖。第六實施例的陣列開關電路500與第四實施例的陣列開關電路400大致相同,差異在於第一基板31與第二基板41非共平面而是縱向擴展,且第一基板31上的該些第一訊號導電墊32分別透過多個導電穿孔V與第二基板41上的該些第二訊號導電墊42相互連接。
關於圖11的實施例,表示兩個訊號型陣列開關透過縱向延伸的導電穿孔V,可在三維平面上進行縱向的擴展。然而圖11的兩個訊號型陣列開關之擴展僅為一個範例,根據使用上的需求,本發明的其他實施例亦可透過多於兩個的訊號型陣列開關在三維空間中進行縱向的擴展,或者可透過兩個以上的混合型陣列開關在三維空間上進行縱向的擴展。
在其他實施例中,可透過多於兩個的訊號型陣列開關或混合型陣列開關同時於水平方向(如圖10)以及縱向方向(如圖11)進行擴展。
後續所記載開關元件的任一實施例,均可應用於陣列開關電路之列訊號開關、行訊號開關、列電源開關以及行電源開關。
圖12為本發明第一實施例的開關元件的示意圖。如圖12所示,開關元件600包括第一電晶體61、第一反相器62以及第二反相器63,其中第一反相器62與第二反相器63之組合可視為緩衝器。第一電晶體61為金屬氧化物半導體場效電晶體(MOS電晶體),其包含第一閘極端611、第一汲極端612、第一源極端613以及基體端614,第一閘極端611用於接收控制訊號,而第一電晶體61依據控制訊號之電壓位準決定第一汲極端612與第一源極端613之間處於導通狀態或截止狀態。共同參閱圖2與圖12,假設開關元件600作為圖2中的列訊號開關13,則第一汲極端612與第一源極端613分別連接同一列位置上的兩個訊號導電墊12。假設開關元件600作為圖2中的行訊號開關14,則第一汲極端612與第一源極端613分別連接同一行位置上的兩個訊號導電墊12。
第一反相器62包含第二電晶體621以及第三電晶體622,第二電晶體621為MOS電晶體且包含第二閘極端6211、第二汲極端6212以及第二源極端6213,而第三電晶體622為MOS電晶體且包含第三閘極端6221、第三汲極端6222以及第三源極端6223。第二閘極端6211連接於第三閘極端6221以及第一汲極端612,且第二閘極端6211以及第三閘極端6221作為第一反相器62的第一輸入端。第二汲極端6212連接於第三汲極端6222且第二汲極端6212以及第三汲極端6222作為第一反相器62的第一輸出端。第二源極端6213用於接地,而第三源極端6223用於連接電壓源Vdd。
第二反相器63包含第四電晶體631以及第五電晶體632,第四電晶體631為MOS電晶體且包含第四閘極端6311、第四汲極端6312以及第四源極端
6313。第五電晶體632為MOS電晶體且包含第五閘極端6321、第五汲極端6322以及第五源極端6323,第四閘極端6311連接於第五閘極端6321且第四閘極端6311與第五閘極端6321作為第二反相器63的第二輸入端。第二反相器63的第二輸入端連接於第一反相器62的第一輸出端,第四汲極端6312連接於第五汲極端6322且第四汲極端6312與第五汲極端6322作為第二反相器63的第二輸出端,而第二反相器63的第二輸出端連接於第一電晶體61的基體端614。第四源極端6313用於接地,而第五源極端6323用於連接電壓源Vdd。
當輸入訊號輸入至第一電晶體61的第一汲極端612以及第一反相器62的第一輸入端時,輸入訊號透過第一反相器62以及第二反相器63之組合可調整第一電晶體61的基體端614的電壓。根據MOS電晶體的基體效應的公式:,當MOS電晶體的基體端電壓可調整時,便可調整MOS電晶體的臨界電壓(V th )。根據MOS電晶體的電流公式:I d =,在V d 不變的條件下,當V th 因為基體端電壓的變化而降低時,可使I d 上升以及電阻(R)下降。根據時間常數公式:τ=RC,當R下降時,時間常數下降,電晶體的充放電速度就會加快,如此一來通道頻寬得以提升。
圖13為本發明第二實施例的開關元件的示意圖。如圖13所示,開關元件700包括第一電晶體71、第一反相器72以及第二反相器73,其中第一反相器72與第二反相器73之組合可視為緩衝器。第一電晶體71為MOS電晶體且包含第一閘極端711、第一汲極端712、第一源極端713以及基體端714,第一閘極端711
用於接收控制訊號,而第一電晶體71依據控制訊號之電壓位準決定第一汲極端712與第一源極端713之間處於導通狀態或截止狀態。
第一反相器72包含第二電晶體721以及第三電晶體722,第一反相器72類似圖12的第一反相器62,其差別在於第一反相器72的第二電晶體721和第三電晶體722皆為雙極性接面型電晶體(BJT電晶體)。第二反相器73包含第四電晶體731以及第五電晶體732,第二反相器73類似圖12的第二反相器63,其差別在於第二反相器73的第四電晶體731和第五電晶體732皆為雙極性接面型電晶體(BJT電晶體)。
當系統晶片封裝結構中的各晶片之間的連接或者封裝的I/O腳位之間的連接,因為用途上的需求要進行修改時,只需控制陣列開關電路中的列訊號開關及行訊號開關之導通狀態及截止狀態,便可達到重新設計各晶片之間的繞線或者封裝的I/O腳位之間的繞線,無須重新設計導線重佈層,達到減少產品開發時間以及降低研發成本的目標。此外,本發明的開關元件可應用於陣列開關電路中的列訊號開關以及行訊號開關,透過改變開關元件之電晶體的基體端電壓來降低電晶體的臨界電壓。當電晶體的臨界電壓降低且電晶體的汲極電壓不變時,流經電晶體的電流上升且電晶體的通道電阻下降。當通道電阻下降時,訊號的時間常數下降,開關元件之電晶體的充放電速度就會加快,如此一來通道頻寬得以提升。
雖然本發明以前述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。
100:陣列開關電路
11:基板
12:訊號導電墊
13:列訊號開關
14:行訊號開關
15:訊號擴展引腳
16:訊號擴展開關
S:訊號導電墊陣列
S11:第一側邊
S12:第二側邊
S13:第三側邊
S14:第四側邊
Claims (6)
- 一種陣列開關電路,包括:一基板;多個訊號導電墊,互相間隔地設置於該基板,該些訊號導電墊於該基板上排列成一訊號導電墊陣列,每一該些訊號導電墊於該訊號導電墊陣列中具有一列位置及一行位置,對應同一列位置的任二相鄰的訊號導電墊之間設有一列訊號開關,對應同一行位置的二相鄰的訊號導電墊之間設有一行訊號開關;以及多個訊號擴展引腳,分別透過多個訊號擴展開關與位在該訊號導電墊陣列的一側邊的該些訊號導電墊相連接。
- 如請求項1所述之陣列開關電路,更包括多個電源導電墊以及多個電源擴展引腳,該些電源導電墊互相間隔地設置於該基板且排列成一電源導電墊陣列,該電源導電墊陣列電性隔絕於該訊號導電墊陣列,每一電源導電墊於該電源導電墊陣列中具有一列位置及一行位置,對應同一列位置的任二相鄰的電源導電墊之間設有一列電源開關,對應相同行位置的二相鄰的電源導電墊之間設有一行電源開關,該些電源擴展引腳互相間隔地設置於該基板且分別透過多個電源擴展開關與位在該電源導電墊陣列的一側邊的該些電源導電墊相連接。
- 如請求項1所述之陣列開關電路,其中該訊號導電墊陣列包含兩個相對的側邊,該些訊號擴展引腳中分別靠近該兩側邊的兩者之間連接有一列訊號傳輸捷徑。
- 如請求項1所述之陣列開關電路,其中該基板為一第一基板,該些訊號導電墊為多個第一訊號導電墊,該些第一訊號導電墊於該第一基板排列成一第一訊號導電墊陣列,該些訊號擴展引腳為多個第一訊號擴展引腳,該些列訊號開關為多個第一列訊號開關,該些行訊號開關為多個第一行訊號開關,該陣列開關電路更包括一第二基板及多個第二訊號導電墊,該第二基板與該第一基板非共平面,該些第二訊號導電墊相互間隔地設置於該第二基板且排列成一第二訊號導電墊陣列,每一第二訊號導電墊於該第二訊號導電墊陣列中具有一列位置及一行位置,對應相同列位置的二相鄰的第二訊號導電墊之間設有一第二列訊號開關,對應相同行位置的二相鄰的第二訊號導電墊之間設有一第二行訊號開關,而該些第二訊號導電墊透過多個導電穿孔分別連接於該些第一訊號導電墊。
- 如請求項1所述之陣列開關電路,其中該基板為一第一基板,該些訊號導電墊為多個第一訊號導電墊,該些第一訊號導電墊於該第一基板排列成一第一訊號導電墊陣列,該些訊號擴展引腳為多個第一訊號擴展引腳,該些列訊號開關為多個第一列訊號開關,該些行訊號開關為多個第一行訊號開關,該些訊號擴展開關為多個第一訊號擴展開關,該陣列開關電路更包括一第二基板、多個第二訊號導電墊以及多個第二訊號擴展引腳,該第一基板與該第二基板共平面,該些第二訊號導電墊相互間隔地設置於該第二基板且排列成一第二訊號導電墊陣列,每一第二訊號導電墊於該第二訊號導電墊陣列中具有一列位置及一行位置,對應相同列位置的二相鄰的第二訊號導電墊之間設有一第二列訊號開關,對應相同行位置的二相鄰的第二訊號導電墊之間設有一第二行訊號開關,該些第二訊號擴展引腳分別電性連接於位在該第二訊號導電墊陣列的一側邊的 該些第二訊號導電墊,且該些第二訊號擴展引腳分別連接於該些第一訊號擴展引腳。
- 一種系統晶片封裝結構,包含:一導線重佈層;多個晶片,連接於該導線重佈層;一個如請求項1所述之陣列開關電路,該陣列開關電路的該些訊號導電墊透過該導線重佈層連接於該些晶片,且該導線重佈層位於該陣列開關電路之上方;以及一矽穿孔層,該矽穿孔層連接於該些訊號導電墊,且該矽穿孔層位於該陣列開關電路之下方。
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CN101976951A (zh) * | 2010-02-02 | 2011-02-16 | 成都芯源系统有限公司 | 多相功率开关模式电压调节器 |
CN109216292A (zh) * | 2017-06-29 | 2019-01-15 | 晟碟信息科技(上海)有限公司 | 包含降低针脚电容的控制开关的半导体装置 |
TW201937492A (zh) * | 2018-02-23 | 2019-09-16 | 日商半導體能源研究所股份有限公司 | 記憶體裝置及其工作方法 |
US10749528B2 (en) * | 2019-08-20 | 2020-08-18 | Intel Corporation | Stacked programmable integrated circuitry with smart memory |
TW202101468A (zh) * | 2019-03-29 | 2021-01-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
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CN101976951A (zh) * | 2010-02-02 | 2011-02-16 | 成都芯源系统有限公司 | 多相功率开关模式电压调节器 |
CN109216292A (zh) * | 2017-06-29 | 2019-01-15 | 晟碟信息科技(上海)有限公司 | 包含降低针脚电容的控制开关的半导体装置 |
TW201937492A (zh) * | 2018-02-23 | 2019-09-16 | 日商半導體能源研究所股份有限公司 | 記憶體裝置及其工作方法 |
TW202101468A (zh) * | 2019-03-29 | 2021-01-01 | 日商半導體能源研究所股份有限公司 | 半導體裝置 |
US10749528B2 (en) * | 2019-08-20 | 2020-08-18 | Intel Corporation | Stacked programmable integrated circuitry with smart memory |
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