TWI769533B - 半導體結構以及其形成方法 - Google Patents

半導體結構以及其形成方法 Download PDF

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TWI769533B
TWI769533B TW109133246A TW109133246A TWI769533B TW I769533 B TWI769533 B TW I769533B TW 109133246 A TW109133246 A TW 109133246A TW 109133246 A TW109133246 A TW 109133246A TW I769533 B TWI769533 B TW I769533B
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Taiwan
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layer
forming
redistribution
copper
redistribution layer
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TW109133246A
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TW202125654A (zh
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沈香谷
陳殿豪
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種半導體結構，包括第一鈍化層、含銅重分佈層、第二鈍化層、聚合物層、凸塊、以及焊料層。第一鈍化層設置在金屬線上方。含銅重分佈層設置在第一鈍化層上方，含銅重分佈層電性耦接金屬線，且含銅重分佈層接觸第一鈍化層的一部份形成銳角。第二鈍化層設置在含銅重分佈層上方，第二鈍化層以及含銅重分佈層之間之界面是彎曲的。聚合物層設置在第二鈍化層上方，聚合物層之一部份延伸以接觸含銅重分佈層。凸塊電性耦接含銅重分佈層。焊料層設置在凸塊上方。

Description

半導體結構以及其形成方法
本揭露係關於一種半導體結構以及形成半導體結構的方法。
半導體積體電路(integrated circuit，IC)工業經歷了快速的增長。積體電路材料及設計的技術改進已產生了數個世代的積體電路，每一世代的積體電路都具有比上一世代更小及更複雜的電路。然而，這些進步增加了處理和製造積體電路的複雜性，並且為了要實現這些進步，積體電路的處理和製造需要有類似的發展。在積體電路進化過程中，功能密度(單位晶片面積的互聯裝置數量)通常隨著幾何尺寸(使用製造製程可以創建的最小元件或線)下降而增加。
舉例來說，積體電路形成在半導體基板上，而半導體基板上可以被切割成單獨的裝置晶粒或積體電路晶片。每個積體電路晶片可以進一步附接到(例如藉由接合)到中介層(interposer)、再生晶圓(reconstituted wafer)、電路板、或另一個晶粒，以形成封裝體或裝置。為了滿足各種佈線需求，可以在積體電路晶片上形成導電金屬線的重分佈層(redistribution，RDL)，以將鍵合的連線從晶片的邊緣重新佈線到晶片的中心，或者通常將鍵合的連線分散到大於積體電路晶片面積的區域。目前已經實現在重分佈層周圍提供一或多層鈍化層，以保護半導體表面免於短路、應力、和化學污染物的影響。然而，一些鈍化層在隨後的製程中易於產生應力和破裂，並且可能導致與相鄰金屬接點的界面處的空隙或破裂。因此，雖然現有的製造重分佈層的方法通常已足以滿足其預期的目的，但它們並非在所有方面完全令人滿意。
本揭露一些實施例提供一種形成半導體結構的方法，包括提供內連線結構，設置在半導體基板上方，內連線結構包括金屬線；在金屬線上方形成第一介電層；圖案化第一介電層，以在第一開口中露出一部分的金屬線；在第一介電層上方形成圖案形成層，從而填充第一開口；在圖案形成層中形成第二開口；形成基腳特徵，以橫向延伸第二開口；在第二開口中形成重分佈層，使重分布層電性耦接金屬線，其中重分佈層包括彎曲頂表面；以及在重分布層上方形成第二介電層。
本揭露一些實施例提供一種半導體結構，包括內連線結構、第一介電層、重分佈層、第二介電層、保護層、以及導電特徵。內連線結構設置在半導體基板上方，內連線結構包括導電線。第一介電層設置在內連線結構上。重分佈層設置在第一介電層上方，重分佈層延伸通過第一介電層以接觸導電線，且重分佈層包括彎曲頂表面以及設置在第一介電層的頂表面上方的基腳特徵。第二介電層設置在重分佈層上方。保護層設置在第二介電層上方。導電特徵設置在重分佈層上方並電性耦接至重分佈層。
本揭露一些實施例提供一種半導體結構，包括第一鈍化層、含銅重分佈層、第二鈍化層、聚合物層、凸塊、以及焊料層。第一鈍化層設置在金屬線上方。含銅重分佈層設置在第一鈍化層上方，含銅重分佈層電性耦接金屬線，且含銅重分佈層接觸第一鈍化層的一部份形成銳角。第二鈍化層設置在含銅重分佈層上方，第二鈍化層以及含銅重分佈層之間之界面是彎曲的。聚合物層設置在第二鈍化層上方，聚合物層之一部份延伸以接觸含銅重分佈層。凸塊電性耦接含銅重分佈層。焊料層設置在凸塊上方。
以下公開許多不同的實施方法或是範例來實行所提供之標的之不同特徵，以下描述具體的元件及其排列的實施例以闡述本揭露。當然這些實施例僅用以例示，且不該以此限定本揭露的範圍。舉例來說，在本揭露中的在另一特徵部件之上形成、連接到及/或耦接到另一特徵部件可包括其中特徵部件形成為直接接觸的實施例，並且還可包括其中可形成插入上述特徵部件的附加特徵部件的實施例，使得上述特徵部件可能不直接接觸。另外，其中可能用到與空間相關用詞，例如「較低」，「較高」，「水平」，「垂直」，「在…上方」，「上方」，「在…下方」，「下方」，「上」，「下」，「下方」、「頂」、「底」及其衍伸詞（例如「水平地」、「向下地」、「向上地」等） 。這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係，這些空間相關用詞旨在涵蓋包括特徵的裝置的不同方向。
此外，當用「大約」、「近似」等描述數字或數字範圍時，此術語旨在涵蓋在包括所述數字的合理範圍內的數字，例如所述數量的正負10%，或本領域通常知識者所能理解的其他數值。舉例來說，術語「約5nm」涵蓋從4.5nm至5.5nm的尺寸範圍。此外，在不同實施例中可能使用重複的標號或標示，這些重複僅為了簡單清楚地敘述本揭露，不代表所討論的不同實施例及/或結構之間有特定的關係。
導電金屬線的導電(即含金屬的)重分佈層(redistribution layer，RDL)形成在許多積體電路晶片上，以將鍵合的連線從晶片的邊緣重新佈線到晶片的中心，或者通常將鍵合的連線分散到大於積體電路晶片面積的區域。可在重分佈層周圍提供一或多層鈍化層(可包括一或多種介電材料)，以保護半導體表面免於短路、應力、和化學污染物的影響。在一些情況下，一高分子保護層形成在一或多層鈍化層上方。由於對保護層進行固化時發生的體積收縮，以及高分子保護層、一或多層鈍化層、與重分佈層之間的熱膨脹係數(coefficient of thermal expansion，CTE)不匹配，應力可能會集中在與一或多層鈍化層接觸的重分佈層的角落處。這種集中的應力可能會傳播並通過一或多層鈍化層，從而導致一或多層鈍化層產生裂痕及/或從重分佈層分層(delamination)。至少由於這些原因，需要對用來形成重分佈層的方法進行改進。
現在將參考所附圖式更詳細地描述本揭露的各方面。第1圖是根據本揭露一些實施例繪示的用於製造半導體裝置的方法10的流程圖。方法10僅是示例，而非意圖將本揭露限制在方法10中明確揭示的內容。可以在方法10之前、之中、之後提供額外的步驟，並且對於此方法的其他實施例，可以更換、取消、或移動所描述的一些步驟。為了簡單起見，本文並未詳細描述所有的步驟。第2圖至第14B圖是根據本揭露一些實施例工件200在方法10的不同階段時的示意性局部剖面圖。隨後與第2圖至第14B圖一起描述方法10。
參照第1圖和第2圖，在方法10的方塊12處形成工件200，工件200包括基板200A、在基板200A上方的內連線結構200B、在內連線結構200B上方的蝕刻停止層(etch stop layer，ESL)210、和第一鈍化層212。在一些實施例中，基板200A可以由矽或其他半導體材料(例如鍺)製成。在一些其他實施例中，基板200A可以包括化合物半導體，如碳化矽、砷化鎵、砷化銦、或磷化銦。在一些實施例中，基板200A可包括合金半導體，如矽鍺、碳化矽鍺、磷化砷鎵、或磷化銦鎵。額外地或替代地，基板200A可以包括覆蓋在塊體半導體(未示出)上的磊晶層(未示出)。雖然未示出，但是各種微電子元件可以形成在基板200A之內或之上，例如包括源極/汲極特徵及/或閘極結構的電晶體元件、包括淺溝槽隔離(shallow trench isolation，STI)的隔離結構、被動元件、及/或任何其他合適的元件。
形成在基板200A上的內連線結構200B可為多層內連線(multi-layered interconnect，MLI)結構，並且可以包括埋設入多層金屬間介電層(multiple inter-metal dielectric layer，IMD layer)中的導孔208和導電線209，導孔208和導電線209在第2圖中一起繪示為金屬間介電層206以做為範例。在一些範例中，導孔208和導電線209中的每一者埋設在分開的金屬間介電層206中。在其他範例中，導孔208和導電線209可以一起形成在一金屬間介電層中。在同一水平的導電線可以統稱為金屬層，而不同的金屬層藉由一或多個導孔208互相連接。內連線結構200B配置成在已經或將要形成在工件200上的各種微電子部件之間提供內連線(例如佈線)。在內連線結構200B和基板200A之間可以設置中間層或元件，但是為了簡單起見並未示出這種層或元件。金屬間介電層206可以包括氧化矽或介電常數小於二氧化矽的介電常數(大約3.9)的低介電常數介電材料，在一些實施例中，低介電常數介電材料包括多孔有機矽酸鹽(organosilicate)薄膜，例如SiOCH、原矽酸四乙酯(tetraethylorthosilicate，TEOS)氧化物、未摻雜的矽酸鹽玻璃、摻雜的氧化矽，例如硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、熔融石英玻璃(fused silica glass，FSG)、磷矽玻璃(phosphosilicate glass，PSG)、摻雜氟的二氧化矽、摻雜碳的二氧化矽、多孔二氧化矽、多孔摻雜碳的二氧化矽、碳氮化矽(SiCN) 、碳氧化矽(SiOCN) 、氫倍半矽氧烷(hydrogen silsesquioxane，HSQ)、甲基倍半矽氧烷(methylsilsesquioxane，MSQ)、或其組合。金屬間介電層206可以進一步包括設置在導孔208和導電線209之間(即金屬間介電層206之間)的一或多層蝕刻停止層。
導孔208和導電線209形成在金屬間介電層206中。每個導孔208和導電線209可以藉由單鑲嵌(single damascene)製程分開形成及/或藉由雙鑲嵌(dual damascene)製程一起形成。在單鑲嵌製程中，首先在一層金屬間介電層206中形成用於形成導電線209(或用於形成導孔208的導孔開口)的溝槽，然後使用導電材料填充溝槽(或導孔開口)。然後執行如化學機械研磨或平坦化(chemical-mechanical polishing or planarization，CMP)製程的平坦化製程，以去除形成在金屬間介電層206頂表面上方的導電層的多餘部分，從而在溝槽(或導孔開口)中留下導電線209(或導孔208)。在一些實施例中，如果導孔208和設置在導孔208上的導電線209是使用單鑲嵌製程各自形成的，則可以沉積具有不同成分的導電層來形成前述特徵。在雙鑲嵌製程中，在金屬間介電層中一起形成溝槽和導孔開口，其中導孔開口設置在溝槽下方並連接到溝槽。然後在單道沉積製程中將導電層沉積在溝槽和導孔開口中，以在導孔208上方形成導電線209。導電層可以包括銅、鎢、鋁、鈷、釕、金、其他合適的金屬、其合金、或其組合。此外，可以藉由任何合適的方法來進行沉積，例如藉由化學氣相沉積(chemical vapor deposition，CVD)、鍍層(例如電鍍(electroplating)、無電鍍層(electroless plating)等)、其他合適的方法、或其組合。在一些實施例中，導電層包括銅，例如銅元素、白銅、銅鋁合金、其他含銅的合金、或其組合。在一些實施例中，雖然未繪示，但是導孔208及/或導電線209均包括設置在阻障層上方的導電層。阻障層可以包括鈦、氮化鈦、鉭、氮化鉭、鎢、鈷、氮化鈷、氮化鎢、釕、氮化釕、其他合適的金屬、其他合適的金屬氮化物、或其組合。對於導電層包括銅(或其合金)的實施例，導孔208及/或導電線209還可以包括在沉積在導電層上的含銅晶種層。
工件200更包括形成於內連線結構200B上方的蝕刻停止層210和第一鈍化層212。蝕刻停止層210可以包括碳氮化矽(SiCN)、碳氧化矽(SiOCN)、碳氧化矽(SiOC)、碳化矽(SiC)、氮化矽(SiN)、或其組合，並且蝕刻停止層210可以藉由合適的方法而形成在內連線結構200B上方，例如原子層沉積(atomic layer deposition，ALD)及/或化學氣相沉積。第一鈍化層212可為在蝕刻停止層210上方形成的單層或複合層，並且可藉由任何合適的方法來形成第一鈍化層212，例如玻璃上旋轉塗佈法(spin-on-glass，SOG)及/或其他合適的方法。第一鈍化層212可以由無孔(non-porous)材料形成。在本實施例中，第一鈍化層212是包括未摻雜的矽酸鹽玻璃(un-doped silicate glass，USG)的單層。以下描述係關於在蝕刻停止層210和第一鈍化層212上形成重分佈層，以與內連線結構200B最頂部的導電線209電性連接的方法。因此為了簡單起見，方法10的中間階段將會參照工件200如隨後的第3圖至第14B圖所示的這些部分來進行討論。
現在參考第1圖和第3圖，在方法10的方塊12處，對第一鈍化層212和蝕刻停止層210進行圖案化，以形成露出導電線209一部分的開口214。可以藉由一系列的圖案化和蝕刻製程來形成開口214，包括例如在第一鈍化層212上方形成遮罩元件(未示出)、藉由光罩來曝光包括光阻層的遮罩元件、在合適的溶劑(即顯影劑)中顯影曝光的遮罩元件，以形成包括開口的圖案化遮罩元件、蝕穿在開口中露出的第一鈍化層212和蝕刻停止層210、以及藉由合適的方法(例如阻劑剝離 (resist stripping)、濕蝕刻、及/或電漿灰化)從工件200上去除圖案化遮罩元件。
參照第4圖，在方法10的方塊12處，隨後在被圖案化的第一鈍化層212上方形成晶種層216，使得晶種層216襯於開口214的底部和側壁表面。晶種層216可以包括銅、鉭、鈦、氮化鈦、氮化鉭、其他合適的材料、或其組合。晶種層216可為單一的金屬層，也可為複合的層。在本實施例中，晶種層216包括銅，使得晶種層216配置成有助於隨後在晶種層216上形成含銅的重分佈層。可以藉由任何合適的方法來沉積晶種層216，例如化學氣相沉積、原子層沉積、物理氣相沉積(physical vapor deposition，PVD)、或其他合適的方法。雖然未繪示，但是可以在晶種層216與被圖案化的第一鈍化層212之間形成阻障層。這種阻障層的成分和形成方法與上述導孔208和導電線209的成分和形成方法相似。在本實施例中，晶種層216配置成提供基板，以在此基板上使用如電鍍之類的鍍覆方法形成重分佈層，其製程將在下面詳細討論。
現在參考第1圖和第5A圖至第5C圖，在方法10的方塊14處，在晶種層216上方形成遮罩元件220，從而填充開口214。遮罩元件220可以為多層的(如第5A圖和第5B圖所示)或單層的(如第5C圖所示)。雖然這兩種結構均同樣適用於本實施例，但是它們提供了不同的用於形成重分佈層的路徑，這將在隨後詳細討論。
參考第5A圖，在方法10的方塊14處，首先在晶種層216上方形成底層220A，從而填充開口214。在本實施例中，底層220A包括含有碳、氫、氧、氮、及/或矽的聚合物材料。在本實施例中，底層220A包括矽。雖然並未限制對底層220A的具體成分，但是本文提供的底層220A可藉由微影製程來圖案化(隨後將隨著光阻層2來詳細討論)，並且能夠提供對隨後形成在底層220A上的光阻層220B的成分的蝕刻選擇性。即，底層220A的成分與隨後討論的光阻層220B的成分充分地不同，以確保底層220A和光阻層220B中的其中一層與另一層相比具有較快的蝕刻速率。可以藉由任何合適的方法(例如旋轉塗佈)在晶種層216上形成底層220A。
參照第5B圖，在方法10的方塊14處，在底層220A上方形成光阻層220B。在本實施例中，光阻層220B包括至少包含碳、氫、氧、及/或氮的聚合物材料，並且藉由如旋轉塗佈的任何合適的方法所形成。如上所述，為了確保底層220A和光阻層220B之間的蝕刻選擇性，底層220A的成分會與光阻層220B的成分不同。舉例來說，底層220A可以包括含有矽的聚合物(例如矽的重量至少占30%)，而光阻層220B包括實質上不含矽的聚合物(例如矽的重量小於約1%)。在一些實施例中，光阻層220B更包括光酸起始劑(photo-acid generators，PAG)、熱酸起始劑(thermal-acid generators，TAG)、光鹼起始劑(photo-base generators，PBG)、及/或配置成對給定的輻射源來說能增強光阻層220B的光敏性(photosensitivity)的其他分子。在本實施例中，底層220A和光阻層220B(統稱為遮罩元件220)配置成可藉由相同的微影製程來圖案化。舉例來說，微影製程可以包括使用光罩，藉由輻射源(例如極紫外光(extreme ultraviolet，EUV)輻射)來曝光遮罩元件220，並且使曝光的遮罩元件220顯影，以在遮罩元件220中形成想要的圖案。
現在參考第5C圖，在方法10的方塊14處，在晶種層216上方僅形成光阻層220B，從而填充開口214。先前已參考第5B圖詳述了光阻層220B的成分。此外，在不具有底層220A的情況下，只要光阻層220B可被輻射源圖案化，光阻層220B的成分並不受限制(如第5C圖的實施例所示)。
參考第1圖和第6A圖至第6D圖，在方法10的方塊16處，在遮罩元件220中形成開口，並且在開口的底部形成底切特徵。第6A圖和第6B圖所示的實施例一起對應於第5A圖和第5B圖所示的實施例，其中遮罩元件220包括形成在底層220A上方的光阻層220B。第6C圖和第6D圖所示的實施例一起對應於第5C圖所示的實施例，其中遮罩元件220僅包括光阻層220B。
參照第6A圖，在方法10的方塊16處，對遮罩元件220實施圖案化製程310，從而形成開口222並重新露出開口214。在本實施例中，圖案化製程310去除了一部份的遮罩元件220(即底層220A和光阻層220B)，而並未去除或並未實質上去除晶種層216或第一鈍化層212。在本實施例中，實施圖案化製程310包括藉由光罩將遮罩元件220曝光於於輻射源(例如極紫外光)，並在合適的溶劑(即顯影劑)中顯影曝光遮罩元件220，以形成圖案化的遮罩元件220。取決於遮罩元件220和溶劑之間的化學反應，可以去除遮罩元件220的曝光部分(若使用正光阻)或未曝光部分(若使用負光阻)，以形成圖案化的遮罩元件220。在執行曝光製程之後，圖案化製程310可以可選地包括一或多道烘烤製程。
繼續第6B圖，在方法10的方塊16處，對圖案化的遮罩元件220實施蝕刻製程320，從而在底層220A的底部形成底切特徵224A。在本實施例中，由於上述底層220A和光阻層220B之間的成分差異，蝕刻製程320去除一部份底層220A的速率比去除光阻層220B和晶種層216的速率更高。在一些實施例中，蝕刻製程320不去除或實質上不去除光阻層220B和晶種層216的任何部分。蝕刻製程320可為任何合適的蝕刻製程，例如乾蝕刻製程、濕蝕刻製程、反應離子蝕刻(reactive ion etching，RIE)、或其組合。在本實施例中，蝕刻製程320是使用含氟蝕刻劑的乾蝕刻製程，例如CF4 、CH3 F、CHF3 、其他合適的含氟蝕刻劑、或其組合。
在本實施例中，係由蝕刻製程320的持續時間來控制所得的底切特徵224A的橫向尺寸L2，可以根據光阻層220B的蝕刻速率來決定此持續時間。在一些範例中，開口222的橫向尺寸L2與寬度L1之比可以為約1:30至約1:24。一方面來說，較大的橫向尺寸L2可能造成較小的角度θ1及/或角度θ2(如第6B圖所示)，從而導致在後續鍍層製程中可能難以填充底切特徵224A。另一方面來說，較小的橫向尺寸L2可能會造成較大的角度θ1和角度θ2，從而限制了被填充的底切特徵224A(即隨後在第9圖中討論的基腳特徵230B)緩解應力集中在隨後形成的鈍化層(即隨後在第9圖中討論的第二鈍化層240)角落處的能力。
現在參考第6C圖和第6D圖，在方法10的方塊16處，以圖案化製程330和隨後的散焦(de-focusing)製程340交替形成開口222和底切特徵224B。參照第6C圖，圖案化製程330可為微影製程，配置成經由一系列曝光和顯影製程去除一部分的光阻層220B，從而形成開口222並重新露出開口214。在一些實施例中，圖案化製程330實質上類似於上述的圖案化製程310。值得注意的是，本文討論的圖案化製程310和蝕刻製程320係藉由不同的工具所實現。反之，散焦製程340與圖案化製程330係藉由相同的微影工具所實現，但散焦製程340與圖案化製程330具有不同的操作條件。
現在參考第6D圖，方法10實施散焦製程340，以在遮罩元件220(即光阻層220B)中形成底切特徵224B。對於圖案化製程330來說，一光束(即輻射源)通過光罩聚焦在遮罩元件220上，以形成具有期望尺寸的開口222。聚焦的光束確保所提供的能量足以引發被曝光的遮罩元件220中的光化學變化(即由光源引起的光阻層220B的化學變化)。然而，散焦製程340包括故意擴散或散佈光束的焦點，使得超出被光罩曝光的光阻層220B的一部份光阻層220B可以被光束曝光。因此，使光束散焦會導致光阻層220B的底部角落被過度曝光，並且在顯影之後會形成底切特徵224B。換句話說，與被蝕刻的底切特徵224A不同，底切特徵224B直接在遮罩元件220中被圖案化。因此，可以藉由調節光束的焦點的擴散程度來控制底切特徵224B的橫向尺寸L3，更大程度造成更大的橫向尺寸L3。在本實施例中，橫向尺寸L3的大小可以類似於前述橫向尺寸L2的大小。
不論方塊16是由圖案化製程310和蝕刻製程320實施，還是由圖案化製程330和散焦製程340實施，本文所提供的底切特徵224A或底切特徵224B配置成在橫向(即在所示的實施例中沿X軸)超出開口222的垂直側壁。雖然底切特徵224A或底切特徵224B的角落在本實施例中係繪示為尖角，但是本實施例不要求底切特徵224A或底切特徵224B的角落具有特定形狀，只要底切特徵224A或底切特徵224B的角落橫向延伸超過開口222的側壁即可。在一些實施例中，這種角落可能會變鈍。此外，角度θ1和角度θ2的大小不需相等。可以由上述的角度θ1和角度θ2來定義底切特徵224A或底切特徵224B，其中角度θ1和角度θ2是銳角(即小於90度)。在本實施例中，角度θ1和角度θ2分別為約30度至約70度。值得注意的是，若角度θ1和角度θ2小於約30度，則通常難以確保在隨後的鍍層製程中適當地填充(例如未完全填充)底切特徵224A或底切特徵224B，從而在隨後形成的重分佈層中造成缺陷。然而，如果角度θ1和角度θ2大於約70度，則被填充的底切特徵224A或底切特徵224B(即基腳特徵230B)減輕重分佈層的角落處的應力集中的能力可能會變弱。
現在參考第1圖和第7A圖至第8圖，在方法10的方塊18處，填充圖案化的遮罩元件220的開口(即開口214、開口222、和底切特徵224A或底切特徵224B)，以在第一鈍化層212上方形成重分佈層230。重分佈層230配置成電性連接導電線209與隨後形成的凸塊(例如第13圖至第14B圖所示的凸塊250)。雖然第7A圖和第7B圖分別繪示了從第6B圖和第6D圖開始的本揭露的不同實施例，但是形成重分佈層230的製程實質上相同，因此將以與第7A圖和第7B圖類似的術語來進行討論。
在本實施例中，重分佈層230包括元素銅，並且不含含銅合金。如本揭露所提供的，係藉由如電鍍及/或無電鍍層的鍍層製程來沉積重分佈層230，以填充圖案化的遮罩元件220中的開口。特別來說，可以使用從下而上(bottom-up)的方式來實施鍍層製程。在此方式中，重分佈層230首先在晶種層216上生長，然後重分佈層230在其自身上生長，而非在圖案化的遮罩元件220的表面上生長。因此，當可不加限制地進行鍍層製程時，重分佈層230將繼續生長，且重分佈層230的最頂部升高到圖案化的遮罩元件220的頂表面上方，隨後將詳細討論此製程。換句話說，重分佈層230的最大高度超過開口222的深度。在一些範例中，可在形成重分佈層230之前沉積潤濕劑(wetting agents)以促進自下而上的鍍層製程。雖然未示出，但是在形成重分佈層230之前，可以在由圖案化的遮罩元件220露出的晶種層216的部分上形成阻障層。阻障層可以包括鈦、氮化鈦、鉭、氮化鉭、鎢、鈷、氮化鈷、氮化鎢、釕、氮化釕、其他金屬、其他金屬氮化物、或其組合。
此後，參考第8圖，藉由任何合適的方法(例如阻劑剝離、濕蝕刻、及/或電漿灰化)從工件200中去除圖案化的遮罩元件220。隨後，從工件200選擇性地去除未設置在重分佈層230下方的一部份晶種層216，而不去除或實質上去除一部份的重分佈層230或第一鈍化層212。在一範例中，所述蝕刻製程可為利用如SF6 的含氟蝕刻劑的乾蝕刻製程。另外地或替代地，方法10可以利用強鹼性溶液的濕蝕刻製程，以去除任何前述製程步驟殘留的材料。
如本文所述，重分佈層230係由在第一鈍化層中形成以接觸導電線209的底部230A、形成在底切特徵224中的基腳特徵230B、以及設置在晶種層216上方和重分佈層230的垂直側壁之間的頂部230C所形成。在本實施例中，係使用分別以蝕刻製程320或散焦製程340形成的底切特徵224A或底切特徵224B的形狀造成的銳角θ1和銳角θ2來定義基腳特徵230B。在本實施例中，頂部230C具有向上彎曲並遠離工件200的下方的元件的頂表面(也是重分佈層230的頂表面)。換句話說，重分佈層230的頂表面和側壁相交於一圓角。如第8圖所示，彎曲的頂表面可以由頂部230C的高度h與寬度w之比值所定義。在本實施例中，此比值的範圍為約0.2至約0.3。一方面來說，如果此比值小於約0.2，則所得的頂部230C可能會太平，即用來定義重分佈層230的內角的角度θ4(在頂部230C的放大圖中示出)可能接近或變成90度。另一方面來說，如果此比值大於約0.3，則所得的頂部230C可能不會有足夠的接觸面積來與隨後形成的凸塊(例如第13圖至第14B圖所示的凸塊250)接合。
另外，彎曲的頂表面的特徵可以在於與彎曲表面相切的斜率發生的連續變化。舉例來說，如頂部230C的放大圖所示，S1至S5代表沿彎曲頂表面在不同點處的切線方向繪製的直線的斜率。可以理解的是，斜率S1至S5的大小係逐漸地和連續地發生變化。舉例來說，在所繪示的實施例中，斜率從S1逐漸減小到S5。反之，請參見第8圖中虛線所示的配置231(也在放大圖中顯示)，如果頂部230C具有實質上平坦的頂表面，則定義配置231內角的角度θ3實質上是正交的(即大約90度)。這造成斜率從S6(由於實質上垂直的表面而未定義)到S7(由於實質上水平的表面而為零)處突然發生改變而非漸漸改變。
通常來說，可以在鍍層製程即將結束時引入平坦劑(flattening agent，包含例如苯基聚合物)，以確保所得的重分佈層230的頂表面實質上與被圖案化的遮罩元件220的頂表面等高或共平面，使得配置231具有上述銳角(例如角度θ3)，如第8圖所示。換句話說，平坦劑配置成抑制重分佈層230過度生長而超出圖案化的遮罩元件220的頂表面。在這些情況下，平坦劑藉由選擇性地吸附到銅原子上(藉由靜電吸引)而非吸附到圖案化的遮罩元件220上，以抑制銅層生長。因此，在重分佈層230上形成鈍化層(例如下述第二鈍化層240)之後，鈍化層所經歷的任何應力都可能會集中在這些正交角上，並導致結構上的缺陷，包括裂痕、分層、及/或第二鈍化層中的其他缺陷。在某些情況下，這種應力可能是由第二鈍化層和隨後形成在第二鈍化層上的保護層(例如第11圖至第14B圖所示的保護層246)之間的熱膨脹不均勻所引起的。為了解決這些挑戰，本揭露提供了一種形成無尖角或實質上無尖角(即由實質上正交的角例如θ3定義的角)的重分佈層的方法，此方法係藉由形成由銳角(例如θ1、θ2定義的角)定義的基腳特徵230B，並且藉由不受平坦劑所影響的由下而上的鍍層製程以形成彎曲的頂表面。換句話說，本實施例的鍍層製程不施加平坦劑，從而使得銅層不受抑制地生長超出圖案化的遮罩元件220的頂表面。
現在參考第1圖和第9圖，在方法10的方塊20處，在重分佈層230上方形成第二鈍化層240。第二鈍化層240可以包括氮化矽、氧化矽、其他合適的介電材料、或其組合。在一些實施例中，第二鈍化層240包括緻密(dense)的介電材料，配置成提供保護以防止污染物(例如水氣及/或氧氣)進入重分佈層230及/或工件200的其他元件。在一些實施例中，第二鈍化層240的成分不同於第一鈍化層212的成分。舉例來說，第一鈍化層212可以包括未摻雜的矽酸鹽玻璃，第二鈍化層240可以包括氮化矽。第二鈍化層240可以具有單層結構或可具有多層結構。第二鈍化層240可以藉由化學氣相沉積、高密度電漿化學氣相沉積(high-density plasma CVD，HDPCVD) 、電漿增強化學氣相沉積(plasma-enhanced CVD，PECVD) 、次大氣壓化學氣相沉積(sub-atmospheric CVD，SACVD) 、其他合適的方法、或其組合來形成。在本實施例中，重分佈層230在其與第二鈍化層240的界面處不具有銳角，從而減輕了由任何潛在的熱膨脹不匹配引起的重分佈層230與第二鈍化層240之間的應力集中。
現在參考第1圖和第10圖，在方法10的方塊22處，在第二鈍化層240中形成開口242，以露出一部分重分佈層230。可以藉由與上述形成開口214(第3圖)類似的一系列圖案化和蝕刻製程來形成開口242。舉例來說，可以在重分佈層230上方形成具有開口的圖案化遮罩元件(未示出)，並且隨後藉由蝕刻製程去除在開口中露出的第二鈍化層240的一部分。在一些實施例中，蝕刻製程是用如SF6 的蝕刻劑實施的乾蝕刻製程。另外地或替代地，可以執行使用強鹼性溶液的濕式清潔製程以形成開口242。在一些範例中，如此處所示，在方塊22處的蝕刻製程可去除重分佈層230的一部分，使得開口242延伸到重分佈層230的頂表面下方。
參考第1圖和第11圖，在方法10的方塊24處，在圖案化的第二鈍化層240上形成保護層246，從而填充開口242。保護層246可包括聚醯亞胺(polyimide)、聚苯並噁唑(polybenzoxazole，PBO)、苯並環丁烯(benzocyclobutene，BCB)、其他合適的聚合物材料、或其組合。在本實施例中，保護層246包括聚醯亞胺，聚醯亞胺是光阻材料，當曝光於輻射源時可進行光化學變化。在一些實施例中，保護層246包括光敏性增強劑(photo-sensitivity enhancer)，例如光酸起始劑、熱酸起始劑、光鹼起始劑、其他合適的增強劑、或其組合。在一些實施例中，保護層246係藉由如旋轉塗佈的適當製程所形成。對於開口242延伸到重分佈層230的頂表面之下的實施例，保護層246的一部分可因此延伸到重分佈層230的頂表面之下。
現在參考第1圖和第12圖，在方法10的方塊26處，圖案化保護層246以形成開口248。對於保護層246包括如聚醯亞胺的光阻材料的實施例來說，可以直接對保護層246進行圖案化以形成開口248。換句話說，可以藉由將保護層246通過光罩曝光於輻射源，隨後顯影露出的保護層246，以形成開口248。在本實施例中，調整開口248的寬度，使得開口248的側壁僅由保護層246而非第二鈍化層240的部分定義，即，保護層246襯在開口248的側壁。這是為了確保圖案化製程時僅去除對光敏感的保護層246，而不去除包括介電材料的第二鈍化層240的部分。換句話說，將保護層246的一部分留在開口248中確保了所得的側壁具有實質上平滑的輪廓。對於開口242延伸到重分佈層230的頂表面下方的實施例(如第10圖所示)，保護層246的底部的側壁接觸第二鈍化層240和重分佈層230。
在圖案化之後，可以藉由將保護層246烘烤或曝光於輻射源(例如紫外光)來固化保護層246。在一些實施例中，固化保護層246的操作使得保護層246的聚合物鏈發生交聯(cross-link)，從而形成網路，以保護下方的重分佈層230免於後續製程步驟(例如凸塊形成製程)產生的機械應力。然而，固化也可能導致保護層246由於溶劑蒸發或還原反應而收縮，從而在第二鈍化層240上施加收縮的應力。如果第二鈍化層240在與重分佈層230的界面處包括尖角，則固化的保護層246產生的收縮應力可能會集中在這些尖角上，從而導致工件200中如裂痕、分層、及/或其他的結構缺陷。本實施例藉由彎曲的頂表面和基腳特徵230B代替尖角來補救這些結構缺陷，從而改善工件200的結構完整性。
現在參考第1圖和第13圖，在方法10的開口28處，在開口248中形成凸塊250。在本實施例中，凸塊250被配置為與露出於開口248的重分佈層230的部分接合(即電性耦接)。在本實施例中，凸塊250包括塊體導電層，包括銅、鎳、鈷、鋁、金、銀、鈀、錫、鉍、其合金、或其組合。凸塊250可包括晶種層(未示出)，晶種層設置在開口248中的塊體導電層下方，並且配置成促進塊體導電層的形成。取決於塊體導電層的成分，晶種層可包括銅、鉭、鈦、氮化鈦、氮化鉭、其他合適的材料、或其組合。在一些示例性實施例中，凸塊250包括設置在含銅晶種層上方的含銅塊體導電層。對於開口242延伸到重分佈層230的頂表面下方的實施例，凸塊250的一部分也延伸到重分佈層230的頂表面下方。
可以藉由一系列圖案化和沉積製程形成凸塊250。舉例來說，形成凸塊250的操作可以包括形成遮罩元件(未示出)，遮罩元件包括保護層246以及保護層246上方的光阻層，藉由光罩將遮罩元件曝光於輻射源，顯影曝光的遮罩元件以形成圖案化的遮罩元件並至少重新露出開口248，然後可選地在開口248中沉積晶種層，並在晶種層上方形成塊體導電層。因此，在工件200未被圖案化遮罩元件覆蓋的部分中形成凸塊250。在一些實施例中，圖案化的遮罩元件留在保護層246上方，直到隨後在凸塊250上方形成焊料層(例如焊料層252)為止，隨後將進行討論。塊體導電層可以藉由鍍層製程(例如電鍍及/或無電鍍層)形成。在一些實施例中，形成凸塊250的鍍層製程使用前述平坦劑，使得凸塊250的頂表面實質上是齊平的。
此後，可以在凸塊250上方沉積焊料層252。焊料層252可為含鉛或無鉛的焊料層。在一些範例中，焊料層252可包含鉛和錫以形成基於鉛的成分。在另一些範例中，對於無鉛焊料層252，焊料層252可以包含銦和銻的合金，或包含錫、銀、和銅的合金(可稱為SAC)。在其他示例中，可以使用具有各種成分的SAC合金，例如SAC105(錫98.5%，銀1.0%，銅0.5%)、SAC305及/或SAC405。在一些實施例中，焊料層252包括具有共同熔點的共晶(eutectic)材料，配置成在電應用中形成導電的焊料連接。無鉛的焊料層252可以由錫和銅(及其合金或化合物)形成，而無需使用銀。或者，無鉛的焊料層252可以包括錫和銀(及其合金或化合物)，而無需使用銅。在形成焊料層252之後，藉由阻劑剝離、濕蝕刻及/或電漿灰化來去除圖案化的遮罩元件，從而得到第13圖所示的實施例。
此後，參考第14A圖和第14B圖，在方法10的方框30處，可以對工件200進行退火，以允許焊料層252在凸塊250上方回流並形成回流的焊料層252'。回流的焊料層252'可以用作與外部電路的連接點，所述外部電路例如是其他基板、印刷電路板(printed circuit board，PCB)、中介層、重構晶圓、積體電路晶粒、其他重分佈層、其他內連接結構、或其他半導體裝置。由於保護層246和第二鈍化層240之間的熱膨脹係數不匹配，在方塊30處的退火製程可能會產生額外的應力。值得注意的是，本文提供的彎曲的頂表面及/或重分佈層230的基腳特徵230B減輕了這種由熱造成的應力，從而防止結構上的缺陷損壞第二鈍化層240。
在一些實施例中，凸塊250可以直接形成在重分佈層230的底部230A的上方(未示出)，如第14A圖所示與底部230A沿著X軸稍微重疊，或者如第14B圖所示沿著X軸偏離底部230A。只要導電線209和凸塊250藉由重分佈層230電性連接，並且在凸塊250和頂部230C之間有足夠的接觸表面，則凸塊250相對於重分佈層230的組態於本實施例並不限制。此外，參照第14B圖，取決於蝕刻製程320或散焦製程340的程度，角度θ1和角度θ2可為任何銳角並且可以不同。更進一步，如第14A圖和第14B圖所示，從重分佈層230的垂直側壁到基腳特徵230B的過渡區域可為有角度的(如重分佈層230的實心輪廓所示)或彎曲的(如用虛線輪廓繪示)，或者可為階梯狀(未繪示)。如上所述，不管過渡區域的形狀如何，角度θ1和角度θ2都是銳角。
雖然並非用以限制，但是本揭露的一或多個實施例為半導體裝置及其形成方法提供了許多好處。舉例來說，本揭露的實施例提供了一種含銅的重分佈層，其包括基腳特徵和在與鈍化層的界面處的彎曲的頂表面。在一些實施例中，藉由過度蝕刻或藉由微影圖案化來形成基腳特徵，以橫向延伸一開口，並且隨後在此開口中會形成重分佈層。在一些實施例中，當在開口中形成重分佈層時，藉由從下而上的方式來形成重分佈層以形成彎曲的頂表面，使得重分佈層生長超過開口的深度。在本實施例中，所得到的重分佈層在與一或多層鈍化層的界面處實質上不具有銳角(即非正交角)，從而減輕了由例如鈍化層與形成在鈍化層上的聚合物保護層的熱膨脹不匹配所引起的應力在這種界面造成的結構缺陷。
本揭露一些實施例提供一種形成半導體結構的方法，包括提供內連線結構，設置在半導體基板上方，內連線結構包括金屬線；在金屬線上方形成第一介電層；圖案化第一介電層，以在第一開口中露出一部分的金屬線；在第一介電層上方形成圖案形成層，從而填充第一開口；在圖案形成層中形成第二開口；形成基腳特徵，以橫向延伸第二開口；在第二開口中形成重分佈層，使重分布層電性耦接金屬線，其中重分佈層包括彎曲頂表面；以及在重分布層上方形成第二介電層。
在一些實施例中，形成半導體結構的方法更包括在形成圖案形成層之前，在第一介電層上形成晶種層；以及在形成第二介電層之前去除晶種層未被重分佈層覆蓋的部份。在一些實施例中，形成圖案形成層的操作包括在第一介電層上形成光阻層。在一些實施例中，形成第二開口的操作包括對光阻層進行第一微影製程，且其中形成基腳特徵的操作包括在進行第一微影製程之後對光阻層進行第二微影製程。在一些實施例中，形成圖案形成層的操作包括在第一介電層上形成底層以及隨後在底層上形成光阻層。在一些實施例中，底層包括矽，且光阻層實質上不包括矽。在一些實施例中，形成第二開口的操作包括對光阻層進行微影製程，且形成基腳特徵的操作包括在進行微影製程之後，相對於光阻層選擇性地蝕刻底層。在一些實施例中，形成重分佈層的操作包括進行從下而上的鍍層製程。在一些實施例中，形成半導體結構的方法更包括在第二介電層中形成第三開口，以露出重分佈層之頂部；在第二介電層上方形成保護層，使得保護層在第三開口中延伸接觸重分佈層之頂部；在保護層中形成第四開口，以露出重分佈層之頂部；在第四開口中形成凸塊；以及在凸塊上方形成焊料特徵。
本揭露一些實施例提供一種半導體結構，包括內連線結構、第一介電層、重分佈層、第二介電層、保護層、以及導電特徵。內連線結構設置在半導體基板上方，內連線結構包括導電線。第一介電層設置在內連線結構上。重分佈層設置在第一介電層上方，重分佈層延伸通過第一介電層以接觸導電線，且重分佈層包括彎曲頂表面以及設置在第一介電層的頂表面上方的基腳特徵。第二介電層設置在重分佈層上方。保護層設置在第二介電層上方。導電特徵設置在重分佈層上方並電性耦接至重分佈層。
在一些實施例中，重分佈層包括銅。在一些實施例中，由基腳特徵之傾斜表面以及基腳特徵之底表面所定義的角度小於約90度。在一些實施例中，導電特徵的側壁係由保護層所定義。在一些實施例中，半導體結構更包括含銅晶種層，設置在重分佈層以及第一介電層之間。在一些實施例中，半導體結構更包括焊料層，設置在導電特徵上方。在一些實施例中，彎曲頂表面在圓角處與重分佈層之側壁相交。
本揭露一些實施例提供一種半導體結構，包括第一鈍化層、含銅重分佈層、第二鈍化層、聚合物層、凸塊、以及焊料層。第一鈍化層設置在金屬線上方。含銅重分佈層設置在第一鈍化層上方，含銅重分佈層電性耦接金屬線，且含銅重分佈層接觸第一鈍化層的一部份形成銳角。第二鈍化層設置在含銅重分佈層上方，第二鈍化層以及含銅重分佈層之間之界面是彎曲的。聚合物層設置在第二鈍化層上方，聚合物層之一部份延伸以接觸含銅重分佈層。凸塊電性耦接含銅重分佈層。焊料層設置在凸塊上方。
在一些實施例中，半導體結構更包括含銅晶種層，位在含銅重分佈層以及第一鈍化層之間，且位在含銅重分佈層以及金屬線之間。在一些實施例中，凸塊的側壁延伸至含銅重分佈層的頂表面的下方。在一些實施例中，含銅重分佈層實質上不具有含銅合金。
上述內容概述許多實施例的特徵，因此任何所屬技術領域中具有通常知識者，可更加理解本揭露之各面向。任何所屬技術領域中具有通常知識者，可能無困難地以本揭露為基礎，設計或修改其他製程及結構，以達到與本揭露實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解，在不脫離本揭露之精神和範圍內做不同改變、代替及修改，如此等效的創造並沒有超出本揭露的精神及範圍。
10:方法 12,14,16,18,20,22,24,26,28,30:操作 200:工件 200A:基板 200B:內連線結構 206:金屬間介電層 208:導孔 209:導電線 210:蝕刻停止層 212:第一鈍化層 214,222,242,248:開口 216:晶種層 220:遮罩元件 220A:底層 220B:光阻層 224A,224B:底切特徵 230:重分佈層 230A:底部 230B:基腳特徵 230C:頂部 231:配置 240:第二鈍化層 246:保護層 250:凸塊 252,252’:焊料層 310,330:圖案化製程 320:蝕刻製程 340:散焦製程 h:高度 L1:寬度 L2,L3:橫向尺寸 S1,S2,S3,S4,S5,S6,S7:斜率 w:寬度 θ1,θ2,θ3,θ4:角度
以下將配合所附圖式詳述本揭露之實施例。應注意的是，依據在業界的標準做法，多種特徵並未按照比例繪示且僅用以說明例示。事實上，可能任意地放大或縮小元件的尺寸，以清楚地表現出本揭露的特徵。還應強調的是，所附圖式僅示出本揭露的典型實施例，而非旨於限制本揭露的範圍，從而本揭露亦可應用於其他的實施例。 第1圖是根據本揭露一些實施例的用於製造半導體裝置的方法的流程圖。 根據本揭露一些實施例，第2、3、4、5A、5B、5C、6A、6B、6C、6D、7A、7B、8、9、10、11、12、13、14A、14B圖是一工件在第1圖中繪示的方法的實施例的各個階段的剖面圖。
10:方法
12,14,16,18,20,22,24,26,28,30:操作

Claims (13)

  1. 一種形成半導體結構的方法，包括：提供一內連線結構，設置在一半導體基板上方，其中該內連線結構包括一金屬線；在該金屬線上方形成一第一介電層；圖案化該第一介電層，以在一第一開口中露出一部分的該金屬線；在該第一介電層上方形成一圖案形成層，從而填充該第一開口；在該圖案形成層中形成一第二開口；形成一底切特徵，以橫向延伸該第二開口；在該第二開口中形成一重分佈層，使該重分布層電性耦接該金屬線，其中該重分佈層包括一彎曲頂表面；以及在該重分布層上方形成一第二介電層。
  2. 如請求項1之形成半導體結構的方法，更包括：在形成該圖案形成層之前，在該第一介電層上形成一晶種層；以及在形成該第二介電層之前去除該晶種層未被該重分佈層覆蓋的部份。
  3. 如請求項1之形成半導體結構的方法，其中形成該圖案形成層的操作包括在該第一介電層上形成一光阻層。
  4. 如請求項3之形成半導體結構的方法，其中形成該第二開口的操作包括對該光阻層進行一第一微影製程，且其中形成該底切特徵的操作包括在進行該第一微影製程之後對該光阻層進行一第二微影製程。
  5. 如請求項1之形成半導體結構的方法，其中形成該圖案形成層的操作包括在該第一介電層上形成一底層以及隨後在該底層上形成一光阻層，其 中該底層包括矽，且該光阻層實質上不包括矽。
  6. 如請求項5之形成半導體結構的方法，其中形成該第二開口的操作包括對該光阻層進行一微影製程，且形成該底切特徵的操作包括在進行該微影製程之後，相對於該光阻層選擇性地蝕刻該底層。
  7. 如請求項1之形成半導體結構的方法，更包括：在該第二介電層中形成一第三開口，以露出該重分佈層之一頂部；在該第二介電層上方形成一保護層，使得該保護層在該第三開口中延伸接觸該重分佈層之該頂部；在該保護層中形成一第四開口，以露出該重分佈層之該頂部；在該第四開口中形成一凸塊；以及在該凸塊上方形成一焊料特徵。
  8. 一種半導體結構，包括：一內連線結構，設置在一半導體基板上方，其中該內連線結構包括一導電線；一第一介電層，設置在該內連線結構上；一重分佈層，設置在該第一介電層上方，其中該重分佈層延伸通過該第一介電層以接觸該導電線，且該重分佈層包括一彎曲頂表面以及設置在該第一介電層的一頂表面上方的一基腳特徵，其中該彎曲頂表面在一圓角處與該重分佈層之一側壁相交；一第二介電層，設置在該重分佈層上方；一保護層，設置在該第二介電層上方；以及一導電特徵，設置在該重分佈層上方並電性耦接至該重分佈層。
  9. 如請求項8之半導體結構，其中該導電特徵的側壁係由該保護層 所定義。
  10. 如請求項8之半導體結構，更包括一含銅晶種層，設置在該重分佈層以及該第一介電層之間。
  11. 一種半導體結構，包括：一第一鈍化層，設置在一金屬線上方；一含銅重分佈層，設置在該第一鈍化層上方，其中該含銅重分佈層電性耦接該金屬線，且該含銅重分佈層接觸該第一鈍化層的一部份形成一銳角；一第二鈍化層，設置在該含銅重分佈層上方，其中該第二鈍化層以及該含銅重分佈層之間之一界面是彎曲的，該界面包括連續的一第一側壁以及一第二側壁，該第一側壁與該第一鈍化層形成該銳角，且該第二側壁的延伸方向與該第一鈍化層的表面的夾角大於該銳角；一聚合物層，設置在該第二鈍化層上方，其中該聚合物層之一部份延伸以接觸該含銅重分佈層；一凸塊，電性耦接該含銅重分佈層；以及一焊料層，設置在該凸塊上方。
  12. 如請求項11之半導體結構，更包括一含銅晶種層，位在該含銅重分佈層以及該第一鈍化層之間，且位在該含銅重分佈層以及該金屬線之間。
  13. 如請求項11之半導體結構，其中該凸塊的側壁延伸至該含銅重分佈層的該頂表面的下方。
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