TWI769436B - Method for measuring input capacitance of pin of electronic device - Google Patents

Abstract

A method for measuring an input capacitance of a pin of an electronic device includes, using a tester including Pin Electronics (PE), obtaining a first capacitance measurement while the pin is disconnected from the PE, and a second capacitance measurement while the pin is connected to the PE. The input capacitance of the pin is calculated from the first and second capacitance measurements.

Description

Method and device for measuring input capacitance of pins of electronic components

The present invention relates to an automated test equipment (ATE), and more particularly, to using the ATE to measure the input capacitance of a device under test (DUT).

An automated test equipment (ATE) is used to perform tests on a device (hereinafter referred to as a device under test or a DUT). When the device under test is an electronic device, such as an integrated circuit (IC), the ATE usually applies voltage and current patterns to the input end of the device under test, and measures the voltage at the output end of the device under test and current.

ATE can also be used to measure component characteristics, such as measuring the parameters of the component under test under various changing conditions.

Roughly speaking, ATE technology includes hardware and software, which can be found in the "Automatic Test Equipment" document published by F. Liguori in Wiley Encyclopedia of Electrical and Electronics Engineering in 1999.

According to an embodiment, the present invention provides a method for measuring an input capacitance value of a pin of an electronic component, comprising the steps of: using a tester including a pin circuit, when the pin is disconnected from the pin circuit Obtaining a first capacitance measurement when the pin is on, and obtaining a second capacitance measurement when the pin is connected to the pin circuit; and calculating the connection according to the first capacitance measurement and the second capacitance measurement The input capacitance value of the pin.

According to one embodiment, the step of obtaining each of the first capacitance measurement and the second capacitance measurement includes: using a current source to drive the pin circuit with at least a predefined current, and measuring the pin circuit corresponding to at least at least one voltage generated by a predefined current. According to an embodiment, the at least one voltage includes at least two voltages, wherein the step of calculating the input capacitance value includes: deriving a voltage slope over time from the at least one voltage, and calculating the input capacitance value according to the voltage slope.

According to one embodiment, the step of obtaining each of the first capacitance measurement and the second capacitance measurement includes prompting a user to disconnect the pin from the pin circuit before obtaining the first capacitance measurement, and prompting the user to connect the pin and the pin circuit before obtaining the second capacitance measurement value.

According to an embodiment, the present invention further provides a device for measuring an input capacitance value of a pin of an electronic component, comprising: a plurality of pin circuits connected to the pin; and a controller connected to the pin Obtain a first capacitance measurement when the pin is disconnected from the pin circuit, and obtain a second capacitance measurement when the pin is connected to the pin circuit, and obtain a second capacitance measurement according to the first capacitance measurement and the second capacitance measurement value to calculate the input capacitance value of the pin.

According to an embodiment, the present invention further provides a computer software product for measuring an input capacitance of a pin of an electronic component, the computer software product comprising a physical non-transitory computer readable medium for storing program instructions , when the processor coupled to the pin circuit connected to the pin reads the program instruction, the processor executes: obtains a first when the pin is disconnected from the pin circuit capacitance measurement, and obtaining a second capacitance measurement when the pin is connected to the pin circuit; and calculating the input of the pin based on the first capacitance measurement and the second capacitance measurement capacitance value.

100: Automated test machine

102: Controller

104: Pin circuit

106: Component to be tested

108: Test head

110: Socket

202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 252, 254, 256, 258, 260, 262: Steps

250: Process

302: Programmable Drive

304: switch

306: VOH comparator

308:VOL comparator

310: IOL Programmable Current Source

312: IOH programmable current source

314: Diode Bridge

316, 318: Sampler

320, 322, 324, 326: Diodes

FIG. 1 is a block diagram schematically illustrating an automated test equipment (ATE) according to an embodiment of the present invention.

FIG. 2 is a flow chart schematically illustrating a method for measuring the capacitance value of an input pin of a device under test according to an embodiment of the present invention.

FIG. 3 is a block diagram schematically illustrating the structure of a pin circuit (Pin Electronics, PE) according to an embodiment of the present invention.

FIG. 3A is a block diagram schematically depicting driving an IOL current to the DUT pins.

Figure 3B is a block diagram schematically depicting the receiving of IOH current from the DUT pins.

FIG. 4 is a screen shot of a pin circuit setting of an automated testing machine according to an embodiment of the present invention.

FIG. 5 is a screenshot of the DC setting of the automated testing machine according to an embodiment of the present invention.

FIG. 6 is a screen shot of a test sample of an automated testing machine according to an embodiment of the present invention.

The above figures are schematic and not to scale. Relative dimensions and proportions in the drawings are exaggerated or reduced for the purpose of precision and/or convenience, and the dimensions are arbitrary and not limited thereto. Like reference characters in the drawings represent similar elements.

The embodiments of the present invention will be described in detail below in conjunction with the drawings and examples, so as to fully understand and implement the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects.

As used herein, the singular forms such as "a", "the", "the" and the like are also intended to include the plural forms unless the context clearly dictates otherwise.

Introduction

Test equipment used for automated testing of electronic systems and integrated circuits is called automatic test equipment (ATE). Automated test machines can be used for component testing (such as wafer testing or assembly testing), and component characteristic measurement, such as measuring component parameters under changing conditions.

An automated testing machine usually includes a "pin electronics (PE)" module, which is coupled to the pins of the device under test (DUT). It should be noted that the term "pin circuit (PE)" may refer to the totality of electronic circuits coupled to the pins of the device under test. In the following description, "pin circuit (PE)" will be used to describe an electronic circuit coupled to a single DUT pin. With necessary modifications, the techniques described below can also be applied to other defined pin circuits.

Each pin circuit can be controlled to drive a DUT pin or measure the voltage level (and/or current) of the DUT pin. Traditionally, when the pin circuit is connected to a DUT input pin, the pin circuit will drive the DUT pin; when the pin circuit is connected to a DUT output pin, the pin circuit will measure The pin of the device under test; when the circuit of this pin is connected to an input and output (I/O) pin of the device under test, the circuit of this pin will be controlled by the software of the automatic test machine to drive or measure this pin at different times The pin of the component to be tested.

For each pin, the direct current (DC) specification of the output pin of the device under test usually defines the minimum and/or maximum voltage that the output signal of this pin should meet when a preset DC current is loaded. right Two parameters are usually defined for the logic pins of the device under test: the parameter VOH, which is the minimum logic 1 voltage level of the pin when the load DC current is IOH; and the parameter VOL, which is when the receiving DC current reaches When IOL, the maximum logic 0 voltage level of the pin. The usual values of this DC parameter are: VOH=2.4V; VOL=0.45V; IOH=400μA; and IOL=16mA.

In order to test whether the output pin of the device under test conforms to the above-mentioned DC specification, the pin circuit usually includes a programmable current source for sinking the current IOH or supplying the current IOL; and at least A voltage comparison unit is used to compare the voltage level on the output pin of the device under test with a predetermined voltage (eg, voltage VOL or VOH). During testing, the tester drives the input pin of the device under test with a sequence of voltages, so that the output pin of the device under test outputs a known logic value. Next, the tester detects the voltage comparison unit of the corresponding pin circuit, and checks the output signal of the voltage comparison unit to verify that the voltage of the output pin is higher than the voltage VOH (which is a logic high output signal) or lower than VOL (which is a logic high output signal) logic low output signal).

The alternating current (AC) parameter of the device under test is usually defined as the time when the pin of the device under test reaches a preset threshold voltage after a voltage change on one of the input pins of the device under test (for example, the rising edge of the clock input signal) reaches a preset threshold voltage. The DUT pin load has a predefined load (eg, 50pf). Usually two parameters are defined: parameter Tr, which is the time when the positive edge signal on the output pin of the device under test reaches VH (usually 2.0V); parameter Tf, which is the negative edge signal on the output pin of the device under test Time to reach VL (usually 0.8V). The above DC and AC specifications are abbreviations; more information about the DC and AC specifications of integrated circuits can be found in the aforementioned document "Automated Test Machines" by F. Liguori.

In order to test whether the device under test conforms to the alternating current (AC) specification, the pin circuit may further include at least one programmable timer for corresponding changes in the input pins of the device under test. Then sample the voltage comparison unit within a preset time. For example, in order to test the Tr parameter of the DUT output pin, the automated test tool can program the voltage threshold of the comparator to be the voltage VIH, and the timer to be programmed at the time of the clock (usually driven by the automated test tool) The comparator is sampled Tr (nanoseconds) after the rising edge.

It will be appreciated that a variety of calibration techniques are applicable to the foregoing description. For example, the timer can compensate for the delay of the clock output signal from the tester to the pin of the device under test, as well as the delay value of the sampling comparator.

Traditionally, with some exceptions, the input pins of the device under test are driven, not used for measurement, according to the stimuli of the test pattern. The slopes of the rising and falling edges of the input pins can be fixed or controllable. US Patent Application No. 16/269,573, filed by the applicant of the present application, discloses that a programmable-slew-rate edge signal can be applied by using a current source conventionally used to test output pins To the input pin of the device under test. The disclosures of the aforementioned US patent applications are incorporated herein by reference.

According to embodiments of the present invention, an automated test machine system includes software for generating test samples. A common test program includes a static PE configuration script and a dynamic PE test pattern. The configuration script is used to set up the driver and the comparator for the pinout. For example, the static configuration pin circuit should drive the input pin of the device under test to the logic high voltage level (VIH) and the logic low voltage level (VIL) respectively, and the pin circuit should test the logic of the output pin of the device under test. Low voltage level (VOL) and logic high voltage level (VOH), and the high load current and low load current that the pin circuit should load into the output pins of the device under test, and this static configuration during dynamic test sample execution will not change.

According to an embodiment of the present invention, the dynamic test sample dynamically defines some or all of the DUT pins, the driving methods of the DUT input pins, and the measurement of the DUT output pins (including the DUT pins) at different times. expected outcome). Traditionally, the time axis is divided into discrete time periods slot), and dynamic test samples define the characteristics of driving and measurement (eg, expected results) at time-slot resolution.

According to an embodiment, in order to drive the DUT pins, the pin circuit module typically includes a driver having two signal levels, a low input voltage (VIL) and a high input voltage (VIH). The static configuration script usually sets the VIL and VIH values for each pin circuit module, while the dynamic test sample defines whether the pin circuit in each slot when the pin circuit drives the pin of the device under test should drive the pin to VIH or not. VIL value. For example, a pinout circuit can be statically configured with VIL=0.8V and VIH=2.0V, while a dynamic test sample for a pinout circuit can be specified as 1-1-0-0-1. In the first and second time slots, the pin circuit will drive the DUT pins to a signal level of 2.0V, and in the third and fourth time slots, drive the DUT pins to a 0.8V signal level , and drive the pin of the device under test to the signal level of 2.0V in the fifth time slot.

According to the embodiment of the present invention, the measurement circuit of the pin circuit generally includes two parts: a comparator and a load control. The comparator is used to compare the voltage level on the pin of the device under test with the two voltage levels, which are set by the low output VOL and the high output VOH of the configuration script. The pin circuit verifies that the voltage on the pin exceeds VOH during the time slot that the measurement portion of the dynamic test (eg, the expected result) specifies that the pin should be tested for a logic-high signal. The pin circuit verifies that the voltage on this pin is lower than VOL during the time slot that the measurement portion of the dynamic test (eg, the expected result) specifies that this pin should be tested for a logic-low signal.

In one embodiment, the load control is used to apply one of two programmable load currents (low output current IOL and high output current IOH) to the DUT pins. These two current values are often programmed in configuration scripts. In the following description, the current flowing from the pin circuit to the pin is called positive current, and the current flowing from the pin to the pin circuit is called negative current. Furthermore, the driving current is meant to be "sourcing current", and the received current is meant to be "sinking current". In a time slot where the test sample indicates that this pin is to be tested with a logic low signal, the pin circuit will apply a current equal to IOL to The DUT pin, and when the test sample indicates that this pin is to be tested with a logic high signal, the pin circuit will apply a current equal to IOH (usually a negative current) to the DUT pin.

For example, for a DUT pin, the test script can define a logic low level (VOL) not exceeding 0.4V when the load current (IOL) is 1.6mA, and a logic high level (VOH) when the load current (IOH) is 0.1mA Should not be less than 2.0V. For output pins, the current example of the dynamic test sample is 1-1-1-0-1-1. In time slots 1, 2, 3, 5, and 6, the pin circuit will drive the pin at -0.1mA and check if the voltage on this pin is higher than 2.0V. In time slot 4, the pin circuit will drive the pin at 1.6mA and check if the voltage on the pin is below 0.4V.

Characterization process

According to embodiments of the present invention, automated test equipment can characterize integrated circuits under varying conditions (eg, ambient temperature, power supply voltage, etc.) by measuring AC and DC parameters (amongst other parameters). This characterization process may involve testing multiple components, sometimes from different manufacturing lots, and calculating the mean and standard deviation of the measured parameters.

In some embodiments, the pinout circuits of the automated test equipment use measurement circuits to directly measure parameters, such as VOH, VOL, Tr, and Tf. In other embodiments, the parameter measurement can be performed by the AC and DC test circuits of the pin circuit without additional circuits. For example, in one embodiment, in order to measure VOH, an automated test machine can repeatedly perform tests with varying VOH voltage values; and, in response to the test results, determine the actual value of VOH. In some embodiments, in order to test a parameter, the automated testing machine initially sets the parameter to an extreme value (eg, VOL=0V), and then increments (or decrements) the parameter by a small value (eg, VOL=0V) in repeated tests 1mV), and record the results of each test until the other extreme value is reached. In other embodiments, the measurement can be done by searching, where parameter values are incremented or decremented according to the pass or fail result of the previous test.

Traditionally, some input parameters of integrated circuits have been characterized by special equipment, sometimes not. For example, the capacitance value of the input pin of the device under test is usually specified but rarely characterized (or is characterized using dedicated equipment). The difficulty in measuring the input capacitance value lies in the stray capacitance of the circuit of the automated testing machine, which is coupled to the pin of the device under test and is usually larger than the input capacitance value of the pin.

(In the following description, the term "pin capacitance" refers to the capacitance between the pin and one of the ground pins of the device under test)

According to an embodiment of the present invention, a simple method for measuring the capacitance value of the input pin of the device under test is provided, which uses the pin circuit resources that are not used for the AC and DC tests of the output pin of the device under test, and does not need to add a dedicated circuit . Other embodiments provide a device integrated circuit for testing and characterizing integrated circuits, some of which can be used to test the AC and DC parameters of the DUT output pins, and measure the input capacitance of the DUT input pins value.

In one embodiment, the method includes: when the device under test is not connected, obtaining a first capacitance measurement value of the pin circuit associated with the test input pin, and when the device under test is connected, obtaining the test input pin associated The second capacitance measurement value of the pin circuit of the input pin is calculated, and the capacitance value of the input pin is calculated according to the two capacitance measurement values (eg, the second capacitance measurement value is subtracted from the first capacitance measurement value). It should be noted that the terms "first" and "second" above do not denote a chronological order of measurements.

In some embodiments, the step of obtaining a capacitance measurement between two leads includes connecting one of the leads to a current source, and measuring the time T1 required for the voltage between the leads to equal the first threshold voltage V1; and measuring The time T2 required for the voltage between the leads to be equal to the second threshold voltage V2. And, calculate the capacitance value according to the time of the two measurements and the current provided by the current source, for example, C=I*(T2-T1)/(V2-V1), where I is the current (amps), and the units of T1 and T2 are Seconds, V1 and V2 are in volts.

In the embodiment, one of the leads is the ground lead of the device under test (or one of multiple ground leads); the voltage on the ground lead is zero, so it is only necessary to refer to the voltage on the other lead (pin). pressure. The term "pin voltage" means the voltage between the pin and the ground pin, and the term "pin capacitance" means the capacitance value between the pin and the ground pin.

In some embodiments of the present invention, each pin circuit includes two voltage comparison units. Each input pin of the device under test is connected in parallel to two voltage comparison units of the respective pin circuit, wherein the first voltage comparator compares the pin voltage with the first threshold value, and the second voltage comparator compares the pin voltage and the second threshold voltage. In some embodiments, to measure the time it takes for the voltage on the pin to rise to equal the threshold, the pin circuit tests whether the voltage on the pin rises above the threshold at a given time (initially 0); the tester then repeats Execute the test, increasing the time until the test passes. In another embodiment, the time is initially set to a high value, and if the test fails, the test is then decremented until the test passes.

In yet another embodiment, a binary search is performed in consecutive tests, as shown in Table 1:

First, the time is set to 0, and the test fails. Next, in successive steps, according to the previous test result, the time is increased or decreased by half of the time increased or decreased by the previous test until the required measurement resolution is satisfied (in the exemplary embodiment of Table 1, Measurement time result = 909ns, resolution 1ns).

It should be noted that although the embodiment of the automated testing machine of the present invention mainly tests digital input pins, this method of measuring the input capacitance value can be used for digital and analog input pins.

It should be further noted that, in some embodiments, the techniques disclosed in the present invention can be implemented by software running on conventional testers (eg, simpler and low-end testers). Therefore, in accordance with embodiments of the present invention , the capacitance value of the input pin of the component to be tested can be tested and characterized by measuring the circuit of the automatic test machine without using an additional circuit.

instructions

FIG. 1 is a block diagram schematically illustrating an automated test equipment (ATE) 100 according to an embodiment of the present invention.

The automatic testing machine 100 includes a controller 102 for executing software programs and controlling the operation of the automatic testing machine; a plurality of pin circuit modules (PE) 104, each of which is used for testing and /or stimulate one of the pins of the device under test (DUT) 106 . The controller is connected using busbars Connected to the pin circuit unit, wherein the controller and the pin circuit unit perform configuration and data communication of dynamic test samples, and the pin circuit transmits the test results back to the controller.

The number of pin circuit modules is equal to the number of pins of the device under test (when the number of test pins is lower than the number of pin circuit modules, some pin circuit modules can be turned off).

The automated testing machine 100 further includes a test head 108 that provides an interface on the socket 110 for characterization, or a load board (not shown) that interfaces for wafer level testing and assembly device testing.

The socket 110 can be a zero-insertion-force (ZIF) socket, which can quickly and easily plug and unplug the device under test.

Automated test machines can be used for wafer-level testing, packaged device testing, or device characterization. In test terminology, wafer-level testing refers to "wafer-Sort", while packaged component testing refers to "assembly sort".

In order to measure the capacitance value of the input pin of the device under test, the controller sets a corresponding pin circuit to couple the current source to the pin of the device under test, and performs a series of tests (which will be described in conjunction with Fig. 2 below), to measure the rate of change of voltage on the pin. The controller then calculates the capacitance value based on the rate of change and the current source.

The automated testing machine repeats the above capacitance measurement twice. One time the device under test 106 is inserted in the zero insertion force receptacle 110 and the other time the device under test is not inserted in the zero insertion force receptacle 110 . The capacitance value of the input pin can be calculated from the above two measurement values, for example, the capacitance value measured when the device under test is inserted minus the capacitance value measured when the device under test is not inserted.

Therefore, according to the exemplary embodiment described in conjunction with FIG. 1, the automated testing machine can measure and characterize the input capacitance of the DUT pins with the same circuits used by the automated testing machine for DC and AC testing.

It can be understood that the above-mentioned structure of the automated testing machine 100 is only an example. The automated testing machine of the technology disclosed in the present invention is not limited to the above examples.

In some embodiments, the controller includes a general-purpose processor and an interface board. In one embodiment, an interface board is not used, and the computer communicates directly with the pin circuit module 104 . In some embodiments, the controller includes a plurality of processors; in other embodiments, the automated testing machine does not use the processor, but is connected to the automated testing machine on other computers or via a communication network (eg, the Internet). Execute the test software on the computer.

FIG. 2 is a flow chart 200 schematically illustrating a method for measuring the capacitance value of the input pin of the device under test according to an embodiment of the present invention. The flowchart 200 is executed by the controller 102 shown in FIG. 1 .

At the beginning of the process, in a DUT pulling step 202, the processor requests a processing program (not shown in the figure) to pull out (or disconnect) the DUT 106 from the socket 110, and in some embodiments, This step is done manually by the user. Next, in step 202, the controller enters a voltage setting step 204, and two threshold voltages (which correspond to the test pins V1 and V2 respectively) are set to the pin circuit module 104 (FIG. 1). The processor then enters a step 206 of connecting the current source, and controls the pin circuit to connect the current source (providing current I) to the pin.

Next, at step 206, the controller enters a measurement T1d step 208, where the controller measures the time it takes for the input pin voltage to rise from an initial low voltage (eg, 0V volts) to V1. When the DUT is disconnected (time measurement step 208 includes sub-steps, which will be described in the following paragraphs), this result is referred to as T1d-T1. Next, in step 208, the controller enters a measurement T2d step 210, where the controller measures the time required for the voltage of the input pin to rise from the initial low voltage to V2. When the DUT is disconnected, the result is T2d-T2. Step 210 includes the same sub-steps as step 208, which will be described below.

From steps 202 to 210, the above measured parameters can be used to calculate stray capacitance, which is the capacitance value of the lines and circuits connected to the pins of the device under test. Next, when the pin of the device under test is connected to the automated testing machine, the controller measures the required parameters for calculating the capacitance value of the pin of the device under test. In a In the DUT insertion step 212, the controller requests the device under test (DUT) to be inserted into the socket; then, when the DUT is connected, in a measure T1c step 214, the controller measures the T1 value; and when the DUT is connected, at A measure T2c step 216, the T2 value is measured.

After step 216, all measurements are completed and the controller can calculate the capacitance value. When the DUT is disconnected, in the calculating Cd step 218, the controller calculates the capacitance value, for example, according to the following formula: Cd=(T2d-T1d)*I/(V2-V1)

Next, when the DUT is connected, in a calculation Cc step 220, the controller calculates the capacitance value, for example, according to the following formula: Cc=(T2c-T1c)*I/(V2-V1)

Finally, in a calculation C step 222, the controller subtracts Cd from Cc to obtain the input capacitance value of the pin of the device under test.

Process 250 describes the sub-steps of each time measurement step 208 , 210 , 214 and 216 . Executed by the controller, this process measures the time required for the DUT pin to rise to the voltage level V. The process starts from a set T step 252, where the controller sets a time variable T to a minimum value (in the exemplary embodiment of FIG. 2, the minimum value is 0), and sets a ΔT time variable to an initial value, which are the same Or more than half of the maximum expected T value. Next, at an execute test step 254, the controller executes the test and checks whether the test is passed at T=0 (when re-entering step 254, whether the test is passed at other T values.)

If, at step 254, the test fails, the controller proceeds to an increment ΔT step 256, where the T value is incremented by one-half of the ΔT value. Similarly, if the test passes at step 254, the controller proceeds to a decrement ΔT step 258 where T is decremented by half the value of ΔT each time.

After step 256 or step 258, the controller proceeds to an update ΔT step 260 to halve the value of ΔT. Next, the processor proceeds to confirm the minimum ΔT value step 262 to check whether the current value of ΔT is still not less than a minimum value (which is the required measurement resolution). If ΔT is less than the required solution If the resolution is determined, the process ends; or, if ΔT is not smaller than the resolution, the controller re-enters step 254 .

Therefore, in fact, the time measurement process 250 is a binary search, which tests the measurement time in a log2(max_value/resolution) manner, where max_value is the maximum value that the T parameter can reach, and resolution is the measurement resolution.

To sum up, the process 200 describes a method for calculating the input capacitance value of the DUT pin, which includes: (a) connecting a predetermined current source to the DUT pin; (b) disconnecting the DUT, Obtain two times corresponding to the measurement pin reaching the first voltage threshold and the second voltage threshold; (c) connecting the device under test, and then obtaining the measurement pin reaching the first voltage threshold and the second voltage threshold The corresponding two times; (d) according to the four measurement times, calculate C.

Therefore, according to the exemplary embodiment described in FIG. 2, a method of measuring the input of the input pin of the device under test can be realized, which uses the tester resources for testing the AC and DC parameters of the device under test. The method disclosed in the present invention is inexpensive and does not require any hardware resources except for the resources used for AC and DC testing of the device under test.

It can be understood that the above description of the exemplary embodiment in conjunction with FIG. 2 is only an example. The capacitance measurement method of the technology disclosed in the present invention is not limited to the above examples. For example, in other embodiments, steps 202 and 212 may include confirming whether the unplug/plug operation is completed (if the unplug/plug operation is performed by an operator, the confirmation result is preset to be true). In various embodiments, the order of the above steps can be changed, for example, the step of measuring when the device under test is inserted can be before the step of measuring when the device under test is unplugged; step 218 can be completed after step 212 .

In some embodiments, the V1 and V2 thresholds used when the DUT is pulled out may be different from the V1 and V2 thresholds used when the DUT is inserted, eg, to minimize measurement errors.

The time measurement process 250 is an example of a time measurement method using binary search. This method is fast, but prone to measurement errors. In some embodiments, a slower linear approach may be used in which the full range of expected time results are tested and recorded. Then, the controller can check the results for a single pass or fail event (when T is moved forward or backward, it is found that a pass result is surrounded by multiple fail results, or a fail result is surrounded by multiple pass results. Results wrap around) filtering to derive a noise-filtered time measurement.

In other embodiments, the binary and/or linear search may be performed several times, and the final time parameter may be derived from the results. For example, in one embodiment, a binary search is performed twice; if the result obtained is agreed, the time measurement is complete; if the result changes, a linear search is performed.

FIG. 3 schematically illustrates the structure of the pin circuit 104 (FIG. 1) according to an embodiment of the present invention. The pin circuit communicates with the controller 102 to receive configuration and sample data, and to transmit test results. The pin circuit is connected to a line connected to a single pin (shown in FIG. 1 ) of the device under test 106 via the test head 108 and the socket 110 .

In order to drive the DUT pins, the pin circuit 104 includes a programmable driver 302 for outputting two pre-configured signal levels VIL and VIH according to a control input signal (HIGH/LOW in the figure) One of them; and a switch 304 for connecting the programmable driver to the DUT pin or disconnecting the programmable driver from the DUT pin.

In order to measure the DUT pins, each pin circuit 104 includes: a VOH comparator 306 for verifying whether the voltage level of the DUT pins is higher than the pre-configured VOH; a VOL comparator 308 for To verify whether the voltage level of the pin of the device under test is lower than the pre-configured VOL; an IOL programmable current source 310, which is used to provide a pre-configured current IOL; an IOH programmable current source 312, which is used for sinking preconfigured current IOH; and a diode bridge 314 including four diodes and a programmable voltage source VREF.

The diode bridge is used to perform the following steps: (a) when the voltage level on the DUT pin is lower than VREF, flow the current provided by the IOL programmable current source 310 to the DUT pin, and from VREF The voltage source sinks the current provided by the IOH programmable current source 312; (b) when the potential of the pin is higher than VREF, the current provided by the IOH programmable current source 312 is drawn from the DUT pin to make the IOL programmable The current provided by the VREF current source 310 flows into the VREF voltage source (the function and operation of the diode bridge 314 will be described below in conjunction with FIGS. 3A and 3B).

For AC testing, the pin circuit 104 further includes a sampler 316 and 318. The sampler 316 is used to latch the output of the VOL comparator 308 at time T1, and the sampler 318 is used to latch the latched VOL comparator. The output of 308 at time T2.

The operation of the diode bridge 314 will be explained below in conjunction with Figures 3A and 3B.

Figure 3A is a schematic illustration of driving the IOL current into the DUT pins. The voltage Vref is set to be at least 1.3V higher than the expected output voltage of the device under test, which is twice the threshold voltage of the silicon diode (for ease of explanation, the forward threshold voltage of the silicon diode is assumed to be 0.65V here) ). The diode 320 is turned on, allowing the current IOL to flow into the pin of the device under test. The voltage of the IOL port of the diode bridge is Vdut+0.65V; the diode 324 is reverse biased and does not conduct. The current drawn by the IOH current source is supplied by Vref via the diode 326; the voltage at the IOH port of the diode bridge is Vref-0.65V=Vdut+0.65V. Diode 322 is reverse biased to not conduct.

Figure 3B is a block diagram schematically depicting the sinking of IOH current from the DUT pins. The voltage Vref is set to be at least 1.3V lower than the expected prediction element output voltage. The diode 322 is turned on, sinking the current IOH from the pin of the device under test. The voltage at the IOH port of the diode bridge is Vdut-0.65V; therefore, diode 326 is reverse biased and does not conduct. The current provided by the IOL current source can be drawn from Vref via the diode 324; the voltage at the IOL port of the diode bridge is Vref+0.65V=Vdut-0.65V. Diode 320 is reverse biased and does not conduct.

To sum up, the controller 102 (FIG. 1) can independently control each pin of the device under test to perform the following operations: (a) According to the setting of the switch 304, determine whether to drive the pin circuit or monitor the pin; ( b) If the pin circuit drives the pin, then according to the setting of the high/low input of the driver 302, it is determined whether the pin circuit drives the pin with a logic low or logic high signal, and the driven voltage level (if the pin circuit is driven) is determined. If the driving logic of the pin circuit is high, it is VIH, and if the driving logic of the pin circuit is low, it is VIL); (c) If the pin circuit monitors the pin, then according to the set Vref voltage, it is determined whether the pin circuit is coupled to the current source IOL (driving current flowing into the pin) or IOH current source (sinking current from the pin), and (by setting the IOL and IOH) to determine the current source rate; (d) if the pin circuit is monitoring the pin, set the test thresholds VOL and VOH , the logic low and logic high voltage levels of the device under test used to test the voltage level driven by the device under test; and (e) for the AC test, select the rise time (T2) that the pins of the device under test must conform to Or fall time (T1) parameter. Typically, in AC testing, no current source is connected to the pins.

It is noted here that this configuration may change frequently during testing. According to the dynamic test samples, in some time slots, the pins can be tested for logic low (logic low); while in other time slots, the pins can be tested for logic high (logic high). Furthermore, the IO pins that are input pins in some time slots and output pins in other time slots can be alternately driven and tested according to dynamic test samples. According to an embodiment of the present invention, in order to measure the input capacitance, the pin circuit couples the current source to the pin, and measures Tr or Tf.

Therefore, according to the exemplary embodiments shown in FIGS. 3, 3A, and 3B, the automated testing machine with pin circuits can test and characterize the logic functions of the device under test, including characterizing the input capacitance value of the pins of the device under test. , and do not need to increase the dedicated capacitance measurement circuit.

It should be understood that the structure of the above-mentioned pin circuit 104 is for illustration only. The pin circuit of the technology disclosed in the present invention is not limited to the above examples. In some embodiments, additional circuitry may be coupled to each or some of the pin circuits, eg, for precision analog measurements. In one embodiment, diode bridge 314 includes similar functions implemented in different circuits. In an embodiment, the switch 304 may be an electro-mechanical relay or an electronic switch.

Another embodiment described in the current patent application discloses the measurement method of the input pins of the device under test as an example of a commercially available automated test machine (Chroma 3650-EX), using the DC and AC quantities of the tester test circuit. The content of 3650-EX-E-201709-500 "SOC/ANALOG Test System Model 3650-EX" published by Chroma in 2017 is cited as a reference.

FIG. 4 is a schematic diagram of a screen shot 400 of a pin circuit (PE) setting of an automated testing machine according to an embodiment of the present invention. This screen shot is part of a graphical user interface (GUI) that allows users to easily program pin circuit settings.

This screen shot includes a programmable driver 402 (302 in Figure 3), which can drive the DUT pin-configurable voltage level VIL or VIH (according to the dynamic test sample); a switch 404 (section 302) 304 shown in Figure 3), which is used to connect the driver 302 to the DUT pin according to the dynamic test sample; VOH and VOL comparator 406, which is used for the voltage on the DUT pin and the configurable VOH and VOL value; and a load cell 408 including a diode bridge with programmable current sources IOL and IOH (similar to cells 314, 310 and 312 in FIG. 3). All configurable parameters VIH, VIL, VOH, VOL, IOH, IOL, and VREF can be set using the test script; or the desired values can be entered in the digital input sub-window shown in Figure 4.

According to an embodiment of the present invention, the user-programmable automated testing machine measures the rise time (or in other embodiments, the fall time) of a signal of the pin voltage when the device under test is connected and when the device under test is disconnected. , to measure the input pin capacitance. In order to measure the rise time, the automated test machine sets VREF=VOH+1.3V (or higher), IOL=I1 (eg 1mA), VIL=0V (or other suitable potential lower than VOL), VOL (eg 0.4V) ), and VOH (eg, 2.0V). Next, in the first time slot, the automated testing machine setting switch 402 is turned on to ensure that the pin starts from a low voltage, and in the second time slot, the automated testing machine turns off the switch 402 . The voltage on the pin rises, and its rising slope is determined by the current source and the value of the capacitor (mainly). By repeating the above test, the change time of the output of the comparator 406 is sampled, The tester can measure the rise time of the voltage on the pin from the voltage VOL to the voltage VOH, and calculate the capacitance value C=Tr*I/(VOH-VOL). (Herein, the definition of Tr in this example only includes the time of the signal rising from the voltage VOL to the voltage VOH.)

The time measurement can also be done by measuring the falling edge of the pin of the device under test. In order to measure the fall time, the automated test machine sets VREF=VOL-1.3V (or lower), IOH=I1 (eg -1mA), VIH=5V (or other suitable potential higher than VOH), VOL (eg 0.4 V) and VOH (eg 2.0V). In the first time slot, when the automatic test machine setting switch 402 is turned on, the pin starts from a high voltage. In the second time slot, the voltage on the pin drops. By repeating the above test and sampling the time change of the output of the comparator 406, the tester can measure the falling time of the voltage on the pin from VOH to VOL, and calculate the capacitance value C=Tf*I/(VOH-VOL) .

It can be understood that the above screenshot 400 is for illustration only. In other embodiments, the values of VIH, VIL, VOH, VOL, IOL, IOH, and VREF can be set using any other GUI programming; or, non-graphical programming can be used to set the script.

FIG. 5 is a screen shot 500 of the DC setting of an automated testing machine according to an embodiment of the present invention. This screen shot includes two set level commands 502 and 504 for setting a positive edge (pull-up) and a negative (pull-down) edge, respectively. Level setting commands are usually embedded in static configuration scripts.

In the exemplary embodiment depicted in Figure 5, the set level command receives 8 arguments: 1. a pin name argument 506; 2. a logic low drive level argument 508 ("VIL"), which It can be used to set the slope start level of Tr measurement; 3. A logic high drive level parameter 510 (“VIH”), which can be used to set the slope start level of Tf measurement; 4. A logic low comparison threshold parameter count512("VOL"); 5. a logic high compare threshold argument 514 ("VOH"); 6. a logic low load argument 516 ("IOL"); 7. a logic high load argument 518 ("IOH"); and 8. a The diode bridge voltage reference 520 ("VREF) can set a high level for rising edges and a low level for falling edges.

The above-mentioned arguments can be input by setting the level command, which is not related to the present invention, so it will not be repeated here.

FIG. 6 is a screen shot 600 of a test sample of an automated testing machine according to an embodiment of the present invention. According to the exemplary embodiment of FIG. 6, the test sample includes a PIN_PAT part, in which a sequential list of pin names is defined as follows. A WAVE part (3600_WAVE in the diagram), which defines the symbols used in the master sample, and a master sample part (MAIN_PAT in the diagram), which defines the programming of all pins in all the time slots of this sample. PIN_PAT and WAVE are configuration scripts, while MAIN_PAT is a dynamic test sample.

According to the exemplary embodiment of Figure 6, an ATE time slot is divided into 6 individually programmable "periods". The timing of this period is defined in the "timing-set" line, which is part of a test setup (eg, a configuration script), and is not shown in the figure. It should be noted that the periods are not necessarily mutually exclusive.

Each line of the WAVE section of the test sample contains:

1. A symbol, or a pair of lowercase and uppercase symbols. Symbols will be used in dynamic test samples. When represented using a pair of lowercase and uppercase letters, the lowercase letters represent the logical low level and the uppercase letters represent the logical high level.

2. After the equal sign (=), 6 indicators are used to represent the 6 states of the pin circuit during the 6 periods of the time slot.

3. Additional symbol information (not relevant to the present invention)

The six periods of each time slot are hereinafter referred to as T1 to T6. T1 and T2 are defined as driving periods. T3 and T4 are defined as switching from drive to compare (but can also be used to define the drive period, similar to T1 and T2). T5 and T6 are defined as comparison periods (T5 and T6 also correspond to T1 and T2 respectively in the general description of FIG. 3).

The following describes the definition of the period term in the WAVE part (the first 6 arguments): DX: Drive, value=x (don't care). The pin circuit settings will not change during this period (the same value as the previous period).

IOFF: During this period, the pin circuit is a comparator (the driver 402 in Fig. 4 is turned off).

ION: Drive 402 on

SX: S means strobe and X means "don't care". The automated test rig is in compare mode but ignores fail/pass results (IOH and IOL are enabled).

DTP: Driver Profile. Depending on the portion of the sample (eg, for an a/A symbol, drive the pin to logic low when the sample is represented as "a" and drive the pin to logic high when the sample is represented as "A"), either a 0 or a 1 is driven.

D1: Drive logic "1" during this period, regardless of sample data.

DTP/: Similar to DTP, but the data driven is inverted (eg, drive logic low for uppercase sample symbols; drive logic high for lowercase sample symbols).

h/H designation - same as above.

STP: Compare.

The third part of the test sample is the dynamic sample (MAIN_PAT). This sample contains an annotation pin header followed by a symbol row. Such rows correspond to consecutive time slots; each row contains a plurality of symbols, wherein the consecutive symbols define the samples in this corresponding time slot for consecutive pin circuit modules.

The symbol "Super0_0" at the end of each pattern line designates a time setting that is part of the test configuration script and is used to define timing values for the 6 time periods.

In the exemplary embodiment of FIG. 6, the automated test tool measures the timing on the CLK pin 602. The CLK pin can assume a/A format 604 or h/H format 606, where a/A format 604 is defined as:

‧Time 1 is DTP (Driver Data)

‧Period 2 is DX: continue to drive data

‧Time period 3 is ION: turn on the driver 402 (Fig. 4)

‧DX in period 4: same content as period 3 without change

‧Times 5 and 6 are SX: compare but ignore the comparison result (both IOL and IOH are turned off because ION is programmed in time period T3); h/H format is defined as: ‧DX during time period 1: continue to previous time The state of the last period of the slot; DX in period 2: continue previous state; IOFF in period 3: drive 402 turned off (FIG. 4); DX in period 4: same as period 3 without change ; • STP in period 5: data and the sign in this sample; • STP/ in period 6: Compare the opposite value of the data and the sign in this sample.

In the sample portion of the screen shot, the CLK pin 602 (and all other pins except the reset pin) in the sixth time slot 608 assumes an "a" format and drives the corresponding pin to 0V (5th Argument 508 shown in the figure). During the seventh time slot 610, the CLK pin 602 (and all other pins except the reset pin) assume an h format to check if the logic value of this row is a logic low "0" during period 5 And in period 6 it is logic high "1".

Next, the automated test machine can vary the timing of the fifth and sixth periods to measure the pin voltage reaching 1V and 2V (Fig. 5) when the pin is charged with a 1mA current source (parameter 516 shown in Fig. 5). Arguments 512 and 514) shown.

Thus, according to the exemplary embodiments of Figures 5 and 6, a commercially available Chroma3650 tester can be programmed to measure the voltage rise or fall time at a given load current charge, and calculate the time to test using an embodiment of the method of the present invention. Capacitance value of any input pin of the device.

The Chroma 3650 automated test bench and the Chroma 3650 screenshots shown in Figures 4 to 6 for multiple unit settings and programming are for clarity of concept only. Other embodiments may use any other suitable setting programming and screen capture. The above settings and programming are applicable to the Chroma tester; the settings and programming of other testers can be changed according to the hardware settings and programming interface of other testers, and different screenshots can also be used.

The pin circuit 104 (FIG. 1) may be a single integrated circuit, a collection of multiple integrated circuits, a multi-chip carrier, or a printed circuit board. In some embodiments, a group of pin circuits or all of the pin circuits can be grouped in the same physical object (eg, in a single integrated circuit).

A portion of the automated testing machine 100, such as the controller 102, may be implemented in hardware, software, or a combination of hardware and software. The controller 102 and/or the pin circuit 104 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of a field programmable gate array and an application oriented IC.

In some embodiments, the controller 102 includes a general-purpose programmable processor that can be programmed in software to perform the functions described herein. The software may be downloaded to the processor in the form of an electronic signal, or, for example, the software may be stored on a non-transitory tangible medium such as magnetic memory, optical memory, or electronic memory.

Although the present invention is disclosed above by the aforementioned embodiments, it is not intended to limit the present invention. Anyone who is familiar with the similar arts can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of patent protection shall be determined by the scope of the patent application attached to this specification.

100: Automated test machine

102: Controller

104: Pin circuit

106: Component to be tested

108: Test head

110: Socket

Claims (9)

A method for measuring an input capacitance value of a pin of an electronic component, comprising: a driver selectively controlling a first programmable current source or a second programmable current source to deliver current to the pin, and The output current value of the first programmable current source is higher than the output current value of the second programmable current source; a tester including a pin circuit is used to obtain when the pin is disconnected from the pin circuit a first capacitance measurement, and a second capacitance measurement obtained when the pin is connected to the pin circuit; and calculating the pin according to the first capacitance measurement and the second capacitance measurement the input capacitance value. The method of claim 1, wherein the step of obtaining each of the first capacitance measurement and the second capacitance measurement comprises: using a current source to drive the pin circuit with at least a predefined current, and At least one voltage generated by the pin circuit corresponding to the at least one predefined current is measured. The method of claim 2, wherein the at least one voltage comprises at least two voltages, and wherein the step of calculating the input capacitance value comprises: deriving a voltage slope over time from the at least one voltage, and calculating based on the voltage slope the input capacitance value. The method of claim 1, wherein the step of obtaining the first capacitance measurement and the second capacitance measurement comprises: prompting a user to associate the pin with the second capacitance measurement before obtaining the first capacitance measurement The pin circuit is disconnected, and the user is prompted to connect the pin and the pin circuit. A device for measuring an input capacitance value of a pin of an electronic component, comprising: a plurality of pin circuits connected to the pin, each pin circuit respectively comprising a first programmable current source, a second programmable current source A programmable current source, and a driver, the output current value of the first programmable current source is higher than the output current value of the second programmable current source, the driver is respectively connected to the first programmable current source and the a second programmable current source for selectively causing the first programmable current source or the second programmable current source to output current to the pin; and a controller connected between the pin and the pin obtaining a first capacitance measurement when the pin circuit is disconnected, and obtaining a second capacitance measurement when the pin is connected to the pin circuit, and obtaining a first capacitance measurement according to the first capacitance measurement and the second capacitance The measured value calculates the input capacitance value of the pin. The device of claim 5, further comprising a current source, wherein the controller generates at least the pin circuit by instructing a current source to drive the pin circuit with at least a predefined current, and measuring the pin circuit in response to the current a voltage to obtain each of the first capacitance measurement and the second capacitance measurement. The apparatus of claim 6, wherein the at least one voltage includes at least two voltages, wherein the controller derives a voltage slope over time from the voltage, and calculates the input capacitance value according to the voltage slope. The apparatus of claim 5, wherein before obtaining the first capacitance measurement, the controller prompts a user to disconnect the pin from the pin circuit, and before obtaining the second capacitance measurement Previously, the controller prompted the user to connect the pin and the circuit of the pin. A physical non-transitory computer readable medium, a driver can selectively control a first programmable current source or a second programmable current source to deliver current to the pin, and the first programmable current The output current value of the source is higher than the output current of the second programmable current source The flow value is used to measure an input capacitance value of a pin of an electronic component. The physical non-transitory computer-readable medium is used to store program instructions when coupled to the processor of the pin circuit connected to the pin. When reading the program command, the processor executes: obtaining a first capacitance measurement when the pin is disconnected from the pin circuit, and obtaining a second capacitance when the pin is connected to the pin circuit a measurement value; and calculating the input capacitance value of the pin according to the first capacitance measurement value and the second capacitance measurement value.

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