JP2010009475A - Electronic circuit analysis apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit analysis apparatus for confirming operation of an electronic circuit, which prevents circuit analysis from being performed incorrectly even if the measurement accuracy of wave form information is low when the circuit analysis is performed especially by using an IBIS model. <P>SOLUTION: The electronic circuit analysis apparatus receives inputs of the voltage-current characteristic and wave form information of an output element model with a load resistance connected, to perform a circuit analysis. The electronic circuit analysis apparatus includes: a means which creates a switching characteristic in an ON/OFF state change of a switching means contained in the output element model from the wave form information; a permissible current value setting means which sets a permissible current value capable of permitting a current value flowing in the state change of the switching means in comparison to a current value of the steady state of the switching means; and a display means which calculates a range of a value of the switching characteristic of the switching means not exceeding the set permissible current value from the set permissible current value, the voltage-current characteristic, and a value of the load resistance, to highlight-display a part being abnormal in the switching characteristic of the switching means on the wave form information. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic circuit analysis apparatus, an electronic circuit analysis method, and an electronic circuit analysis program for confirming the operation of an electronic circuit.

  Nowadays, driving voltages of circuit elements such as digital LSI (large scale integration) and multichip modules are lowered, and the operating frequency is also increased. Under such circumstances, the operation timing and noise margin of elements in the design of a printed circuit board have been reduced, making it difficult to design electronic devices. In particular, with regard to operation timing, analysis accuracy in the order of several picoseconds (ps) is required.

  On the other hand, the product development period is shortened, and a rapid and highly accurate analysis technique is required in the pre-production stage of the product. For this reason, establishment of an analysis method having a short analysis time while maintaining high analysis accuracy is desired.

  In such a situation, an IBIS model (Input / Output Buffer Information Specification) which is an operation model describing an operation result under a specific condition of an element as an LSI element model used for simulation of an electronic circuit in a conventional printed circuit board design. Model) is being provided.

  This IBIS model has been expanded with the advancement of semiconductor technology, and today there are two ways to express the rising and falling transient characteristics of driver elements. One is the load circuit shown in FIG. 18 (a) and the model (RAMP model) shown in FIG. 18 (b) showing the voltage change with time to the load. This RAMP model reproduces only the Tr / Tf time. For example, a time when the voltage amplitude changes from 20% to 80% is described at the rising edge, and a time when the voltage amplitude changes from 80% to 20% is described at the falling edge.

  On the other hand, another method is a model (Waveform model) that expresses characteristics obtained by measuring a waveform under a certain load condition. FIG. 19 shows the load circuit of this model, and FIG. 20 shows the voltage change when this circuit is used. The characteristic shown in FIG. 20 is a characteristic when the switching element rises, and a voltage change from the start to the end is described as intersection information corresponding to each time. The voltage change when the switching element falls is also described in the same manner.

  FIG. 21 shows an analysis method for performing analysis processing of the target circuit using the Waveform model. For example, the analysis target circuit information registered in the storage device 30 is read by the analysis target information reading unit 31 together with the IBIS usage condition information, and is sent to the analysis model generation unit 33 via the circuit information reading unit 32. On the other hand, the IBIS file 34 which is a Waveform model is read by the IBIS model reading unit 35 and sent to the analysis model generating unit 33.

The analysis model generation unit 33 applies the IBIS model to the analysis target circuit, generates an analysis model 36, performs circuit analysis by the circuit simulator 37, and obtains an analysis result 38.
Patent Document 1 is an invention of the above IBIS model creation method. In order to provide an IBIS model to a user in a short time, an IBIS model is prepared for all the circuits to be provided to the user, and a simulation is performed in advance. Thus, the IBIS model can be provided quickly, for example, to shorten the development time of a semiconductor device.

Further, Patent Document 2 is based on a description definition table that indicates a correspondence relationship between a description specification of an element model and a correction plan when deviating from the description specification in order to quickly and accurately check an element model and correct a defective portion. In this invention, the element model description rule check is performed, and if it deviates, the element model is corrected according to the above-mentioned correction plan, and the defective portion is quickly corrected and provided to the user.
JP 2006-323470 A JP 2002-245112 A

  In the circuit simulation performed by the conventional Waveform model, the following conditions are required to obtain a more accurate analysis result. That is, a. The termination voltage and termination resistance value of the termination circuit at the time of measurement are appropriate, b. The measurement plot interval is appropriate, c. The measurement conditions are different among a plurality of waveforms, and there is some difference in the waveforms; d. The absolute time on the time axis of waveform measurement is the same between different waveforms.

Many IBIS models are SPICE (Simulation Program with Integrated Circuit)
Emphasis) model is created by automatic conversion using a conversion program. ~ C. In many cases, this condition is not appropriate. On the other hand, in the IBIS model created from actual measurement, it is difficult to precisely match the time axis (the condition of the above d.), So that there is a problem that both time and voltage include measurement errors.

  For this reason, if analysis processing is performed using an IBIS model that does not meet the above conditions, the error of the switching characteristics of the transistor increases, the amplitude of the waveform obtained as a result of the analysis becomes abnormal, and ringing or A step occurs. For example, FIG. 22A shows an example of ringing, and a wave waveform is generated at the rising edge of the waveform. FIG. 2B shows an example in which a step is generated at the falling edge of the waveform.

  Therefore, the present invention calculates the switching characteristics of the switching means (transistor) from the voltage / current characteristics of the IBIS model, checks whether the calculated switching characteristics in the switching means (transistor) are correct, and calculates information on accuracy. An electronic circuit analyzer for performing the above is provided.

  According to the present invention, in the electronic circuit analyzer for performing circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected, according to the present invention, the waveform information is converted into the output element model. Means for creating a switching characteristic when the switching means included is changed, and the current value that flows when the state of the switching means changes is acceptable for the steady state current value of the switching means. An allowable current value setting means for setting a current value, a set allowable current value, the voltage / current characteristic, and a switching resistance of the switching means that does not exceed the set allowable current value from the value of the load resistance. A calculation means for calculating a range of values of the switching means, and the waveform information as a reference for calculating the switching characteristics of the switching means are displayed on the same time axis, and the switching means of the switching means is displayed. Characteristics can be achieved by providing an electronic circuit analyzing device having a display means for highlighting portions of the waveform information has become abnormal.

With this configuration, when performing circuit analysis using the IBIS model, erroneous circuit analysis can be prevented even when the measurement accuracy of the waveform information is low.
Further, the abnormality of the switching characteristic is also determined by setting a voltage value that is output when the state of the switching means changes to an allowable voltage value with respect to a steady-state voltage value of the switching means. In addition, by judging the abnormality of the switching characteristics and highlighting the abnormal part, it is possible to prevent erroneous circuit analysis when performing circuit analysis using the IBIS model.

  In addition, the switching characteristics are checked by calculating the derivative for the waveform information, the voltage accuracy guarantee range is set for the transient characteristics by sweeping the load resistance, and the upper limit value of the analysis frequency is checked. Thus, circuit analysis can be performed using an appropriate analysis frequency.

  According to the present invention, display is performed when there is an abnormality in the IBIS model. When performing circuit analysis using the IBIS model, the analyst can confirm this display and avoid performing incorrect circuit analysis. In addition, it is possible to perform circuit analysis using an appropriate load resistance and within a voltage accuracy guarantee range, and to perform circuit analysis using an appropriate analysis frequency.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram illustrating a configuration example of an electronic circuit analysis device according to the present embodiment.

  In this figure, the electronic circuit analysis device of this example is different from the conventional example (FIG. 21 described above) in that the transistor switching characteristic calculation unit, the switching characteristic storage unit, the switching characteristic check unit, and its check result storage unit, A configuration such as a display unit is added. That is, the analysis target circuit information registered in the storage device 1 is read by the analysis target information reading unit 2 together with the IBIS use condition information as described above, and transmitted to the analysis model generation unit 4 via the circuit information reading unit 3. Is done. On the other hand, the IBIS file 5 which is a Waveform model is read by the IBIS model reading unit 6 via the analysis target information reading unit 2 and transmitted to the analysis model generation unit 4.

  The IBIS file 5 read by the IBIS model reading unit 6 calculates switching characteristics (described later (KPU (T)) and (KPD (T))) by the transistor switching characteristic calculation unit 7. . Further, the switching characteristic information calculated by the switching characteristic calculation unit 7 is stored in the switching characteristic storage unit 8.

  The switching characteristic information stored in the switching characteristic storage unit 8 is further transmitted to the switching characteristic check unit 9. The switching characteristic check unit 9 checks switching characteristic information by a method described later, and stores the check result in the transistor switching characteristic check result storage unit 10. The check result is transmitted to the above-described analysis model generation unit 4 and is also transmitted to the transistor characteristic & abnormality location display unit 11.

  The analysis model generation unit 4 confirms the result of checking the switching characteristics of the transistors. If there is no problem with the check result, the analysis model 12 is generated, the target circuit is analyzed by the circuit simulator 13, and the analysis result 14 is displayed. Output.

  On the other hand, when an abnormality is detected in the switching characteristic of the transistor by the switching characteristic check unit 9, a display corresponding to the transistor characteristic & abnormality part display unit 11 is performed, and an erroneous analysis result can be output. It is avoided that a characteristic analysis process is performed.

  FIG. 2 is a diagram for explaining particularly the characteristic processing of the present invention in the electronic circuit analyzing apparatus configured as described above. First, the above-mentioned IBIS file is read (step (hereinafter referred to as S) 1), and transistor switching characteristics (KPU (T)) and (KPD (T)) are calculated (S2).

  Next, the setting value-specific processing for the limit values Klimit_min and Klimit_max is determined (S3). The limit values Klimit_min and Klimit_max are set by a current value, a voltage value, etc. as will be described later. For example, when the limit value is obtained from the allowable current value, the limit values Klimit_min and Klimit_max are calculated by the process (S4). Further, when the limit value is obtained from the allowable voltage value, the calculation is performed by the process (S5). Furthermore, when setting directly, a setting value is read by a process (S6).

  Next, it is checked whether the aforementioned switching characteristics (KPU (T)) and (KPD (T)) are between the limit values determined based on the above settings (Klimit_min to Klimit_max) (S7), A check result is obtained (S8).

  Next, the switching characteristics (KPU (T)) and (KPD (T)) of the transistor are checked by calculating a differential coefficient, which will be described later, and a check result is obtained (S10). Further, an OS (overshoot) / US (undershoot) voltage accuracy guarantee range is determined by a load characteristic sweep described later (S11), and an OS / US voltage accuracy guarantee range is set (S12). Furthermore, an upper limit check of the analysis frequency described later is performed (S13), and an upper limit value of the analysis frequency is set (S14). Each of the above processes will be described in an embodiment described later.

  First, in the description of the first embodiment, an example in which the limit values Klimit_min and Klimit_max are obtained from the allowable current values (S4) and the transistor switching characteristics (KPU (T)) and (KPD (T)) are checked will be described. To do. An example in which the limit value is obtained from the allowable voltage value (S5) and the transistor switching characteristics (KPU (T)) and (KPD (T)) are checked will be described in the second embodiment.

  FIG. 3 is a diagram for explaining the IBIS model of this example. FIG. 3A shows a schematic configuration of an output circuit (LSI) and output pins, and FIG. 3B shows an equivalent circuit thereof. The equivalent circuit shown in FIG. 2B is composed of a pull-up side transistor TrU and a pull-down side transistor TrD, a power clamp D1, a ground clamp D2, a capacitor C, an inductance element Lpkg, a capacitance element Cpkg, and a resistance element Rpkg. ing.

  FIG. 4 is a circuit for further explaining transistor switching characteristics (KPU (T)) and (KPD (T)). (KPU (T)) indicates the switching characteristic of the pull-up side transistor, and (KPD (T)) indicates the switching characteristic of the pull-down side transistor. The on / off states of the pull-up side and pull-down side transistor elements are shown as follows. That is, the switching characteristic when the pull-up transistor is on is indicated by (KPU_ON (T)), the switching characteristic when it is off is indicated by (KPU_OFF (T)), and the switching characteristic when the pull-down transistor is on The characteristic is indicated by (KPD_ON (T)), and the switching characteristic when OFF is indicated by (KPD_OFF (T)).

  FIG. 5 shows a Waveform waveform provided as an IBIS model, which is provided in three waveforms: a steady waveform (Typ), a maximum waveform (Max), and a minimum waveform (Min). Based on this information, the analyst calculates the rise and fall characteristics of the transistor and checks the switching characteristics.

As described above, in this example, the limit values Klimit_min and Klimit_max are set based on the allowable current value, and an abnormality in the switching characteristics of the transistor is determined based on whether or not the limit value (threshold value) is exceeded.

  FIG. 6 shows the switching characteristics of the pull-up side transistor. Upper and lower thresholds are set at the time of switching, and it is determined whether or not the transistor switching characteristics fall within this threshold. . That is, as shown in the figure, an upper limit value Klimit_max and a lower limit value Klimit_min are set as threshold values. For example, when the transistor is turned on (off → on), it is checked whether the upper limit value Klimit_max is exceeded, and the transistor is turned off. Check whether the lower limit value Klimit_min is exceeded (ON → OFF).

  FIG. 7 is a diagram for specifically explaining this example, and the values of Klimit_max and Klimit_min are determined by specifying an allowable current value. In the figure, a characteristic (curve) α is a voltage-current characteristic in a steady state (hereinafter referred to as a VI characteristic) when the pull-up side transistor is on. A characteristic (straight line) β is a load straight line of the termination circuit.

  Here, a variable for setting an allowable value of current in the transient characteristic is defined. For example, the output current of H that is the intersection of the VI characteristic α and the load straight line β in the steady state is defined as I (H), and any amount of current may flow with respect to the output current I (H). The allowable margin is Imargin low shown in the figure. Similarly, let Imargin high be an allowable margin for how much current may flow with respect to the output current I (L) of L in a steady state.

  Next, a point on the load straight line β, which is a current value with the margin added, is calculated to obtain points B and b. That is, an intersection B between the current value lower limit line L1 obtained by adding a margin (Imargin low) to the steady state H and the load straight line β is obtained. Next, the point A is obtained on the steady state VI characteristic α at the same voltage as the point B. Then, the VI characteristic α1 passing through the point B is calculated by PU_VI (Vout) × (B / A). Similarly, an intersection b between the current value upper limit line L2 obtained by adding a margin (Imargin high) to the steady state L and the load straight line β is obtained. Next, a point on the steady state VI characteristic α having the same voltage as the point b is obtained. Then, the VI characteristic α2 passing through the point b is calculated by PU_VI (Vout) × (b / a).

  Here, the point A of the V-I characteristic α in the steady state is a current value that does not exceed the margin of transient characteristics when the transistor is turned on, and the point a exceeds the margin of transient characteristics when the transistor is turned off. It is the current value of the last minute.

  Therefore, Klimit_max = (current value at point B / current value at point A) and Klimit_min = (current value at point b / current value at point a), and the switching characteristics of the pull-up side transistor ( By checking whether KPU (T)) is between Klimit_min and Klimit_max, the switching characteristic of the pull-up side transistor can be controlled so as not to exceed the threshold value.

In the above description, the pull-up side transistor has been described, but the pull-down side transistor can be similarly processed.
FIG. 8 is a diagram showing a display method when it is determined that the switching characteristic of the transistor exceeds the threshold value and is abnormal by the above processing. In this case, the abnormal part of the switching characteristic (KPU (T)) can be displayed by adding a color to the abnormal part or adding a circle to the switching characteristic (KPU (T)). . In the figure, the pull-up side is explained, but the abnormal part of the switching characteristics (KPD (T)) is displayed by adding a color to the abnormal part or adding a circle on the pull-down side as well. Can do.

FIG. 9 shows a display in which a color is added at the time when an abnormal part exists in the waveform of the output voltage. With this configuration as well, abnormal portions of the switching characteristics (KPU (T)) and (KPD (T)) can be found.

  As described above, when an analyst performs an analysis using an IBIS model, the analysis result waveform could not be known conventionally. However, according to this example, when the analysis result has an abnormality, 8 and 9, abnormalities are displayed on the display, switching characteristics (KPU (T)), (KPD (T)) are abnormal, and it is inappropriate to use the IBIS model You can easily know that.

(Embodiment 2)
Next, Embodiment 2 of the present invention will be described.
Also in this example, as shown in FIG. 6 described above, the upper limit value Klimit_max and the lower limit value Klimit_min are set as thresholds, and when the transistor is turned on (off → on), between the lower limit value Klimit_min and the upper limit value Klimit_max Check if there is any. Similarly, when the transistor is turned off (from ON to OFF), it is checked whether it is between the lower limit value Klimit_min and the upper limit value Klimit_max. In this example, an allowable voltage value is specified and the Klimit_max and Klimit_min criteria are used. It is what.

  FIG. 10 is a diagram for explaining this example, and, as described above, the characteristic (curve) α is a VI characteristic indicating the steady state of the pull-up transistor, and the characteristic (straight line) β is the load of the termination circuit. It is a straight line.

  In this example, a variable for setting an allowable voltage in the transient characteristic is defined instead of the above-described current. That is, the output voltage of H, which is the intersection of the VI characteristic α and the load line β in the steady state, is defined as Vout (H), and how much margin is allowed with respect to the output voltage Vout (H). Set. For example, in this example, the allowable margin is Vout (H) × Vmargin high. Similarly, the output voltage of L in a steady state is Vout (L), and in this example, a margin of Vout (L) × Vmargin low is allowed for this output voltage Vout (L).

  Next, a point on the load straight line β that is a voltage value to which the margin is added is calculated, and points B and b are obtained. In this example, the allowable voltage line obtained by adding a margin (Vout (H) × Vmargin high) to the steady state H is L3. Next, a point on the steady-state VI characteristic α having the same voltage as the point B is obtained. That is, point A having the same voltage as point B and point a having the same voltage as point b are obtained. An intersection B between the line L3 and the load straight line β is obtained. Then, the VI characteristic α3 passing through the point B is calculated by PU_VI (Vout) × (B / A). Similarly, for the point b, the allowable voltage line obtained by adding a margin (Vout (L) × Vmargin low) to the steady state L is L4, and the intersection b between the line L4 and the load straight line β is obtained. Then, the VI characteristic α4 passing through the point b is calculated by PU_VI (Vout) × (b / a).

  Here, the point A of the VI characteristic α in the steady state is a marginal value not exceeding the transient characteristic margin (Vout (H) × Vmargin high) when the transistor is turned on, and the point a is the transistor turned off. This is a marginal value not exceeding the margin (Vout (L) × Vmargin low) of the transient characteristics.

  Therefore, also in this example, Klimit_max = (current value at point B / current value at point A), Klimit_min = (current value at point b / current value at point a), and the transistor on the pull-up side By checking whether the switching characteristic (KPU (T)) is between Klimit_min and Klimit_max, the switching characteristic of the pull-up transistor can be controlled so as not to exceed the threshold value.

In the above description, the pull-up side transistor has been described, but the pull-down side transistor can be similarly processed.
Further, when it is determined that the switching characteristics of the transistor are abnormal by the above processing, the switching characteristics are added by adding a color or adding a circle as shown in FIG. 8 as described above. The abnormal part of (KPU (T)) and (KPD (T)) can be displayed. Moreover, as shown in FIG. 9, you may make it display the abnormal location of a waveform.

  As described above, in this example as well, when an analyst performs an analysis using an IBIS model, the analysis result waveform could not be known in the past. 8 and 9 above, abnormalities are displayed on the display, switching characteristics (KPU (T)), (KPD (T)) are abnormal, and the IBIS model should be used. Can easily know that is not appropriate.

  Note that FIG. 11 shows an example in which the characteristics of the pull-up transistor have characteristics close to a constant current characteristic, and the switching characteristics (KPU (T)), (KPD (T)) are performed by performing the same processing as described above. ) Can be known. That is, the aforementioned H output voltage, which is the intersection of the VI characteristic α and the load straight line β in the steady state, is Vout (H), and the margin allowed for this output voltage Vout (H) is Vout (H) × Vmargin high. Similarly, the output voltage of L in a steady state is Vout (L), and in this example, a margin of Vout (L) × Vmargin low is allowed for this output voltage Vout (L).

  Next, a point on the load straight line β that is a voltage value to which the margin is added is calculated, and points B and b are obtained. In this example, the allowable voltage line obtained by adding a margin (Vout (H) × Vmargin high) to the steady state H is L5, and the intersection B between the corresponding VI characteristic α5 and the load straight line β is obtained. . Similarly, for the point b, the allowable voltage line obtained by adding a margin (Vout (L) × Vmargin low) to the steady state L is L6, and the corresponding VI characteristic α6 is calculated. The intersection b between the −I characteristic α6 and the load straight line β is obtained.

  Next, as described above, points A and a, which are points on the steady-state VI characteristic α at which the voltage is the same as point B, are obtained. Similarly to the above, Klimit_max = (current value at point A / current value at point B), Klimit_min = (current value at point a / current value at point b), and the pull-up side transistor By checking whether the switching characteristic (KPU (T)) is between Klimit_min and Klimit_max, the switching characteristic of the pull-up side transistor can be controlled so as not to exceed the threshold value.

In the above description, the pull-up side transistor has been described. However, the pull-down side transistor can be similarly implemented.
Further, when it is determined that the switching characteristics of the transistor are abnormal by the above processing, as described above, a color or the like is added to the abnormal portion as shown in FIG. 8 or 9, and the switching characteristics (KPU (T )), (KPD (T)) is configured to display an error.

(Embodiment 3)
Next, a third embodiment of the present invention will be described.
In this example, the load resistance range that ensures the voltage accuracy is determined by sweeping the load resistance. This will be specifically described below.

The amount of error included in the switching characteristics (KPU (T)) and (KPD (T)) varies depending on the load resistance at the time of measurement. For example, when the transient characteristic of the IBIS model is measured with a large load resistance connected, the amount of current flowing through the load resistance is small. In this case, since the switching characteristics (KPU (T)) and (KPD (T)) are defined by the ratio of the steady-state VI characteristics and the transient VI characteristics, the resistance value flowing through the load resistance is small. Switching characteristics (KPU (T)), (KPD
The value of (T) changes greatly when the current value changes slightly, and the error increases. On the other hand, when the load resistance is extremely smaller than the output resistance of the driver element, a large current difference is required to slightly change the voltage, resulting in a large error. Therefore, it is an accurate measurement condition of the switching characteristics (KPU (T)) and (KPD (T)) to measure within a range in which the output resistance value of the driver element and the load resistance value do not greatly differ.

  However, the actually provided IBIS model is created under various conditions. When the analysis is performed under a load condition that is significantly different from the measurement condition of the transient characteristic of the IBIS model, the switching characteristic (KPU (T )), (KPD (T)) errors greatly affect the analysis accuracy.

  In particular, when the switching characteristics (KPU (T)) and (KPD (T)) have large values, the voltage becomes an abnormally large voltage that cannot actually occur. Therefore, in this example, the OS (overshoot) voltage and US (undershoot) generated when the load resistance is changed using the switching characteristics (KPU (T)) and (KPD (T)) obtained from the IBIS model. ) Obtain the voltage and check whether the OS voltage and the US voltage are not too large with respect to the amplitude depending on the connected load.

  The following is an example of amplitude output by the pull-up side transistor when the load resistance is changed at 0V termination. FIG. 12 is a diagram illustrating this embodiment. As described above, in this example, the load resistance is swept, and the OS voltage of Vout when the load is changed is calculated from the switching characteristics (KPU (T)).

  In the figure, α indicates the switching characteristics of the transistor on the pull-up side in the steady state. Also, β represents a load straight line (load resistance), and in this example, four load straight lines β1, β2, β3, and β4 are illustrated in order to sweep the load resistance. Here, Vamp indicated by a one-dot chain double arrow indicates an output (amplitude) when the load resistance is changed in a steady state. For example, when the load line is β1, the amplitude is Vamp1, when the load line is β2, the amplitude is Vamp2, when the load line is β3, the amplitude is Vamp3, and when the load line is β4, the amplitude is Vamp4.

  Next, in order to set the guaranteed range of the load resistance so that the OS voltage does not become too large with respect to the amplitude, the V-I characteristic α1 is used as the maximum value KMAX of the switching characteristic acquired in the above-described embodiment. Then, the OS voltage from the steady voltage that satisfies the maximum value KMAX when the load resistance is changed is obtained as VOSmargin. Specifically, solid line double arrows VOSmargin 1 to 4 shown in the figure correspond to each other, calculate a ratio of margin to amplitude (VOSmargin / Vamp), and check whether this value is within a certain range. If the margin ratio (VOSmargin / Vamp) is within a certain range, it is understood that the IBIS model can be analyzed.

  As described above, according to the present example, the margin ratio (VOSmargin / Vamp) is calculated by sweeping the load resistance, and the IBIS model can be used regardless of the load condition as long as the margin ratio (VOSmargin / Vamp) is within a predetermined range. Can be used. If it does not fall within the range under some load conditions, the connected load is calculated from the operating state of the driver element at the time of analysis execution, and the calculated load is within the accuracy range obtained by the previously obtained sweep It is possible to determine whether the analysis is accurate by checking whether it is within the range.

  FIG. 13 illustrates a method for setting the load resistance when the load resistance is changed. In this example, the maximum allowable current of the transistor element is Imax, and this maximum allowable current Imax is divided by an arbitrary numerical value. In this example, an example of dividing into four is shown.

In this case, the intersection of the characteristics of the current value divided into four and the maximum value KMAX × PU_VI (Vout) is obtained. For example, in the above example, the intersection with β1 is R1, the intersection with β2 is R2, and β3
The intersection with R4 is R3, and the intersection with β4 is R4. The number of divisions is not limited to the above four.

  FIG. 14 is a diagram for explaining a method of determining the US voltage accuracy guarantee range by the load resistance sweep. Also in this example, in order to sweep the load resistance, four load lines β1, β2, β3, and β4 are illustrated, and Vamp indicated by a one-dot chain double arrow indicates an output when the load resistance is changed in a steady state. (Amplitude) is shown. For example, when the load line is β1, the amplitude is Vamp1, when the load line is β2, the amplitude is Vamp2, when the load line is β3, the amplitude is Vamp3, and when the load line is β4, the amplitude is Vamp4. Further, in order to set a guaranteed range in which the switching characteristic does not become an abnormal value, the minimum value KMIN of the switching characteristic obtained in the above embodiment is used, and the steady voltage that satisfies the minimum value KMIN when the load resistance is changed The US voltage from is acquired as VUSmargin. Specifically, the solid line double arrows VUSmargin 1 to 4 shown in the figure correspond to each other, calculate the ratio of the margin to the amplitude (VUSmargin / Vamp), check whether this value is within a certain range, and check the margin ratio. If (VUSmargin / Vamp) is within a certain range, it is determined that the IBIS model can be analyzed.

  As described above, also in this example, the margin ratio (VUSmargin / Vamp) is calculated by sweeping the load resistance, and the IBIS model can be used regardless of the load condition as long as it is within a predetermined range. To be able to use.

(Embodiment 4)
Next, a fourth embodiment of the present invention will be described.
In this example, it is determined whether or not the switching characteristic (KPU (T)) of the transistor is normal from the differential value of the waveform. This will be specifically described below.

  FIG. 15 is a diagram for explaining the processing of this example. FIG. 15A shows the case where the switching characteristic (KPU (T)) is normal, and FIG. 15B and FIG. This shows the case where the wing characteristics (KPU (T)) are abnormal. That is, as shown in the figure, by differentiating the rising waveform, if normal, the differential coefficient changes only once from increase to decrease. However, in the case of abnormality, as shown in FIG. 5B, the differential coefficient increases, decreases, increases, and decreases. Further, as shown in FIG. 5C, the differential coefficient is increased → decreased → repeatedly.

  Therefore, it is determined whether the switching characteristic (KPU (T)) of the transistor is normal or abnormal by obtaining the differential coefficient of the rising waveform during the transient characteristic. As described above, according to this example, it is possible to determine whether the switching characteristic (KPU (T)) is normal or abnormal by obtaining the differential coefficient of the rising waveform at the time of the transient characteristic. However, according to this example, when there is an abnormality in the analysis result, it is possible to easily know the abnormality of the switching characteristic (KPU (T)).

  In the above description, the rise of the pull-up side transistor has been described. However, regarding the fall, an abnormality in the switching characteristic (KPU (T)) can also be known. In the above description, the transistor on the pull-up side has been described, but the same processing can be performed on the transistor on the pull-down side.

(Embodiment 5)
Next, a fifth embodiment of the present invention will be described.
In this example, the upper limit of the analysis frequency is checked by specifying a voltage tolerance. This will be specifically described below.

Since the IBIS model expresses its operation as a behavior, the accuracy varies depending on the analysis frequency. For example, if the next pulse is input before the analysis frequency is increased and the transistor switching state is stabilized to a steady state, it is estimated from the VI characteristics defined in the IBIS model and the transistor switching characteristics. The next switching operation starts from the VI characteristic. As described above, when switching is performed using the estimated characteristics as the starting point, the VI characteristic information serving as the starting point at the time of switching is not accurate, so that the accuracy of the subsequent analysis result waveform decreases.

  Therefore, in this example, the upper limit of the analysis frequency that satisfies the error is obtained by giving a voltage allowable error indicating how much the state before the switching process is completed on the voltage axis.

  FIG. 16 is a diagram for explaining this example, and α is the steady-state VI characteristic when the pull-up transistor is on, and the characteristic (straight line) β is the load line of the termination circuit. is there. In this example, the range of the switching characteristic (KPU (T)) value for satisfying the allowable error is, for example, Kpusw_min to Kpusw_max, and is obtained by the following calculation. That is, Kpusw_max = current value at A / current value at point B, Kpusw_min = current value at point a / current value at point b, and at the rise of the waveform, Switching operation is possible.

The meanings of H point, L point, B point, b point, A point, a point, calculation method, and the like shown in the figure are the same as those in the first and second embodiments. In the above description, the transistor on the pull-up side has been described, but the same can be applied to the transistor on the pull-down side.
FIG. 17 is a diagram illustrating the switching time SW_TIME. (A) shows the SW_TIME timing with respect to the rising switching characteristic (KPU (T)) of the pull-up side transistor, and (b) shows the rising switching characteristic (KPU (T) of the pull-down side transistor. SW_TIME timing for)). FIG. 4C shows the SW_TIME timing with respect to the falling switching characteristic (KPU (T)) of the pull-up transistor, and FIG. 4D shows the switching characteristic of the pull-down transistor falling. SW_TIME timing for (KPU (T)).

  In this example, the upper limit is set to 1 / (2 × SW_TIME), for example, as an analysis frequency that can be processed without causing malfunctions with respect to the above four patterns, and the analysis frequency does not exceed the upper limit frequency obtained during analysis execution. To check. Thus, control is performed so that the previous switching operation is not completed before entering the next switching operation.

(Appendix 1)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
Creation means for creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
A power value setting unit that sets an allowable power value for a power value in a steady state of the switching unit as a power value that flows when the state of the switching unit changes.
Calculating means for calculating a range of the switching characteristic value of the switching means not exceeding the set allowable power value from the set allowable power value, the voltage / current characteristic, and the load resistance value;
Display means for displaying on the same time axis as the waveform information used as a reference for calculating the switching characteristics of the switching means, and for highlighting a portion on the waveform characteristics where the switching characteristics of the switching means are abnormal When,
An electronic circuit analysis device comprising:
(Appendix 2)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A current value setting means for setting a current value allowed for a steady state of the switching means as a current value that flows when the switching means included in the output element model is turned on and off; and
Analyzing means for performing a simulation based on the setting and performing circuit analysis,
In the analysis result, it is confirmed that the current value is within the range of the allowable current value, and a determination unit that determines whether the switching characteristic of the switching unit is normal;
An electronic circuit analysis device comprising:
(Appendix 3)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
Creation means for creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
A voltage value setting means for setting a voltage value output when the state of the switching means is changed to an allowable voltage value with respect to a steady state of the switching means;
Calculating means for calculating a range of the switching characteristic value of the switching means not exceeding the set allowable voltage value from the set allowable voltage value, the voltage / current characteristic, and the load resistance value;
Display means for displaying on the same time axis as the waveform information used as a reference for calculating the switching characteristics of the switching means, and for highlighting a portion on the waveform characteristics where the switching characteristics of the switching means are abnormal When,
An electronic circuit analysis device comprising:
(Appendix 4)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A voltage value setting means for setting an output voltage value generated when the switching means included in the output element model is turned on and off to change an allowable voltage value with respect to a steady state of the switching means;
Analyzing means for performing a simulation based on the setting and performing circuit analysis,
In the analysis result, it is confirmed that the voltage value is within the range of the allowable voltage value, and a determination unit that determines whether the switching characteristic of the switching unit is normal;
An electronic circuit analysis device comprising:
(Appendix 5)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
Creation means for creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
Calculating means for calculating a differential coefficient of the switching characteristics of the switching means;
A determination means for counting the number of times the differential coefficient, which is the calculation result, changes from increasing to decreasing, and determining an abnormality of the switching characteristics based on the counting result;
An electronic circuit analysis device comprising:
(Appendix 6)
6. The electronic circuit analysis apparatus according to appendix 5, wherein the determination unit determines that the switching characteristic is abnormal when the counting result is 2 or more.
(Appendix 7)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
Creation means for creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
Checking means for calculating a time during which the switching characteristic of the switching means changes within a constant value range, and confirming that the circuit analysis is performed using a frequency having a period twice as long as the calculated time; ,
A determination means for determining that the analysis frequency is within a guaranteed range when a circuit analysis is performed using a frequency that is less than half of the calculated time;
An electronic circuit analysis device comprising:
(Appendix 8)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
Creation means for creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
Checking means for calculating a time during which the switching characteristic of the switching means changes within a range of a constant value, and confirming that the switching means is not changing the on / off state at an interval shorter than the calculated time; ,
A determination means for determining that the switching means is within an analysis accuracy guarantee range when the switching means is not changing the ON / OFF state at an interval shorter than the calculated time;
An electronic circuit analysis device comprising:
(Appendix 9)
In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
Creation means for creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
Using the maximum and minimum values of the switching characteristics of the switching means and the voltage / current characteristics, a calculation means for calculating an overshoot voltage generated when the load resistance is changed, and an undershoot voltage;
A determination means for determining whether the overshoot voltage and the undershoot voltage are within an allowable range, and determining that the switching characteristic is normal when the overshoot voltage is within the allowable range;
An electronic circuit analysis device comprising:
(Appendix 10)
In the electronic circuit analysis method that inputs the voltage / current characteristics and waveform information of the output element model to which the load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
A process of setting an allowable current value that is acceptable for a current value that flows when the state of the switching unit changes in the steady state of the switching unit;
A process for calculating a range of the switching characteristic value of the switching means that does not exceed the set allowable current value from the set allowable current value, the voltage / current characteristic, and the load resistance value;
Processing for displaying on the same time axis as the waveform information that is a reference for calculating the switching characteristics of the switching means, and highlighting a portion on the waveform characteristics where the switching characteristics of the switching means are abnormal; ,
An electronic circuit analysis method comprising:
(Appendix 11)
In the electronic circuit analysis method that inputs the voltage / current characteristics and waveform characteristics of the output element model to which the load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
A process for setting a voltage value output when the state of the switching unit is changed to an allowable voltage value for a steady state of the switching unit;
A process of calculating a range of the switching characteristic value of the switching means that does not exceed the set allowable voltage value from the set allowable voltage value, the voltage / current characteristic, and the load resistance value;
Processing for displaying on the same time axis as the waveform information that is a reference for calculating the switching characteristics of the switching means, and highlighting a portion on the waveform characteristics where the switching characteristics of the switching means are abnormal; ,
An electronic circuit analysis method comprising:
(Appendix 12)
In the electronic circuit analysis method that inputs the voltage / current characteristics and waveform information of the output element model to which the load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
Processing for calculating a differential coefficient of the switching characteristics of the switching means;
A process of counting the number of times the differential coefficient, which is the calculation result, changes from increasing to decreasing, and determining abnormality of the switching characteristics based on the counting result;
An electronic circuit analysis method comprising:
(Appendix 13)
In the electronic circuit analysis method that inputs the voltage / current characteristics and waveform information of the output element model to which the load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
Calculate the time for which the switching characteristic of the switching means changes within a certain value range, and confirm that the circuit analysis is performed using a frequency equal to or lower than the frequency having a period twice the calculated time. Processing,
When circuit analysis is performed using a frequency equal to or lower than a frequency having a cycle twice the calculated time, a process of determining that the frequency is within the analysis frequency guarantee range;
An electronic circuit analysis method comprising:
(Appendix 14)
In the electronic circuit analysis method that inputs the voltage / current characteristics and waveform information of the output element model to which the load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
A process for calculating a time during which the switching characteristic of the switching means changes within a range of a constant value, and confirming that the switching means is not changing the on / off state at an interval shorter than the calculated time;
A process for determining that the switching means is in the analysis accuracy guarantee range when the switching means is not changing the ON / OFF state at an interval shorter than the calculated time;
An electronic circuit analysis method comprising:
(Appendix 15)
In the electronic circuit analysis method that inputs the voltage / current characteristics and waveform information of the output element model to which the load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
Using the maximum and minimum values of the switching characteristics of the switching means and the voltage / current characteristics, a process of calculating an overshoot voltage and an undershoot voltage generated when the load resistance is changed,
Determining whether the overshoot voltage and the undershoot voltage are within an allowable range, and if within the allowable range, determining that the switching characteristics are normal;
An electronic circuit analysis method comprising:
(Appendix 16)
A program used for an electronic circuit analysis device for inputting a voltage / current characteristic and waveform information of an output element model to which a load resistance is connected, and performing circuit analysis,
A process of creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
A process of setting an allowable current value that is acceptable for a current value that flows when the state of the switching unit changes in the steady state of the switching unit;
A process for calculating a range of the switching characteristic value of the switching means that does not exceed the set allowable current value from the set allowable current value, the voltage / current characteristic, and the load resistance value;
Processing for displaying on the same time axis as the waveform information that is a reference for calculating the switching characteristics of the switching means, and highlighting a portion on the waveform characteristics where the switching characteristics of the switching means are abnormal; ,
For causing the electronic circuit analysis apparatus to execute the program.
(Appendix 17)
A program used in an electronic circuit analysis device that inputs a voltage / current characteristic and a waveform characteristic of an output element model to which a load resistance is connected, and performs circuit analysis,
A process of creating switching characteristics at the time of on / off state change of the switching means included in the output element model from the waveform information;
A process for setting a voltage value that is output when the state of the switching unit is changed to an allowable voltage value for a steady state of the switching unit;
Processing for calculating a range of the switching characteristic value of the switching means not exceeding the set allowable voltage value from the set allowable voltage value, the voltage / current characteristic, and the load resistance value;
Processing for displaying on the same time axis as the waveform information that is a reference for calculating the switching characteristics of the switching means, and highlighting a portion on the waveform characteristics where the switching characteristics of the switching means are abnormal; ,
For causing the electronic circuit analysis apparatus to execute the program.

It is a figure explaining the process of the electronic circuit analyzer of this embodiment. It is a figure explaining the characteristic process of this invention especially in an electronic circuit analyzer. It is a figure explaining an IBIS model, (a) shows schematic structure of an output circuit (LSI) and an output pin, (b) is a figure which shows the equivalent circuit. It is an equivalent circuit diagram which reproduces a Waveform model. It is a figure which shows a Waveform waveform and demonstrates three waveforms, a steady waveform (Typ), a maximum waveform (Max), and a minimum waveform (Min). It is a figure explaining the threshold value of the upper limit of the switching characteristic of the transistor of a pullup side, and a minimum. It is a figure explaining Embodiment 1 concretely. It is a figure which shows the display method when it is judged that the switching characteristic of a transistor exceeds the said threshold value and is abnormal. It is a figure which shows the example of a display which adds a color at the time when the abnormal location exists in the waveform of an output voltage. FIG. 5 is a diagram for explaining a second embodiment. It is a figure explaining the example in case the characteristic of the transistor of a pullup side has a characteristic close | similar to a constant current characteristic. It is a figure explaining Embodiment 3, and is a figure explaining the determination method of the OS voltage accuracy guarantee range by load resistance sweep. It is a figure explaining the setting method of load resistance, when changing load resistance. It is a figure explaining Embodiment 3, and is a figure explaining the determination method of the US voltage accuracy guarantee range by load resistance sweep. FIG. 10 is a diagram for explaining the processing of the fourth embodiment, (a) is a diagram showing a case where the switching characteristics (KPU (T)) are normal, and (b) and (c) are the switching characteristics (KPU ( It is a figure which shows the case where T)) is abnormal. It is a figure explaining the process of Embodiment 5. FIG. (A) is a timing indicating the time SW_TIME with respect to the rising switching characteristic (KPU (T)) of the pull-up transistor, and (b) is the switching characteristic (KPU (T)) of the pull-down transistor rising. (C) is a timing indicating the time SW_TIME with respect to the switching characteristic (KPU (T)) of the fall of the pull-up side transistor, and (d) is a timing indicating the time SW_TIME of the pull-down side transistor. It is a figure which shows the timing which shows time SW_TIME with respect to the falling switching characteristic (KPU (T)). (A) shows a circuit diagram of the IBIS model, and (b) shows a voltage change with respect to the time. It is a figure which shows the load circuit of an IBIS model. It is a figure which shows the voltage change at the time of using the circuit of FIG. It is a figure which shows the analysis method which performs the analysis process of a target circuit using a Waveform model. (A) is an example of ringing generated in the switching characteristics of the transistor, and is a diagram showing an example in which a wave waveform is generated at the rising portion of KPU (T), and (b) is a diagram of the transistor with ringing of (a). It is a figure which shows the example which the level | step difference which should not exist originally in a falling waveform depending on load conditions arises as a result of switching characteristics.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory | storage device 2 Analysis object information reading part 3 Circuit information reading part 4 Analysis model production | generation part 5 IBIS file 6 IBIS model reading part 7 Transistor switching characteristic calculation part 8 Transistor switching characteristic memory | storage part 9 Transistor switching characteristic check Unit 10 Transistor switching characteristic check result storage unit 11 Transistor characteristic & abnormality location display unit 12 Analysis model generation 13 Circuit simulator 14 Analysis result

Claims (5)

In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A creation unit that creates switching characteristics at the time of on / off state change of the switching unit included in the output element model from the waveform information;
An allowable power value setting unit that sets an allowable power value that allows an electric power value that flows when the state of the switching unit changes in a steady state of the switching unit;
A calculation unit that calculates a range of the switching characteristic value of the switching unit that does not exceed the set allowable power value from the set allowable power value, the voltage / current characteristic, and the load resistance value; ,
A display unit that displays on the same time axis as the waveform information that is a reference for calculating the switching characteristic of the switching unit, and that highlights a portion on the waveform information in which the switching characteristic of the switching unit is abnormal When,
An electronic circuit analysis device comprising: In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A voltage value setting unit that sets an output voltage value that is generated when the switching unit included in the output element model is turned on and off, and an allowable voltage value for a steady state of the switching unit, and
An analysis unit that performs simulation based on the setting and performs circuit analysis;
In the analysis results, a determination unit that confirms that the voltage value is within the range of the allowable voltage value, and determines whether the switching characteristics of the switching unit are normal;
An electronic circuit analysis device comprising: In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A creation unit that creates switching characteristics at the time of on / off state change of the switching unit included in the output element model from the waveform information;
A calculation unit for calculating a differential coefficient of the switching characteristics of the switching unit;
A determination unit that counts the number of times the differential coefficient that is the calculation result changes from increase to decrease, and determines an abnormality of the switching characteristics based on the count result;
An electronic circuit analysis device comprising: In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A creation unit that creates switching characteristics at the time of on / off state change of the switching unit included in the output element model from the waveform information;
Using the maximum and minimum values of the switching characteristics of the switching means and the voltage / current characteristics, a calculation unit that calculates an overshoot voltage generated when the load resistance is changed, and an undershoot voltage;
A determination unit that determines whether the overshoot voltage and the undershoot voltage are within an allowable range, and determines that the switching characteristic is normal when the overshoot voltage is within the allowable range;
An electronic circuit analysis device comprising: In an electronic circuit analyzer that performs circuit analysis by inputting voltage / current characteristics and waveform information of an output element model to which a load resistor is connected.
A creation unit for creating switching characteristics at the time of on / off state change of switching means included in the output element model from the waveform information;
A check unit for calculating a time during which the switching characteristic of the switching unit changes within a certain value range, and confirming that the circuit analysis is performed using a frequency having a period twice as long as the calculated time; ,
A determination unit that determines that the frequency is within the analysis frequency guarantee range when the circuit analysis is performed using a frequency that is 1/2 or less of the calculated time;
An electronic circuit analysis device comprising: