JP4684961B2 - Test signal verification device - Google Patents

Description

  The present invention relates to a test signal verification apparatus that verifies whether or not a measurement object satisfies a standard.

As a conventional test signal verification device, a signal to be tested transmitted by a measurement object is identified as a transition bit and a non-transition bit, and each waveform and an eye mask corresponding to the standard are displayed to display the measurement object. Is known that allows the user to determine whether or not the product satisfies the standard (for example, see Non-Patent Document 1).
"PCI Express Overview, Evaluation, Measurement-Agilent Technologies", [online], [Search July 10, 2006], Internet <URL: http://jp.tm.agilent.com/tmo/mibu/adf /applications/pciexpress/pciexpress.shtml>

  However, in the conventional test signal verification apparatus, when the bit error rate of the signal under test is low, the display luminance is low for the measurement value that causes the error that is infrequent in the eye diagram disclosed in Non-Patent Document 1. For this reason, there is a problem that the user cannot accurately determine whether or not the measurement object satisfies the standard from the display result.

  The present invention has been made to solve the conventional problems, and supports accurate determination of whether or not a measurement object satisfies a standard even when the bit error rate of a signal under test is low. An object of the present invention is to provide a test signal verification apparatus capable of performing the above.

  The test signal verification apparatus of the present invention receives a signal under test transmitted by a measurement object that has received a test signal composed of transition bits and non-transition bits, and displays an eye diagram for each bit error rate on a display unit. A test signal verifying device, wherein a coding unit that codes the signal under test based on a set threshold and a phase of a clock signal, and a phase that shifts the phase of the clock signal input to the coding unit A shift unit, a shift amount setting unit for setting a shift amount in the phase shift unit, a threshold value setting unit for setting the threshold value in the encoding unit, and a transition bit in a reference pattern corresponding to the pattern of the signal under test And the position of the non-transition bit, and the bit error rate of the signal under test is measured for each bit transition. A bit error rate measuring unit, and the shift amount setting unit obtains two shift amounts at which a bit error rate of a transition bit at a preset threshold value becomes a first error rate and an average value thereof At the same time, for the transition bit, when the second error rate to be displayed in the eye diagram is different from the first error rate, the shift in which the bit error rate at the preset threshold becomes the second error rate. For the non-transition bits, the shift amount at which the bit error rate at the preset threshold value becomes the second error rate is determined, and the threshold value setting unit is configured such that the shift amount is the average value. By determining the threshold value at which the bit error rate becomes the second error rate, the eye diagram of the second error rate can be obtained with the presence of bit transition of the reference pattern. It has a structure to be displayed for each.

  With this configuration, the test signal verification apparatus of the present invention obtains the shift amount at which the bit error rate at the preset threshold value becomes the second error rate, and the bit error rate of the transition bit at the threshold value at which the shift amount is preset is By obtaining a threshold value at which the bit error rate becomes the second error rate at the average value of the shift amount that becomes the first error rate, the eye diagram of the second error rate is obtained for each reference pattern bit transition presence / absence. Therefore, even when the bit error rate of the signal under test is low, it is possible to support accurate determination in a short time as to whether or not the measurement object satisfies the standard.

  Further, the shift amount setting unit in the test signal verification apparatus of the present invention has at least 3 between the two thresholds at which the bit error rate becomes the second error rate when the shift amount is the average value. For each division threshold value divided by the number of divisions, the shift amount at which the bit error rate becomes the second error rate is further obtained except for the preset threshold value.

  With this configuration, the test signal verification apparatus according to the present invention can select, for example, a shift amount and a threshold value that are concerned whether the standard is satisfied, and can grasp the eye diagram in the vicinity thereof in detail.

  Further, the threshold value setting unit in the test signal verification apparatus of the present invention has at least 3 between the two shift amounts at which the bit error rate becomes the second error rate when the threshold value is the preset threshold value. For each division shift amount divided by the number of divisions, the threshold value at which the bit error rate becomes the second error rate is further obtained except for the average value, and an eye diagram of a transition bit is displayed. .

  With this configuration, the test signal verification apparatus according to the present invention can select, for example, a shift amount and a threshold value that are concerned whether the standard is satisfied, and can grasp the eye diagram in the vicinity thereof in detail.

  The device test system of the present invention includes a test signal generation device that generates the test signal composed of transition bits and non-transition bits, and the test signal verification device.

  With this configuration, the device test system of the present invention obtains the shift amount at which the bit error rate at the preset threshold value becomes the second error rate, and the bit error rate of the transition bit at the threshold value at which the shift amount is preset is the first. By obtaining a threshold value at which the bit error rate becomes the second error rate when the shift value is an average value of 1 error rate, an eye diagram of the second error rate is obtained for each reference pattern bit transition presence / absence. Therefore, even when the bit error rate of the signal under test is low, it is possible to support accurate determination in a short time as to whether or not the measurement object satisfies the standard.

  The present invention provides a test signal verification apparatus having an effect that it is possible to support accurate determination as to whether or not a measurement object satisfies a standard even when the bit error rate of the signal under test is low. Is something that can be done.

  Embodiments of the present invention will be described below with reference to the drawings.

  A device test system according to an embodiment of the present invention is shown in FIG.

  The device test system 1 includes an input / output device 2, a test signal generation device 4 that generates a test signal for testing the measurement object 3, and a signal under test transmitted by the measurement object 3 that has received the test signal. And a test signal verification device 5 for verification.

  In this embodiment, an example in which the received test signal is transmitted as it is as the measurement object 3 will be described.

  The input / output device 2 includes an input unit 11 configured by a keyboard, a pointing device, and the like, a display unit 12 configured by a CRT display, a liquid crystal display, and the like, and a CPU ( Central Processing Unit) 13. The input / output device 2 may be configured by a computer device externally attached to the device test system 1. Further, the input / output device 2 may be integrated with the test signal verification device 5.

  The test signal generation device 4 includes a pattern storage unit 21 that stores a pattern of a test signal, and a test signal generation unit 22 that generates a test signal based on the pattern stored in the pattern storage unit 21.

  In the present embodiment, the pattern storage unit 21 is configured by a storage medium such as a RAM (Random Access Memory), and the test signal generation unit 22 is configured by a programmed FPGA (Field Programmable Gate Array).

  Further, the test signal verification device 5 receives a signal under test transmitted by the measurement object 3, and reproduces a clock signal for encoding the received signal under test from the signal under test, A phase shift unit 32 that shifts the phase of the clock signal reproduced by the clock reproduction unit 31, a shift amount setting unit 33 that sets a shift amount of the phase to be shifted by the phase shift unit 32, and a signal under test are binarized. A threshold value setting unit 34 for setting a threshold value, and a signal under test is sampled with a clock signal shifted by the phase shift unit 32, and the sampled signal under test is compared with a threshold value set by the threshold value setting unit 34. An encoding unit 35 that performs encoding by binarization and a reference pattern that corresponds to the pattern stored in the pattern storage unit 21 are stored. Based on the pattern storage unit 36, the signal under test encoded by the encoding unit 35, and the reference pattern stored in the reference pattern storage unit 36, the bit error rate of the signal under test is converted into the bit error rate of the transition bits. And a bit error rate measuring unit 37 that measures the bit error rate separately for non-transition bits.

  In the present embodiment, the clock recovery unit 31, the phase shift unit 32, the shift amount setting unit 33, the threshold setting unit 34, the encoding unit 35, and the bit error rate measurement unit 37 are integrally configured by a programmed FPGA, The reference pattern storage unit 36 is configured by a storage medium such as a RAM.

  The shift amount setting unit 33 changes the bit shift rate of the transition bit measured by the bit error rate measuring unit 37 and the bit error rate of the non-transition bit by changing the phase shift amount to be shifted by the phase shift unit 32. The shift amount to be the first error rate for specifying the second error rate and the average value of the diagram display target is specified.

  The threshold value setting unit 34 changes the bit error rate of the transition bits and the bit error rate of the non-transition bits measured by the bit error rate measurement unit 37 by changing the threshold value set in the encoding unit 35. A threshold value for the second error rate is specified.

  When the transition bit included in the received signal under test is emphasised, the DC component of the received signal under test is cut by a capacitor, and the threshold value is set to a common value for the transition bit and the non-transition bit. Alternatively, different threshold values may be set without cutting the DC component.

  Further, when the transition bits are not emphasized, the threshold value may be set to a common value.

  The bit error rate measurement unit 37 performs an exclusive OR operation between the reference pattern stored in the reference pattern storage unit 36 and the one obtained by shifting the reference pattern by one bit, and the position where 1 is output is the position of the transition bit. , 0 is determined as the position of the non-transition bit, and based on the determination result, the bit error rate of the signal under test is measured separately for the transition bit and the non-transition bit.

  About the device test system 1 comprised as mentioned above, the operation | movement is demonstrated using FIGS. First, a case where an eye diagram of a transition bit whose bit error rate is E-9 is measured will be described.

  FIG. 2 is a flowchart showing the operation of the device test system 1. FIG. 3 is a conceptual diagram for explaining a method of measuring an eye diagram of a transition bit.

  When the activation command is received from the input / output device 2, the threshold value Vth0 is set in the encoding unit 35 by the threshold setting unit 34, and the first error rate E-7 is set in the shift amount setting unit 33 (step S1). . Here, it is assumed that the threshold value Vth0 is input to the input unit 11 by the user. The threshold value Vth0 may be obtained by a known auto search function.

  Next, a shift amount specifying process is performed (step S2). In this shift amount specifying process, the bit error rate of the transition bits measured by the bit error rate measurement unit 37 is changed by fixing the threshold value at the threshold value Vth0 and changing the shift amount of the phase to be shifted by the phase shift unit 32. The shift amount setting unit 33 specifies a shift amount that results in an error rate E-7 of 1. Here, as shown in FIG. 3, the amount of shift at the point A1 in the direction in which the phase is delayed and the point A2 in the direction in which the phase is advanced is specified.

  Next, the shift amount Dc (average value) at the midpoint B of points A1 and A2 shown in FIG. 3 is determined by the shift amount setting unit 33 (step S3).

  Next, the second error rate E-9 is set in the shift amount setting unit 33 (step S4).

  Next, a shift amount specifying process is performed (step S5). In this shift amount specifying process, the bit error rate of the transition bits measured by the bit error rate measurement unit 37 is changed by fixing the threshold value at the threshold value Vth0 and changing the shift amount of the phase to be shifted by the phase shift unit 32. The shift amount setting unit 33 specifies a shift amount that results in an error rate E-9 of 2. Here, as shown in FIG. 3, the shift amount at the point C1 in the direction in which the phase is delayed and the point C2 in the direction in which the phase advances is specified.

  Note that the process of step S5 may be performed only when the first error rate and the second error rate are different.

  Next, the shift amount Dc is set in the phase shift unit 32 by the shift amount setting unit 33, and the second error rate E-9 is set in the threshold setting unit 34 (step S6).

  Next, a threshold specifying process is performed (step S7). In this threshold value specifying process, the shift amount is fixed at the shift amount Dc, and the threshold value set in the encoding unit 35 is changed, so that the bit error rate of the transition bits measured by the bit error rate measurement unit 37 is the second value. The threshold value setting unit 34 specifies the threshold value for the error rate E-9. Here, as shown in FIG. 3, the threshold value is specified at a point D1 in a direction with a high threshold value and a point D2 in a direction with a low threshold value.

  Next, by dividing the threshold specified by the threshold specifying process and Vth0 by the number of divisions 2 corresponding to the number of diagram measurement points 8, thresholds Vth1 and Vth2 fixed in step S10 described later are set as threshold setting units. 34 (step S8). Here, the relationship between the number of diagram measurement points and the number of divisions is shown in FIG.

  Next, the threshold value Vth1 is set in the encoding unit 35 by the threshold value setting unit 34 (step S10).

  Next, a shift amount specifying process is performed (step S11). In this shift amount specifying process, the bit error rate of the transition bits measured by the bit error rate measurement unit 37 is changed by fixing the threshold value at the threshold value Vth1 and changing the shift amount of the phase to be shifted by the phase shift unit 32. The shift amount setting unit 33 specifies a shift amount that results in an error rate E-9 of 2. Here, as shown in FIG. 3, the shift amount at the point E1 in the direction in which the phase is delayed and the point E2 in the direction in which the phase advances is specified.

  Note that the processing from step S9 to step S12 (loop 1) is repeated for the number of thresholds determined by the threshold setting unit 34. In the present embodiment, since the threshold values determined by the threshold value setting unit 34 are Vth1 and Vth2, the processing from step S9 to step S12 is performed twice. In step S10, in the second process, the threshold value Vth2 is set in the encoding unit 35 by the threshold value setting unit 34. In the subsequent shift amount specifying process, as shown in FIG. 3, the shift amounts at the point F1 in the direction in which the phase is delayed and the point F2 in the direction in which the phase is advanced are specified.

  Then, an eye mask for determining whether or not the measurement object 3 satisfies the standard, information indicating a shift amount specified by the shift amount setting unit 33 and a threshold corresponding to the shift amount, and a threshold setting unit 34 And the information indicating the shift amount corresponding to the threshold specified by the display are displayed on the display screen by the display unit 12 (step S13).

  FIG. 5 is a display example of an eye diagram of transition bits.

  In FIG. 5, the X axis 41 represents the phase shift amount set by the shift amount setting unit 33, and the Y axis 42 represents the threshold set by the threshold setting unit 34.

  The eye mask 43 represents an area for determining whether or not the measurement object 3 satisfies the standard. Note that the size of this area is determined based on the standard and the bit error rate that is a condition whether or not the standard is satisfied. The center coordinates of the eye mask 43 are: the X coordinate value is a 1-bit center time having a time width that is the reciprocal of the bit rate of the signal under test, and the Y coordinate value is a high level and low level signal determined by the standard. Use the coordinates as the threshold at the midpoint of the level. FIG. 5 shows the eye mask 43 when the bit error rate is E-9.

  The curve 44 connects points representing information indicating the specified shift amount and threshold value. FIG. 5 shows a curve 44 when the second error rate is E-9. The curve 44 is created by first connecting in the order of C1, E1, D1, E2, and C2, and then connecting in the order of C1, F1, D2, F2, and C2. Is done. Here, if the curve 44 does not enter the eye mask 43, the measurement object 3 is determined to satisfy the standard.

  FIG. 6 is a flowchart showing the shift amount specifying process. Here, the shift amount specifying process in step S5 will be described. Note that the shift amount specifying process in step S2 may be performed by replacing the second error rate with the first error rate in the following description.

  First, the signal under test transmitted by the measuring object 3 that has received the test signal is received by the clock recovery unit 31 of the test signal verification device 5, and the clock signal for encoding the received signal under test is clock recovered. The signal is reproduced from the signal under test by the unit 31 (step S22).

  The shift amount setting unit 33 sets the phase shift amount of the clock signal to be shifted to the phase shift unit 32 (step S23).

  Based on the shift amount set by the shift amount setting unit 33, the phase of the clock signal reproduced by the clock reproduction unit 31 is shifted by the phase shift unit 32 (step S24).

  The signal under test transmitted by the measurement object 3 that has received the test signal is sampled by the clock signal shifted by the phase shift unit 32, and the sampled signal under test is set at the threshold set by the threshold setting unit 34. By being compared and binarized, it is encoded by the encoding unit 35 (step S25).

  Based on the signal under test encoded by the encoding unit 35 and the reference pattern stored in the reference pattern storage unit 36, the signal under test is divided into a bit error rate of transition bits and a bit error rate of non-transition bits. Is measured by the bit error rate measuring unit 37 (step S26).

  The shift amount setting unit 33 determines whether or not the bit error rate of the transition bits measured by the bit error rate measuring unit 37 has reached the second error rate (step S27).

  When the shift amount setting unit 33 determines that the bit error rate of the transition bit has reached the second error rate, the shift amount setting unit 33 specifies the shift amount at which the bit error rate becomes the second error rate. (Step S29).

  Then, the shift amount specified by the shift amount setting unit 33, the threshold value corresponding to the shift amount, and the bit error rate when the shift amount is specified by the shift amount setting unit 33 are stored in a storage unit (not shown). Step S30).

  On the other hand, if the shift amount setting unit 33 does not determine that the bit error rate of the transition bit has reached the second error rate, the phase shift amount of the clock signal to be shifted to the phase shift unit 32 is the shift amount. Changed by the setting unit 33 (step S28), the process proceeds to step S23.

  Note that the processing from step S21 to step S31 (loop 1) is performed in the direction in which the phase is delayed and the direction in which the phase is advanced.

  Here, in the case of displaying the eye diagram of the second error rate, a first example of a method for specifying the shift amount in the direction in which the phase in which the bit error rate becomes the second error rate advances is shown in FIG. ).

  The rising and falling time positions of the signal under test are detected, and a 1-bit section with a time width that is the reciprocal of the bit rate of the signal under test is detected.

  As shown in FIG. 7A, the bit error rate is measured by advancing the phase by Δx from the midpoint B. If the bit error rate obtained by the measurement is smaller than the second error rate, the phase is further increased. Advance Δx. This operation is repeated until it is determined that the bit error rate measurement result is equal to the second error rate.

  A second example of a method for specifying the shift amount in the direction in which the phase in which the bit error rate becomes the second error rate when the eye diagram of the second error rate is displayed is based on FIG. I will explain.

  The rising and falling time positions of the signal under test are detected, and a 1-bit section with a time width that is the reciprocal of the bit rate of the signal under test is detected. The phase difference between one boundary point of the detected 1-bit section and the midpoint B is 2Δx.

  As shown in FIG. 7B, the bit error rate is measured by advancing the phase by Δx from the midpoint B. If the bit error rate obtained by the measurement is smaller than the second error rate, the phase is further increased. Advance Δx / 2. When the measurement result of the bit error rate with the shift amount advanced by Δx / 2 is larger than the second error rate, the phase is delayed by Δx / 4. When the measurement result of the bit error rate when delayed by Δx / 4 is smaller than the second error rate, the phase is advanced by Δx / 8. This operation is repeated until it is determined that the bit error rate measurement result is equal to the second error rate. Since the phase amount to be advanced or the phase amount to be delayed is multiplied by 1/2 each time, the shift amount can be specified faster than the first example shown in FIG.

In FIG. 7B, the determination method of whether or not the measurement result of the bit error rate is equal to the second error rate is, for example, a transition bit or a non-transition when the second error rate is E-9. For each bit, an error of 10 ⁹ bits in the signal under test is measured, and when the number of detected errors is 0, it is determined that the error is lower than E-9, and the shift amount in the direction in which the phase advances To change. When an error occurs before 10 ^9- bit error measurement is completed, the bit error rate is determined to be E-9 or more, and error measurement at the current shift amount is interrupted, and the phase of the shift amount is delayed. Change direction. Continue until the amount of change in the shift amount is minimum resolution of the shift amount setting, E-9 a shift amount that most phase advances of the shift amount error count becomes zero when eventually the ^109-bit measurement Specific shift amount.

  By setting the number of bits for error measurement to be large, the accuracy of the specified threshold value and shift amount can be increased, and a highly accurate eye diagram can be obtained.

  FIG. 8 is a flowchart showing the threshold specifying process.

  First, the signal under test transmitted by the measuring object 3 that has received the test signal is received by the clock recovery unit 31 of the test signal verification device 5, and the clock signal for encoding the received signal under test is clock recovered. The signal is reproduced from the signal under test by the unit 31 (step S42).

  Next, based on the shift amount set by the shift amount setting unit 33, the phase of the clock signal reproduced by the clock reproduction unit 31 is shifted by the phase shift unit 32 (step S43).

  The threshold value is set in the encoding unit 35 by the threshold setting unit 34 (step S44).

  The signal under test received by the clock recovery unit 31 is sampled with the clock signal shifted by the phase shift unit 32, and the sampled signal under test is compared with the threshold set by the threshold setting unit 34 to obtain a binary value. Is encoded by the encoding unit 35 (step S45).

  Based on the signal under test encoded by the encoding unit 35 and the reference pattern stored in the reference pattern storage unit 36, the signal under test is divided into a bit error rate of transition bits and a bit error rate of non-transition bits. Is measured by the bit error rate measuring unit 37 (step S46).

  The threshold value setting unit 34 determines whether or not the bit error rate of the transition bits measured by the bit error rate measuring unit 37 has reached the second error rate (step S47).

  When the threshold setting unit 34 determines that the bit error rate of the transition bit has reached the second error rate, the threshold setting unit 34 specifies the threshold at which the bit error rate becomes the second error rate (step S49).

  Then, the threshold specified by the threshold setting unit 34, the shift amount corresponding to the threshold, and the bit error rate when the threshold is specified by the threshold setting unit 34 are stored in the storage unit (step S50).

  On the other hand, if the threshold setting unit 34 does not determine that the bit error rate of the transition bit has reached the second error rate, the threshold set in the encoding unit 35 is changed by the threshold setting unit 34. (Step S48), the process proceeds to Step S44.

  Note that the processing from step S41 to step S51 (loop 1) is performed in the direction in which the phase is delayed and the direction in which the phase is advanced.

  Here, the threshold value setting unit 34 specifies the threshold value at which the bit error rate becomes the second error rate by changing the threshold value. The shift amount setting unit 33 changes the shift amount so that the bit error rate becomes the first error rate. The method is the same as the method for specifying the shift amount with an error rate of 2.

  Next, a case where an eye diagram of a non-transition bit whose bit error rate is E-9 is measured will be described.

  First, similarly to the case of measuring the eye diagram of the transition bit, the processing from step S1 to step S13 is performed.

  FIG. 9 is a display example of an eye diagram of non-transition bits.

  In FIG. 9, the X-axis 51 represents the phase shift amount set by the shift amount setting unit 33, and the Y-axis 52 represents the threshold set by the threshold setting unit 34.

  The eye mask 53 represents an area for determining whether or not the measurement object 3 satisfies the standard. Note that the size of this area is determined based on the standard and the bit error rate that is a condition whether or not the standard is satisfied. The center coordinate of the eye mask 53 is such that the X coordinate value is the center time of a 1-bit section having a time width that is the reciprocal of the bit rate of the signal under test, and the Y coordinate value is the high level of the signal determined by the standard. The coordinates are set as threshold values at the midpoint of the low level. FIG. 9 shows the eye mask 53 when the bit error rate is E-9.

  A curve 54 connects points representing information indicating the specified shift amount and threshold value. FIG. 9 shows a curve 54 when the second error rate is E-9. If the measurement object 3 does not enter the eye mask 53, the measurement object 3 is determined to satisfy the standard.

  Further, in the shift amount specifying process, processes from step S22 to step S26 are performed. Next, the shift amount setting unit 33 determines whether or not the bit error rate of the non-transition bits measured by the bit error rate measuring unit 37 has reached the second error rate.

  When the shift amount setting unit 33 determines that the bit error rate of the non-transition bits has become the second error rate, the shift amount setting unit 33 specifies the shift amount at which the bit error rate becomes the second error rate. Then, the process of step S30 is performed.

  On the other hand, if the shift amount setting unit 33 does not determine that the bit error rate of the non-transition bits has reached the second error rate, the phase shift amount of the clock signal to be shifted to the phase shift unit 32 is shifted. The amount is changed by the amount setting unit 33, and the process proceeds to step S24.

  Note that when measuring an eye diagram of a non-transition bit, the left cross point of the eye diagram is not detected, and therefore the processing from step S21 to step S31 is performed only in the direction in which the phase advances.

  In the threshold value specifying process, processes from step S42 to step S46 are performed. Next, the threshold setting unit 34 determines whether or not the bit error rate of the non-transition bits measured by the bit error rate measuring unit 37 has reached the second error rate.

  When the threshold setting unit 34 determines that the bit error rate of the non-transition bits has become the second error rate, the threshold setting unit 34 specifies the threshold value at which the bit error rate becomes the second error rate, and the step The process of S50 is performed.

  On the other hand, if the threshold setting unit 34 does not determine that the bit error rate of the non-transition bits has reached the second error rate, the threshold setting unit 34 changes the threshold set in the encoding unit 35. Then, the process proceeds to step S44.

  Note that when measuring an eye diagram of a non-transition bit, the left cross point of the eye diagram is not detected, and therefore the processing from step S41 to step S51 is performed only in the direction in which the phase advances.

  When measuring an eye diagram of a non-transition bit, each of dividing at least two between a midpoint B and a boundary point whose phase is delayed with respect to the midpoint B among the detected boundary points of one bit section Even at boundary points where the phase is delayed with respect to the shift amount or the midpoint B, an eye diagram may be created by specifying a threshold value.

  3, 5, and 9, the points specified by the combination of the threshold value that is the second error rate and the shift amount are connected by straight lines in both the transition bits and the non-transition bits. It may be connected with a smooth line so as to include all.

  According to the device test system 1 in the present embodiment, the shift amount at which the bit error rate at the preset threshold value Vth0 becomes the second error rate is obtained, and the bit error of the transition bit at the preset threshold value Vth0. When the average value Dc of the shift amount at which the rate becomes the first error rate is obtained, a threshold value at which the bit error rate becomes the second error rate is obtained, whereby the eye diagram of the second error rate is converted to the bit transition of the reference pattern. Therefore, even when the bit error rate of the signal under test is low, it is possible to support accurate determination in a short time as to whether or not the measurement object 3 satisfies the standard.

  The midpoint B may be the middle position of the detected 1-bit section, that is, the X coordinate of the center coordinate of the eye mask 53, and the signal under test is distinguished from the transition bit and the non-transition bit at a preset threshold value. Alternatively, the average value of the clock signal phases may be such that the total bit error rate measured without the first error rate.

  In the present embodiment, an example suitable for the case where the measurement object 3 is applied to the received test signal as it is is shown, but the output side of the test signal generator 4 and the signal under test verification are shown. By providing an electric-optical converter and an optical-electrical converter on the input side of the apparatus 5, an optical module or the like can be applied as the measurement object 3.

  Further, a shift amount is set in advance by a well-known auto search function or the like, two threshold values at which the bit error rate becomes the first error rate in the preset shift amount, and an average value thereof (threshold average value) are obtained, The eye diagram includes a shift amount at which the bit error rate becomes the second error rate at the obtained threshold average value and two threshold values at which the bit error rate becomes the second error rate at a preset shift amount. You may create it.

1 is a block diagram of a device test system according to an embodiment of the present invention. The flowchart which shows operation | movement of the device test system in one embodiment of this invention. Conceptual diagram for explaining a method of measuring an eye diagram of a transition bit according to an embodiment of the present invention. Table showing the relationship between the number of diagram measurement points and the number of divisions in an embodiment of the present invention Display example of eye diagram of transition bits in one embodiment of the present invention The flowchart which shows the shift amount specific process in one embodiment of this invention Explanatory drawing for specifying the shift amount in one embodiment of the present invention The flowchart which shows the threshold value specific process in one embodiment of this invention Example of display of eye diagram of non-transition bit in one embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Device test system 2 Input / output apparatus 3 Measurement object 4 Test signal generation apparatus 5 Test signal verification apparatus 11 Input part 12 Display part 13 CPU
21 Pattern storage unit 22 Test signal generation unit 31 Clock recovery unit 32 Phase shift unit 33 Shift amount setting unit 34 Threshold setting unit 35 Encoding unit 36 Reference pattern storage unit 37 Bit error rate measurement unit

Claims (4)

Test signal verification for receiving a signal under test transmitted by the measurement object (3) that has received a test signal composed of transition bits and non-transition bits, and displaying an eye diagram for each bit error rate on the display unit (12) A device (5) comprising:
An encoding unit (35) for encoding the signal under test based on a threshold and a phase of the clock signal;
A phase shift unit (32) for shifting the phase of the clock signal input to the encoding unit;
A shift amount setting unit (33) for setting a shift amount in the phase shift unit;
A threshold setting unit (34) for setting the threshold in the encoding unit;
A bit error rate measuring unit (37) that detects the positions of transition bits and non-transition bits in a reference pattern corresponding to the pattern of the signal under test and measures the bit error rate of the signal under test for each bit transition. And comprising
The shift amount setting unit obtains the two shift amounts at which the bit error rate of the transition bits at the preset threshold value becomes the first error rate and an average value thereof, and the transition bits are displayed in an eye diagram. When the target second error rate is different from the first error rate, the shift amount at which the bit error rate at the preset threshold becomes the second error rate is obtained, and for non-transition bits, Obtaining the shift amount at which the bit error rate at the preset threshold becomes the second error rate;
The threshold setting unit obtains the threshold value at which the bit error rate becomes the second error rate when the shift amount is the average value, thereby obtaining an eye diagram of the second error rate as a bit of the reference pattern. A test signal verification apparatus, characterized by being displayed for each transition. The shift amount setting unit, for each division threshold value that divides between the two threshold values at which the bit error rate becomes the second error rate when the shift amount is the average value, at a division number of at least 3. 2. The test signal verification apparatus according to claim 1 , wherein the shift amount at which a bit error rate becomes the second error rate is further obtained except for the preset threshold value. 3. The threshold setting unit is configured to divide each of the two shift amounts at which the bit error rate becomes the second error rate when the threshold is the preset threshold by at least a division number of 3. the amount, except for the mean value, further obtains the threshold bit error rate becomes the second error rate, according to claim 1 or claim 2, characterized in that to display the eye diagram of the transition bit Test signal verification device. A test signal generating device (4) for generating the test signal composed of transition bits and non-transition bits;
A device test system comprising the test signal verification apparatus (5) according to any one of claims 1 to 3 .

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