JP5074300B2 - Semiconductor device - Google Patents

Description

  The present invention incorporates therein a Loopback BIST (Built-in Seifest Test) circuit capable of executing a test of a high-speed IO buffer operating at several Gbps using an external device such as an LSI tester operating at a low speed of 100 Mbps, for example. The present invention relates to a semiconductor device.

  PCI-Express (PCIe) or Serial-ATA (SATA) is a high-speed IO buffer that operates at several Gbps (for example, 3 Gbps to 6 Gbps). In a semiconductor device in which such a high-speed IO buffer is mounted in a chip, a mass production at-speed test of a high-speed IO buffer unit can be performed using an inexpensive LSI tester (for example, a low-speed operation LSI tester operable at 100 MHz). In order to be able to be implemented, a Loopback BIST circuit is mounted in the chip.

  The conventional Loopback BIST circuit includes a pattern generator capable of generating a test pattern which is a random signal on the Tx side (output buffer side), and an expected value comparison circuit corresponding to the test pattern generated on the Rx side (input buffer side) Built in.

  The margin check in the timing direction is performed by sequentially shifting the phase of a clock generated by a CDR (Clock Data Recovery) built in the device and causing the clock to function like a strobe of an LSI tester.

JP 2007-271696 A Japanese Patent Laid-Open No. 2003-78020

  The conventional Loopback BIST circuit has a timing direction in a state in which the voltage amplitude of the test pattern input from the output buffer to the input buffer through an external loopback path is fixed to a voltage value that is ½ of the power supply voltage of the input buffer. Only margin test can be performed, and margin check in the voltage amplitude direction cannot be tested. For this reason, there is a possibility that a semiconductor device with insufficient voltage amplitude margin flows out to the next process of the production process, and this point needs to be prevented.

  The present invention has been made to overcome such technical problems. It is an object of the present invention to provide a semiconductor device including a Loopback BIST circuit that can perform a margin test in the timing direction even when the voltage amplitude of a test pattern is an arbitrary voltage value.

  In the semiconductor device according to the subject of the present invention, when a test mode selection signal is received from an external device such as an LSI tester to enter a timing margin check test mode, an external reference voltage of a certain value is applied from the external device to the pad, The CPU sets the delay time of one of the first and second variable delay elements. For example, it is assumed that the delay time of the second variable delay element connected to the output of the CDR circuit is variably set. Thereafter, the pattern generator outputs a parallel test pattern signal, and the serializer converts the parallel signal test pattern signal into a serial test pattern signal according to the first clock signal. The converted test pattern signal is output from the output buffer to the external loop back path formed by the wiring of the test jig, and is input to the input buffer after transmitting the external loop back path. The voltage of the test pattern signal output from the input buffer is ½ of the power supply voltage of the input buffer. The test pattern signal output from the input buffer is input to the positive terminal of the first differential buffer and the negative terminal of the second differential buffer, while the value of the external reference voltage is the negative terminal of the first differential buffer. And input to the positive terminal of the second differential buffer. If the value of the external reference voltage is less than the voltage of the test pattern signal output from the input buffer, the selector selects the differential signal of the first differential buffer, while the value of the external reference voltage is from the input buffer. When the voltage is equal to or higher than the voltage of the output test pattern signal, the selector selects the differential signal of the second differential buffer. The CDR circuit detects the clock from the edge of the differential signal output by the selector and then delays the phase by 90 degrees to generate the second clock signal. Then, the second variable delay element sequentially changes the phase of the second clock signal. The deserializer converts the test pattern signal output from the input buffer into a parallel test pattern signal again according to the second clock signal. The pattern comparator compares the converted test pattern signal with the comparison pattern signal to determine whether or not both pattern signals match within a predetermined range. The error measuring device stores the presence / absence of an error determined by the pattern comparator. When the presence or absence of an error for each phase of the second clock signal for all external reference voltage values is stored in the error measuring instrument, the CPU reads the result from the error measuring instrument and outputs it to the external device. The external device maps the eye pattern based on the received error measurement result, and determines the quality of the semiconductor device from the size of the eye opening of the eye pattern.

  According to the subject of the present invention, since the input voltage to the CDR circuit is a variable differential voltage, the timing margin of each differential voltage can be checked, so that a defective voltage margin can be detected.

  Hereinafter, various embodiments of the subject of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 shows a case where a mass production at-speed test of a high-speed IO buffer (operating at several Gbps) 2 formed in a semiconductor chip of a semiconductor device 5 is performed using an LSI tester 4 operating at a low speed of 100 Mbps, for example. It is a block diagram which shows typically the circuit arrangement | positioning relationship. Here, a margin test in the timing direction of a high-speed signal of several Gbps (for example, 3 Gbps to 6 Gbps) can be performed using an inexpensive LSI tester 4 while reducing the number of pins provided on the semiconductor device 5 side. For this purpose, the semiconductor device 5 includes the Loopback BIST circuit 1 formed in the semiconductor chip.

  The Loopback BIST circuit 1 adopts a configuration of full duplex communication (Full Duplex), its output side is called a Tx port, and its input side is called an Rx port. The power supply voltage VDD is supplied to the Tx differential buffer and the Rx differential buffer of the Loopback BIST circuit 1 described later. The test pattern signal output from the Tx port of the Loopback BIST circuit 1 during the margin test (jitter measurement test) in the timing direction is transmitted through the external loopback path formed by the circuit wiring in the test jig 3, and then the Loopback BIST. Input to the Rx port of circuit 1. Therefore, the voltage amplitude and phase of the test pattern signal output from the Tx port are changed through the passage of the external loopback path. Therefore, it is necessary to perform a margin test (jitter measurement test) in the timing direction of the test pattern signal for each voltage amplitude of the test pattern signal input into the Loopback BIST circuit 1 from the Rx port.

  The LSI tester 4 outputs various low-speed signals SEL, TSEL, and TSS (all of which have a frequency of several hundred MHz), which will be described later, to the Loopback BIST circuit 1 through the test jig 3. Further, the Loopback BIST circuit 1 outputs a low speed signal REQ requesting application and change of the external reference voltage signal Vref to the LSI tester 4 via the test jig 3. As a result, the LSI tester 4 changes the voltage value of the external reference voltage signal Vref, which is a DC signal, stepwise every time the signal REQ is received via the test jig 3, and the Loopback BIST circuit 1. Apply to. Furthermore, the Loopback BIST circuit 1 uses the test jig 3 to send an error presence / absence result (low-speed signal) ES obtained by a margin test in the timing direction performed for each voltage value of the external reference voltage signal Vref to the LSI. Output to the tester 4. As a result, the LSI tester 4 that has received the contents of the result signal ES determines that it is Pass if there is no error, and determines that it is Fail if an error occurs, thereby creating an eye pattern as shown in FIG. . Then, the LSI tester 4 determines whether or not the value (the eye opening width dimension) of the eye opening (area determined to be “Pass”) of the created eye pattern has a predetermined value or more. That is, the LSI tester 4 determines that the semiconductor device 5 is a non-defective product when an eye pattern with an eye opening value greater than or equal to a desired value is obtained, while only an eye pattern with an eye opening value less than the desired value is obtained. Therefore, it is determined that the semiconductor device 5 is a defective product.

  FIG. 2 is a block diagram showing the internal configuration of the Loopback BIST circuit 1 that forms the core of the present embodiment. In FIG. 2, the differential signal between the output signal of the Rx buffer (input buffer) 10 and the external reference voltage signal Vref is used as the input signal of the CDR (Clock Data Recovery) circuit 12 in this embodiment. It is a feature point. In FIG. 2, reference symbols PAD <b> 1 to PAD <b> 12 are pads that constitute input / output pins of the Loopback BIST circuit 1. Each component of the Loopback BIST circuit 1 is as follows.

  In response to the reception of the test start signal TSS whose level is “1”, the pattern generator 20 is a test pattern signal (a test pattern signal having a frequency of several GHz) which is an N-bit parallel signal during the test mode period. Is generated and output. The test mode selection signal TSEL is a signal indicating the start of the timing margin test, that is, the jitter measurement test of the test pattern signal. The test mode selection signal TSEL instructs execution of the test mode during the period when the level is “1”. Accordingly, the selector 19 selects and outputs the test pattern signal output from the pattern generator 20 during the period when the level of the test mode selection signal TSEL is “1”. On the other hand, the period during which the level of the test mode selection signal TSEL is “0” is a normal operation time, and the selector 19 selects and outputs the normal input data ID input from the high-speed IO buffer 2. In the following, description of each element in the circuit 1 during normal operation is omitted, and the configuration and operation of each element in the circuit 1 during the test mode period which is a jitter measurement test period are described. And

  The PLL circuit 18 multiplies the low-speed clock signal of several hundred MHz input from the LSI tester 4 to generate a phase-locked high-speed (frequency is several GHz) first clock signal CLK1. The serializer 17 converts the N-bit parallel signal output from the selector 19 into a serial signal in accordance with the rising timing of the first clock signal CLK1 output from the PLL circuit 18, and converts the converted serial signal into a differential buffer. The data is output to a certain Tx buffer (output buffer) 16. As a result, the output buffer 16 outputs the test pattern signal, which is a serial signal, to the above-described external loopback path during the test mode period and the period when the level of the test start signal TSS is “1”. The first clock signal CLK1 output from the PLL circuit 18 has jitter. The jitter of the first clock signal CLK1 is transmitted from the serializer 17 via a flip-flop (not shown) in the serializer 17. Superimposed on the test pattern signal of the output serial signal.

  The input buffer 10, which is a differential buffer, receives the test pattern signal that has passed through the external loopback path, and has the voltage VDD / 2 that is the central value of the voltage amplitude that has the largest timing margin. An Rx output signal VRx is output.

  The pad PD5 receives an external reference voltage signal Vref that is a DC signal output from the LSI tester 4 of FIG. The LSI tester 4 outputs the timing output from the CPU 21 in the Loopback BIST circuit 1 via the pad PD10 every time the timing margin check test of the test pattern signal when the external reference voltage signal Vref is at a certain level is completed. The level of the external reference voltage signal Vref is changed in response to the reception of the clock REQ that notifies the end of the margin check test and requests the change of the external reference voltage signal Vref.

  The first and second differential buffers DA 1 and DA 2 obtain a differential signal of a reference voltage that gives a difference value between the Rx output signal VRx and the external reference voltage signal Vref, and output the differential signal to the selector 11.

  The level setting of the select signal SEL of the selector 11 is set in the LSI tester 4 as follows. That is, as shown in FIG. 5A, when the set external reference voltage signal Vref is smaller than the voltage value VDD / 2 of the Rx output signal VRx, the LSI tester 4 sets the level of the select signal SEL. Set to “1”. On the other hand, as shown in FIG. 5B, when the set external reference voltage signal Vref is equal to or higher than the voltage value VDD / 2 of the Rx output signal VRx, the LSI tester 4 sets the level of the select signal SEL to “ Set to 0 ”. As a result, the selector 11 sets the differential signal output from the first differential buffer DA1 to the reference signal differential signal VRx1 in response to the application of the select signal SEL having the level “1”. In this case, a timing margin check test is performed in a range where the voltage amplitude value of the differential signal VRx1 of the reference voltage is negative with respect to the voltage value VDD / 2. Conversely, in response to the application of the select signal SEL with the level “0”, the selector 11 sets the differential signal output from the second differential buffer DA2 to the differential signal VRx1 of the reference voltage. In this case, a timing margin check test is performed in a range where the voltage amplitude value of the differential signal VRx1 of the reference voltage is 0 or plus with respect to the voltage value VDD / 2.

  In the normal operation, a ground potential is always applied to the pad PD5, and a voltage having a level of “1” is applied to the pad PD6, so that VRx = VRx1.

  As shown in FIG. 3, the CDR circuit 12 detects an edge from the data string of the differential signal VRx1 having a reference voltage having jitter, and shifts the phase by 90 degrees with reference to the detected edge timing. A high-speed (having a frequency of several GHz) second clock signal CLK2 is generated and output. Therefore, the second clock signal CLK2 also includes jitter.

  The first variable delay element (first phase changing unit) VDL1 (VDL: Variable Delay Line) is delayed in accordance with the input of the first delay control signal DLC1 that is coded and output from the CPU 21 in the circuit 1. This is a delay element capable of changing the time. That is, the first variable delay element VDL1 changes the phase of the test pattern signal input from the input buffer 10 by a delay time that is changed every time the first delay control signal DLC1 is input. At that time, the CPU 21 measures the number of times the first delay control signal DLC1 is output by the internal counter 22, and increments the count value of the counter 22 by 1 each time the first delay control signal DLC1 is output. When the count value reaches the upper limit value set in the counter 22, the output of the first delay control signal DLC1 is stopped and the count value of the counter 22 is reset to zero. This time corresponds to the end of the VDL code increment described later.

  Similarly, the second variable delay element (first phase changing unit) VDL2 is also a delay element whose delay time can be changed according to the input of the second delay control signal DLC2 that is coded and output from the CPU 21. . That is, the second variable delay element VDL2 changes the phase of the second clock signal CLK2 input from the CDR 12 by a delay time that is changed every time the second delay control signal DLC2 is input. At that time, the CPU 21 measures the number of times the second delay control signal DLC2 is output by the internal counter 22, and increments the count value of the counter 22 by 1 each time the second delay control signal DLC2 is output. When the count value reaches the upper limit value set in the counter 22, the output of the second delay control signal DLC2 is stopped and the count value of the counter 22 is reset to zero. This time corresponds to the end of the VDL code increment described later.

  When a timing margin check test of a test pattern signal in a certain external reference voltage signal Vref is performed, one of the first variable delay element VDL1 and the second variable delay element VDL2 is operated. . Therefore, when the second delay control signal DLC2 is output and the phase of the second clock signal CLK2 is sequentially changed by the second variable delay element VDL2, the CPU 21 does not output the first delay control signal DLC1. In this way, the CPU 21 outputs either one of the first and second delay control signals DLC1 and DLC2, thereby making the relative relationship between the test pattern signal (the output signal VRx of the input buffer 10) and the second clock signal CLK2. The phase relationship is arbitrarily changed. Note that each of the first and second variable delay elements VDL1 and VDL2 is configured, for example, by connecting a plurality of buffers each having a known delay value in series.

  The deserializer 13 converts the test pattern signal of serial data input from the input buffer 10 into a test pattern signal OD as N-bit parallel data and outputs it according to the input timing of the second clock signal CLK2. Here, FIG. 4 is a block diagram showing the configuration of the input unit of the deserializer 13. As shown in FIG. 4, the input unit of the deserializer 13 has a shift register including two flip-flops FF1 and FF2 connected in series. Therefore, the input unit of the deserializer 13 captures input data by the operation of the shift register in accordance with the rising timing of the second clock signal CLK2. Therefore, in the normal operation mode in which the first and second variable delay elements VDL1 and VDL2 do not perform the delay operation, the input unit of the deserializer 13 captures the input data signal at a point where the largest timing margin can be obtained. On the other hand, in the test mode period in which one of the first and second variable delay elements VDL1 and VDL2 performs a delay operation, the deserializer 13 increases as the delay time increases or the phase fluctuation amount increases. The timing margin at the time of capturing the test pattern signal input by the input unit becomes smaller. Therefore, whether or not the test pattern signal can be normally captured depends on the jitter characteristic of the output signal VRx of the input buffer 10 and the jitter characteristic of the second clock signal CLK2. Accordingly, when the jitter characteristics of the PLL circuit 18 and the CDR circuit 12 that generate the high-speed first and second clock signals CLK1 and CLK2 are out of the standard, normal system operation cannot be guaranteed. The PLL circuit 18 and the CDR circuit 12 are treated as defective products.

  The pattern comparator 14 executes the comparison process and the output process of the comparison result during the period when the test start signal TSS is at the “1” level. That is, the pattern comparator 14 stores in advance a comparison pattern signal equivalent to the test pattern signal generated by the pattern generator 20. Then, the pattern comparator 14 performs a pattern comparison between the test pattern signal OD after the phase change input from the deserializer 13 and the comparison pattern signal, and determines whether or not the two pattern signals match within a desired range. judge. If both pattern signals match within a desired range, the pattern comparator 14 determines the value of the differential signal VRx1 and the value of the phase (code values of one of the delay control signals DLC1 and DLC2). In this case, the result that there is no error is held in an error measuring instrument 15 comprising a memory, for example. On the other hand, if the two pattern signals do not match within the desired range, the pattern comparator 14 determines the value of the differential signal VRx1 and the value of the phase (the code of one of the delay control signals DLC1 and DLC2). Value) is stored in the error measuring instrument 15 with an error.

  The error measuring instrument 15 is controlled for each input voltage (each external reference voltage) under the control of the read control signal RCS output by the CPU 21 according to the timing at which the level of the test mode selection signal TSEL shifts from “1” to “0”. An error measurement collection result signal ES in the timing direction (for each Vref) is output to the LSI tester 4.

  Hereinafter, the processing contents of the timing margin check test in the Loopback BIST circuit 1 of FIG. 2 will be described based on the flowchart of FIG. 6 showing the processing procedure.

  First, in step S1, the LSI tester 4 (FIG. 1) selects a test mode for performing a timing margin check test for each external reference voltage Vref. As a result, the LSI tester 4 inputs the test mode selection signal TSEL rising from the “0” level to the “1” level to the pad PD 7 via the test jig 3. Thus, the selector 19 continues to select the terminal 1 during the period when the test mode selection signal TSEL is at the “1” level. In response to the reception of the “1” level test mode selection signal TSEL, the CPU 21 recognizes that the operation of the circuit 1 has been switched from the normal operation to the timing margin check test mode.

  In the next step S2, the setting process of the external reference voltage Vref is performed. That is, in response to the operation mode of the circuit 1 shifting to the test mode, the CPU 21 requests the LSI tester 4 to generate and output the external reference voltage Vref via the pad PD 10 and the test jig 3. The signal REQ to be output is output. In response to the request for the signal REQ, the LSI tester 4 sets the external reference voltage Vref to an initial value and then applies the initial value of the external reference voltage Vref to the pad PD5 via the test jig 3. In this case, the LSI tester 4 sets the initial value of the external reference voltage Vref to the voltage value VDD / 2 of the output signal VRx of the input buffer 10, and thereafter changes the vertical value every time the signal REQ is received. Also good. Alternatively, the LSI tester 4 sets a predetermined minimum value (<VDD / 2) to the initial value of the external reference voltage Vref, and thereafter sets the value of the external reference voltage Vref to the value every time the signal REQ is received. You may make it change in steps toward predetermined | prescribed maximum value (> VDD / 2). Alternatively, the LSI tester 4 sets the predetermined maximum value to the initial value of the external reference voltage Vref, and thereafter directs the value of the external reference voltage Vref to the predetermined minimum value every time the signal REQ is received. It may be changed step by step. Then, the LSI tester 4 sets the level of the selection signal SEL to “0” or “0” according to the magnitude relationship between the set value of the external reference voltage Vref and the voltage value VDD / 2 of the output signal VRx of the input buffer 10. After setting to “1”, the selection signal SEL is applied to the pad PD6 through the test jig 3. For example, when the initial value of the external reference voltage Vref is set to a predetermined minimum value, the LSI tester 4 outputs a selection signal SEL whose level is “1”. In this case, the selector 11 selects and outputs the output signal of the first differential buffer DA1 as the differential signal VRx1. Thereafter, the LSI tester 4 outputs a signal (not shown) for transmitting to the circuit 1 side that the external reference voltage Vref has been output / applied to the CPU 21 via the test jig 3.

  In the next step S3, the CPU 21 sets VDLcode. That is, the CPU 21 sets the code value of one of the first and second delay control signals DLC1 and DLC2 to an initial value, and the corresponding variable delay in the first and second variable delay elements VDL1 and VDL2. Sets the delay time generated by the element. After that, the reset counter 22 in the CPU 21 counts the count value to 1.

  In the next step S4, test pattern running and comparison processing is executed. First, the CPU 21 outputs a test start signal output request signal TSSREQ to the LSI tester 4 via the test jig 3 in order to prompt the LSI tester 4 to start a test. In response to receiving this request signal TSSREQ, the LSI tester 4 applies the tester start signal TSS whose level is raised from “0” to “1” to the pad PD8 via the test jig 3. During the period in which the tester start signal TSS is at the “1” level, the pattern generator 20 generates the test pattern signal that is the N-bit parallel signal described above, the selector 19 selects the test pattern signal, and the serializer 17 converts the input parallel test pattern signal into a test pattern signal which is a serial signal. The converted serial test pattern signal is output from the output buffer 16 to the external loopback path wired in the test jig 3, and the test pattern signal that has passed through the external loopback path is input to the input buffer 10. Entered. Now, when the voltage value of the external reference voltage signal Vref is smaller than the voltage value VDD / 2 of the output signal of the input buffer 10, the level of the selection signal SEL is set to “1”, and the first differential buffer The output of DA1 is selected as the differential signal VRx1 by the selector 11 and input to the CDR circuit 12. If the second variable delay element VDL2 generates a delay time corresponding to the code value given by the second delay control signal DLC2, the phase of the second clock signal CLK2 output from the CDR circuit 12 is CDR. In the circuit 12, a clock synchronized with the rising edge of the differential signal VRx1 is generated and its phase is delayed by 90 degrees, so that it is further delayed. Thereafter, a test pattern signal as a parallel signal whose phase is delayed is output from the deserializer 13.

  The pattern comparator 4 performs a comparison process between the received test pattern signal and the above-described comparison pattern signal, holds an error measurement result indicating the presence / absence of an error in the error measuring device 15, and measures the error with the VDLcode value. Is output to the CPU 21 (step S5). Then, the CPU 21 outputs a signal TSSEND that notifies the end of error measurement to the LSI tester 4 via the test jig 3, and the LSI tester 4 receives the signal TSSEND in response to the reception of the signal TSSEND. Change the level to “0”.

  In the next step S6, in response to reception of the error measurement completion signal EES, the CPU 21 determines whether or not the timing margin check test with a certain external reference voltage signal Vref is completed. That is, in the above example, the CPU 21 determines whether or not the count value of the counter 22 has reached the upper limit value. If the count value has not reached the upper limit value, the timing margin check test with a certain external reference voltage signal Vref is performed. It is determined that it has not been completed, and the code value of the second delay control signal is incremented and the count value of the counter 22 is also incremented. Then, steps S4 and S6 described above are repeated. On the other hand, when the count value of the counter 22 reaches the upper limit value, the CPU 21 determines that the timing margin check test using a certain external reference voltage signal Vref is completed, and the count value of the counter 22 and the variable control are determined. The code value of the delay control signal that is being reset is reset. At this time, for example, as shown by an arrow and a broken line in FIG. 5A, the result of the presence or absence of an error in the timing direction in an external reference voltage signal Vref smaller than VDD / 2 is obtained. can get. Thereafter, the CPU 21 outputs a signal REQ requesting to change the voltage value of the external reference voltage signal Vref by one step to the LSI tester 4 via the test jig 3.

  In step S7, it is determined whether or not the external reference voltage signal Vref has reached the final value after the change. That is, the CPU 21 outputs a signal REQ requesting further change of the external reference voltage signal Vref to the LSI tester 4 via the test jig 3. Upon receiving such a signal REQ, the LSI tester 4 changes the voltage value of the external reference voltage signal Vref by a predetermined value when confirming that the current voltage value of the external reference voltage signal Vref is not the final value. After that, a new external reference voltage signal Vref after the change is applied to the pad PD5 through the test jig 3 (step S2). Thereafter, similar steps S3 to S6 are repeated. As a result, for example, as shown by an arrow and a broken line in FIG. 5B, a result of the presence or absence of an error in the timing direction in a certain external reference voltage signal Vref larger than VDD / 2 is obtained. It is done.

  On the other hand, when the LSI tester 4 confirms that the current value of the external reference voltage signal Vref has reached the final value after the change, the timing margin check test at the voltage value of each external reference voltage signal Vref. Is determined to have been completed, and the level of the test mode selection signal TSEL is changed from “1” to “0”. The CPU 22 that has received such a level change recognizes that the timing margin check test at the voltage value of each external reference voltage signal Vref has already been completed.

  As a result, the CPU 21 outputs a read control signal RCS, reads all measurement results from the error measuring instrument 15, that is, the error measurement collection result signal ES for each input voltage, and passes through the test jig 3. The signal ES is transmitted to the LSI tester 4 (step S8). At that time, the CPU 21 transmits information on the number of times of code setting of the variable delay elements VDL1 and VDL2 to the LSI tester 4 together with the signal ES. Based on this information, the LSI tester 4 can identify each error measurement result for each input voltage from the received signal ES. As a result, the LSI tester 4 that has received the error measurement collection result signal ES for each input voltage creates an eye pattern (see FIG. 5) as described above, and the size of the eye opening of the eye pattern exceeds a desired value. Only when the semiconductor device 5 that has undergone the timing margin check test is determined to be non-defective.

  According to the configuration and operation of the present embodiment described above, the input voltage to the CDR circuit 12 is variable without being fixed only to the center value VDD / 2 of the voltage amplitude. In addition to the check, it is possible to check the timing margin for each input voltage to the CDR circuit 12. As a result, it is possible to execute a test of creating an eye pattern as illustrated in FIG. 5 and determining whether the semiconductor device 5 is good or bad, and it is possible to detect a defective product having an excessive or insufficient voltage margin.

  The signal from the differential buffers DA1 and DA2 is a differential signal between the signal VRx that is differential data and the external reference voltage signal Vref that is a DC signal. Uses only the rising edge of the differential signal VRx1, so there is no effect.

  In addition, the circuit portion composed of each of the constituent elements DA1, DA2, and 11 in the present embodiment is expressed as “the difference between the test pattern signal VRx output from the input buffer 10 and the external reference voltage signal Vref applied from the outside. It is defined as a “difference buffer unit for obtaining the signal VRx1”. The variable delay elements VDL1 and VDL2 are collectively referred to as “a phase changing unit that sequentially changes the relative phase relationship between the test pattern signal VRx output from the input buffer 10 and the second clock signal CLK2.” .

(Embodiment 2)
FIG. 7 is a block diagram showing an internal configuration of the Loopback BIST circuit 1 according to the present embodiment. In FIG. 7, the same reference numerals as those in FIG. 2 denote the same or equivalent components. Also in this embodiment, FIG. 1 is basically used. However, the signal Vref, the signal REQ, and the signal SEL in FIG. 1 are unnecessary. A feature of the present embodiment is that, instead of the external reference voltage signal Vref in FIG. 2, a code-specific reference voltage generator 30 capable of variably generating a reference voltage signal is provided in the Loopback BIST circuit 1. It is in the point. Accordingly, the selection signal SEL of the selector 11 is generated by the CPU 21, and the level change (“0” → “1”) is executed according to the count value of the counter 22 in the CPU 21.

  FIG. 8 is a diagram illustrating a configuration example of the per-code reference voltage generator 30. The reference generator 30 is formed of a ladder resistor, and the first and second differential buffers DA1 and DA2 are set with reference to the voltage corresponding to the code value of the reference voltage code selection signal CSEL output from the CPU 21 of FIG. Output to. At this time, the code value of the reference voltage code selection signal CSEL is counted by the counter 22 of the CPU 21. During normal operation, the CPU 21 outputs a reference voltage code selection signal CSEL that gives a code value of 0. Therefore, the level of the output signal of the reference voltage generator 30 for each code is always at the ground level, and the level of the pad PD6. Is held at “1”, resulting in VRx = VRx1.

  Moreover, the reference voltage code selection signal CSEL is also applied to the error measuring instrument 15 in FIG. As a result, the error measuring instrument (memory or the like) 15 holds the pattern comparison result of the timing margin check test for each code value of the reference voltage code selection signal CSEL.

  FIG. 9 is a timing chart showing an operation in which the Loopback BIST circuit 1 of FIG. 7 performs a timing margin check test for each reference voltage value. 9 differs from that of FIG. 6 in steps S7 and S8. That is, in step S7 of FIG. 9, the CPU 21 determines whether or not the code value of the signal CSEL counted by the internal counter 22 has reached the upper limit value, and when the code value has reached the upper limit value. Finish the timing margin check test. In step S8, the CPU 21 outputs an error measurement collection result signal ES for each code value from the error measuring instrument 15, and also displays information data indicating the correspondence between each code value and the reference voltage value in the LSI. Output to the tester 4.

  According to the Loopback BIST circuit 1 shown in FIG. 7, the pads (external terminals) PD5, PD6, and PD10 shown in FIG. 2 are not necessary, so that an advantage that an increase in the number of pins of the semiconductor device 5 can be avoided can be obtained. .

(Modification of Embodiment 2)
As shown in FIG. 7, the error measuring instrument 15 may output an error measurement collection result signal ES1 for each code value to the CPU 21 itself instead of outputting the signal ES from the pad PD9 to the LSI tester 4. . In this case, the determination unit 23 in the CPU 21 creates an eye pattern as shown in FIG. 5 on the basis of the error measurement collection result signal ES1 for each code value, instead of the LSI tester 4, and the obtained eye opening. The quality of the semiconductor device 5 is determined based on the width dimension.

  In this case, it is not necessary to process the test result for each applied reference voltage by an external device (such as an LSI tester), and the semiconductor device 5 itself can perform timing margin mapping for each reference voltage (code). It becomes.

(Appendix)
While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  The present invention is suitable for application to a product equipped with a SerDes high-speed IP such as PCIe or SATA.

FIG. 3 is a block diagram showing a circuit arrangement when performing a timing margin check test of the semiconductor device according to the first embodiment of the present invention. 1 is a block diagram showing a configuration of a Loopback BIST circuit in a semiconductor device according to a first embodiment of the present invention. It is a timing chart which shows operation | movement of a CDR circuit. It is a block diagram which shows the structure of the input part of a deserializer. It is a figure which shows an eye pattern result. It is a flowchart which shows the procedure of the timing margin check test in Embodiment 1 of this invention. It is a block diagram which shows the structure of the Loopback BIST circuit in the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure which shows the example of an internal structure of the reference voltage generator for every Code. It is a flowchart which shows the procedure of the timing margin check test in Embodiment 2 of this invention.

Explanation of symbols

  1 Loopback BIST circuit, 2 High-speed IO buffer, 3 Test jig, 4 LSI tester, 5 Semiconductor device, 10 Input buffer, DA1, DA2 Differential buffer, 11 Selector, 12 CDR circuit, 13 Deserializer, 14 Pattern comparator, 15 Error measuring device, 16 output buffer, 17 serializer, 18 PLL circuit, 20 pattern generator, 21 CPU, 23 determination unit, 30 Code reference voltage generator, VDL1, VDL2 variable delay element.

Claims (3)

A pattern generator for generating a test pattern signal which is a parallel signal;
A clock generation circuit for generating a first clock signal;
A serializer that converts the test pattern signal of the parallel signal into a test pattern signal of a serial signal in response to the first clock signal;
An output buffer for outputting a test pattern signal of the serial signal to an external loopback path;
An input buffer for receiving a test pattern signal transmitted through the external loopback path;
A difference buffer unit for obtaining a difference signal between a test pattern signal output from the input buffer and an external reference voltage signal applied from outside;
A CDR circuit that generates a second clock signal based on an edge of the differential signal;
A phase changing unit for sequentially changing a relative phase relationship between the test pattern signal output from the input buffer and the second clock signal;
A deserializer for converting a test pattern signal output from the input buffer according to the second clock signal into a test pattern signal of a parallel signal;
A pattern comparator for comparing the test pattern signal output by the deserializer and the comparison pattern signal to detect the presence or absence of an error;
An error measuring device for storing the presence or absence of the error for each relative phase relationship with respect to the value of the external reference voltage signal;
Every time the external reference voltage signal is changed and input from the outside, and every time the relative phase relationship between the test pattern signal output from the input buffer and the second clock signal is set, The pattern generator generates the test pattern signal.
Semiconductor device. A pattern generator for generating a test pattern signal which is a parallel signal;
A clock generation circuit for generating a first clock signal;
A serializer that converts the test pattern signal of the parallel signal into a test pattern signal of a serial signal in response to the first clock signal;
An output buffer for outputting a test pattern signal of the serial signal to an external loopback path;
An input buffer for receiving a test pattern signal transmitted through the external loopback path;
A reference voltage code selection signal generator for generating a reference voltage code selection signal;
A per-code reference voltage generator for generating a signal having a reference voltage corresponding to each code given by the reference voltage code selection signal;
A difference buffer unit for obtaining a difference signal between a test pattern signal output from the input buffer and a reference voltage signal output from the reference voltage generator for each code;
A CDR circuit that generates a second clock signal based on an edge of the differential signal;
A phase changing unit for sequentially changing a relative phase relationship between the test pattern signal output from the input buffer and the second clock signal;
A deserializer for converting a test pattern signal output from the input buffer according to the second clock signal into a test pattern signal of a parallel signal;
A pattern comparator for comparing the test pattern signal output by the deserializer and the comparison pattern signal to detect the presence or absence of an error;
An error measuring device for storing presence / absence of the error for each relative phase relationship with respect to each code given by the reference voltage code selection signal;
Each time the code of the reference voltage code selection signal is set and every time the relative phase relationship between the test pattern signal output from the input buffer and the second clock signal is set, the pattern The generator generates the test pattern signal,
Semiconductor device. The semiconductor device according to claim 2,
An eye pattern is created based on the presence or absence of the error output from the error measuring device, and further includes a determination unit that determines the semiconductor device as a non-defective product when the size of the eye opening of the eye pattern is equal to or greater than a predetermined value. To
Semiconductor device.

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