JP2001144819A - Quality evaluation device for digital signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely quantitatively grasp the waveform quality of a digital signal. SOLUTION: An upper envelope detection means 33 varies the threshold Vs of an analog comparator 21 in a state such that a reference signal with whole bits '0' is inputted to an error measuring unit 28, varies the delay time Td of a delay circuit 24 with respect to a clock signal CK, and obtains a coordinate point decided by the threshold Vs when an error rate E passes through a reference value and by delay time Td as the coordinate point of an upper envelope. A lower envelope detection means 34 varies the threshold Vs in a range where it crosses the lower envelope of the digital signal under the condition where the reference signal with whole bits '1' is inputted to the error measuring unit 28, varies delay time Td and obtains a coordinate point decided by the threshold Vs when the error rate E passes through the reference point and by delay time Td as the coordinate point of a lower envelope.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for evaluating the quality of a digital signal, and more particularly to a technique for accurately grasping the waveform quality of a digital signal.

[0002]

2. Description of the Related Art In various communication systems for transmitting digital signals, the waveform quality of the digital signals is degraded due to fluctuations in the characteristics of the transmission source of the digital signals and changes in the characteristics of the transmission path.

[0003] Deterioration of the waveform quality of a digital signal is caused by fluctuations in amplitude and bias and fluctuations in phase. In order to evaluate the waveform quality, a method of observing a waveform pattern using an oscilloscope has conventionally been used. Had been taken.

That is, when a digital signal is input to an oscilloscope and a sweep is triggered by a clock component of the digital signal, a waveform that changes from “0” to “1” and a waveform that changes from “1” to “0” Waveform, continuous waveform of "0", and continuous waveform of "1"
As shown in FIG. 8A, two lines L1 parallel to the time axis,
A waveform pattern composed of L2 and lines L3 and L4 intersecting in an X shape between the two lines L1 and L2 is observed.

[0005] This waveform pattern is generally called an eye pattern, and an eye pattern of a digital signal having good waveform quality with little fluctuation of amplitude and bias and fluctuation of phase is as follows.
As shown in FIG. 8B, each line L1 to L4 becomes thin.

[0008] Further, in an eye pattern of a digital signal having a lot of fluctuations in amplitude and bias and phase fluctuations and poor quality, each line L1 to L4 becomes thick as shown in FIG.

Therefore, by comparing this eye pattern with a reference eye pattern, it is possible to determine whether the waveform quality of the digital signal is good or bad.

This eye pattern comparison is performed by attaching an eye mask on which a reference eye pattern (for example, an eye pattern that matches the waveform pattern of FIG. 8A) is displayed on an oscilloscope screen, Whether the quality of the digital signal waveform is good or not is determined by whether the eye pattern is hidden or protruded by the eye pattern of the eye mask.

[0009]

However, as described above, the conventional method of observing a digital signal with an oscilloscope lacks accuracy, is likely to cause variations in evaluation by an observer, and furthermore, the waveform quality over time is poor. There is a problem in that it is not possible to know the state of the change or the like, and it is not possible to perform a quantitative evaluation.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problem and to provide a digital signal quality evaluation device capable of accurately and quantitatively grasping the digital signal waveform quality.

[0011]

In order to achieve the above object, a digital signal quality evaluation apparatus according to the present invention comprises an analog comparator (21) for comparing a voltage of a digital signal to be evaluated with a threshold voltage. ), A delay circuit (24) for delaying a clock signal input together with the digital signal to be evaluated, and a reading circuit (25) for reading the output level of the analog comparator with the clock signal delayed by the delay circuit. A selection circuit (27) for selectively outputting either the first reference signal of all bits 0 or the second reference signal of all bits 1
An error rate measuring device (28) for detecting a bit error between a signal output from the reading circuit and a signal output from the selection circuit, and measuring an error rate thereof; With the reference signal selected, the threshold is varied within a range intersecting the upper envelope of the digital signal, and the delay time is varied so that the error rate of the error rate An upper envelope detecting means (33) for obtaining a coordinate point consisting of a threshold value and a delay time when passing through the second reference signal; and selecting the second reference signal from the selection circuit and setting the threshold value The digital signal is varied within a range intersecting the lower envelope and the delay time is varied so that the error rate of the error rate measuring device is determined by a threshold value and a delay time when the error rate passes the reference value. Lower envelope for finding coordinate points And detection means (34), the display device (4
1) and displaying the upper envelope detected by the upper envelope detecting means and the lower envelope detected by the lower envelope detecting means on coordinates of a time axis and a voltage axis of the display device. Waveform display means (35).

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a digital signal quality evaluation device 20 according to an embodiment of the present invention.

The quality evaluation device 20 has a first input terminal 20a for inputting a digital signal A to be evaluated.
And a second input terminal 20b for inputting a clock signal CK for binary determination of the digital signal A.

Here, the digital signal A to be evaluated is a PN pattern signal (pseudo random signal) having a predetermined length.

The digital signal input to the first input terminal 20a is input to one terminal of an analog comparator 21.

The analog comparator 21 compares the analog threshold value Vs output from the D / A converter 22 with the voltage of the digital signal A, and when the voltage of the digital signal A is equal to or higher than the threshold value Vs. A high-level signal is output, and a low-level signal is output when the voltage of the digital signal A is lower than the threshold value Vs.

The D / A converter 22 includes a control unit 30 described later.
Output the specified threshold value Vs.

On the other hand, the clock signal CK input to the second input terminal 20b is input to the frequency detection circuit 23 and the delay circuit 24.

The frequency detection circuit 23 detects the frequency of the clock signal CK and outputs it to the control unit 30.
Outputs a clock signal CK ′ obtained by delaying the clock signal CK by a delay time Td specified by the control unit 30.

The output signal A 'of the analog comparator 21
And the clock signal CK 'from the delay circuit 24 is input to the reading circuit 25.

The reading circuit 25 reads and outputs the binary level of the output signal A 'of the analog comparator 21 at the rising timing of the clock signal CK'.

The reference pattern signal generation circuit 26 generates a reference pattern signal K having the same pattern as the normal pattern of the input digital signal in synchronization with the clock signal CK '.

When receiving a pull-in instruction from the control unit 30, which will be described later, the reference pattern signal generation circuit 26 fetches a predetermined number of bits of the output signal A "of the reading circuit 25 and sets it internally as an initial value. From the value, a code (PN code) synchronized with the clock signal CK 'is sequentially output by the same generation process as the input digital signal A.

The selection circuit 27 includes a reference pattern signal K,
The first reference signal J1 which is always “0” and the second reference signal J1 which is always “1”
Out of the reference signal J2 of FIG.

The error measuring device 28 detects a bit error between the output signal A ″ of the reading circuit 25 and the reference signal output from the selecting circuit 27, and calculates an error rate E for each predetermined time.
Output to the control unit 30.

The control unit 30 is constituted by a microcomputer including a CPU, a ROM, and a RAM. The control unit 30 has a control mode for waveform measurement and a control mode for bit error measurement, and executes the control mode specified by the operation of the operation unit 40.

That is, when the waveform measurement is designated by operating the operation unit 40 or the like, the threshold of the analog comparator 21 is received while receiving the frequency F detected by the frequency detection circuit 23 and the error rate E from the error measuring device 28. Variable of value Vs and delay time Td of delay circuit 24 and selection circuit 27
Are switched in a predetermined order, data necessary for quality evaluation of the waveform of the digital signal A is obtained, and the result is displayed on the display device 41.

When the bit error measurement is specified,
The threshold value Vs and the delay time Td specified by the operation of the operation unit 40 are set in the analog comparator 21 and the delay circuit 24, and the selection circuit 27 outputs the reference pattern signal K. Is performed, and the result is displayed on the display device 41.

As shown in FIG. 1, the control unit 30 includes a period calculating unit 31, an error-free area detecting unit 32, an upper envelope detecting unit 33, a lower envelope detecting unit 34, and a waveform displaying unit 35. And a bit error measurement control unit 37.

The period calculating means 31 includes a frequency detecting circuit 23
The period T is calculated from the frequency of the clock signal CK detected by the above.

The error-free area detection means 32 selects the reference pattern signal K from the selection circuit 27, and monitors the error rate E measured by the error rate measuring device 28 while comparing the threshold value Vs and the delay time Td. The threshold value Vs and the delay time Td when the error rate E passes the reference value Er
Is determined as a read coordinate point P that determines the boundary between the area where the error rate E is smaller than the reference value Er and the area where the error rate E is equal to or more than the reference value Er, and is stored in a memory (not shown).

The upper envelope detection means 33 includes a selection circuit 27
, The first reference signal J1 of “0” is always selected, and while monitoring the error rate E measured by the error rate measuring device 28, the threshold value Vs is varied within a range intersecting the upper envelope of the digital signal. At the same time, the delay time Td is varied by at least one cycle T of the digital signal, so that the threshold Vs and the delay time Td when the error rate E passes the reference value Er.
That is, the read coordinate point Q that determines the boundary between the area where the error rate E is smaller than the reference value Er and the area where the error rate E is equal to or more than the reference value Er is determined by the coordinates of the upper envelope of the input digital signal. And stored in a memory (not shown).

The lower envelope detection means 34 includes a selection circuit 27
, The second reference signal J2 of “1” is always selected, and while monitoring the error rate E measured by the error rate measuring device 28, the threshold value Vs is set within a range intersecting the lower envelope of the digital signal. The threshold value Vs and the delay time Td when the error rate E passes the reference value Er are varied while the delay time Td is varied by at least one cycle T of the digital signal.
That is, the read coordinate point R determined by the threshold value Vs and the delay time Td that determine the boundary between the area where the error rate E is smaller than the reference value Er and the area where the error rate E is equal to or more than the reference value Er.
Is obtained as the coordinates of the lower envelope of the input digital signal and stored in a memory (not shown).

The waveform display means 35 displays the time on the horizontal axis and the rectangular coordinates of the voltage on the vertical axis on the display device 41, and displays, on this coordinate plane, each reference value obtained by the error-free area detection means 32. , The read coordinates P of the upper envelope detected by the upper envelope detector 33 and the read coordinates R of the lower envelope detected by the lower envelope detector 34 are plotted and input. The upper and lower envelopes of the digital signal, and the error-free region, that is,
To enable the eye pattern of a digital signal to be grasped on a screen.

The height of each error-free area of the eye pattern (bias margin) is calculated by the waveform display means 35.
And the width (phase margin), the distance between the upper and lower envelopes, the amount of overshoot, and the like are calculated and numerically displayed together with the eye pattern.

As described above, the bit error measurement control means 37 controls the threshold V specified by the operation of the operation unit 40 or the like.
s and the delay time Td are set in the analog comparator 21 and the delay circuit 24, the reference pattern signal K is output from the selection circuit 27, and a specified error rate measurement is performed by the error measuring device 28, and the result is displayed on a display device. 41 is displayed.

Next, the operation of the quality evaluation device 20 will be described. FIG. 2 is a flowchart illustrating an example of a processing procedure of the error-free area detection unit 32. The operation of detecting an error-free area will be described with reference to the flowchart below.

First, a variable i designating the reference value Er (i) of the error rate is initialized to 0, the delay time Td is set to the period T calculated by the period detecting means 31, and the threshold value Vs is set. Intermediate value Va of nominal high-level voltage VH and low-level voltage VL of digital signal A = (VH + VL) / 2
(S1, S2).

Here, the reference value Er (i) of the error rate is Er
(0) to Er (3), for example, the reference value Er
(0) is 1 / 8th power, reference value Er (1) is 1 / 10th power, reference value Er (2) is 1 / 10th power,
The reference value Er (3) is set to one tenth of the eleventh power.

In this state, the threshold value Vs and the delay time T
As shown in FIG. 3, the read coordinate point P determined by d is located substantially at the center of the eye pattern I (A) of the digital signal, and the signal output from the read circuit 25 is the input digital signal. And the same pattern.

Then, the control unit 30 instructs the reference pattern signal generation circuit 26 to perform the pull-in, and the selection circuit 2
7 is instructed to output a signal from the reference pattern signal generation circuit 26 (S3, S4).

The reference pattern signal generating circuit 26, which has received the pull-in instruction from the control unit 30, takes in the digital signal output from the reading circuit 25 for a predetermined number of bits and sets it internally as an initial value. Clock signal C by the same generation process as the digital signal
Codes synchronized with K 'are sequentially output.

If there is no code error in the signal captured by the reference pattern signal generation circuit 26, the signal K output from the reference pattern signal generation circuit 26 matches the normal pattern of the input digital signal. The error rate E measured by the error rate measuring device 28 is a reference value Er.
(I) It is smaller.

The control unit 30 determines that the error rate E is equal to the reference value Er.
(I) It is confirmed that the value has become smaller, and it is determined that synchronization has been confirmed (S5). If the synchronization is not determined, it is assumed that there is a code error in the captured digital signal.
A redraw instruction is issued again.

After the synchronization is determined in this way, the control unit 30 raises the threshold value Vs from Va by ΔV steps while monitoring the error rate E from the error measuring device 28, and (a) in FIG. ), The error rate E is equal to the reference value Er.
The read coordinate point Pa (i) determined by the threshold value Vs and the delay time Td immediately before exceeding (i) is stored (S6).

While monitoring the error rate E from the error measuring device 28, the threshold value Vs is decreased from Va by ΔV steps at a time, and as shown in FIG.
The read coordinate point Pb (i) determined by the threshold Vs immediately before exceeding r (i) and the delay time Td is stored (S7).

As described above, the error rate E becomes equal to the reference value Er.
(I) When the upper and lower read coordinate points Pa (i) and Pb (i) at the delay time Td = T in the lower region are obtained, the control unit 30 increases the delay time Td from T by ΔT. By repeating the same processing as described above, the upper and lower reading coordinate points Pa (i) and Pb (i) for each delay time in the region where the error rate E is lower than the reference value Er are determined at one end of this region. (S8, S9).

Next, the delay time Td is decreased by ΔT from T, and the reading coordinate points Pa (i) of the upper limit and the lower limit for each delay time in the region where the error rate E is lower than the reference value Er (i),
Pb (i) is obtained until it reaches the other end of this area (S10 to S14).

Thus, the error rate E becomes equal to the reference value Er.
(I) Each read coordinate point Pa for determining the lower area
(I), Pb (i) (collectively referred to as P (i))
Can be obtained.

Hereinafter, the same processing is performed by the reference values Er (1) to E (E).
r (3), and the error rate E becomes equal to each reference value Er.
The read coordinate points P (0) to P (3) that respectively determine the areas lower than (0) to Er (3) are obtained (S15, S15).
16).

Next, the operation of the upper envelope detecting means 33 and the lower envelope detecting means 34 will be described with reference to the flowchart of FIG.

First, the threshold value Vs is ΔV smaller than the maximum value Vp (max) of the threshold value Vs of the read coordinates P (0) obtained for the reference value E (0) in the error-free area detection processing. After the voltage is set to the large voltage Vb, the delay time Td is set to T / 2, and the reference value Er of the error rate is set to E (0), the selection circuit 27 always outputs “0”, that is, all bits 0 1 is selected (S21, S21).
22).

At this time, the read coordinate point Q 'is located at a position where the error rate slightly exceeds the area of the reference value Er (0), as shown in FIG. 28
Are all 0s, the error rate E at this time is a value that greatly exceeds the reference value Er (0).

Here, while monitoring the error rate E from the error measuring device 28, the threshold value Vs is increased by ΔV steps from Vb, and reading is performed immediately before the error rate E becomes smaller than the reference value Er (0). The coordinate point Q is stored as the coordinates of the upper envelope at the delay time Td = T / 2 (S23).

That is, when the threshold value Vs rises and exceeds the upper envelope B of the digital signal, the output of the reading circuit 25 becomes all bits 0, and all bits coincide with the reference signal J1, and the error rate E becomes the reference value. It becomes smaller than Er (0). Therefore, the read coordinate point Q immediately before the point substantially indicates a point on the upper envelope B of the digital signal.

Hereinafter, the same processing is performed by setting the delay time Td to 3T /
The coordinates of the upper envelope B for one cycle of the digital signal A are obtained by repeating the process while increasing the value by ΔT every 2 (S24, S25).

Next, the threshold value Vs is the minimum value Vp (min) of the threshold value Vs of the read coordinate point P (0) obtained for the reference value Er (0) in the error-free area detection processing.
Is set to a voltage Vc smaller by ΔV than the delay time Td
Is set to T / 2, the selection circuit 27 always selects "1", that is, the second reference signal J2 of all bits 1 (S26, S27).

In this state, the read coordinate point R 'is located at a position where the error rate slightly exceeds the area of the reference value Er (0) as shown in FIG. Container 28
Are all 1s, the error rate E at this time is a value that greatly exceeds the reference value Er (0).

Here, while monitoring the error rate E from the error measuring device 28, the threshold Vs is decreased by ΔV steps from Vc, and the read coordinates immediately before the error rate E becomes smaller than the reference value Er (0) are read. The point R is stored as the coordinates of the lower envelope at the delay time Td = T / 2 (S28).

That is, when the threshold value Vs decreases and falls below the lower envelope C of the digital signal, the output of the reading circuit 25 becomes all bits 1 and all bits match the reference signal J2.
The error rate E becomes smaller than the reference value Er (0). Therefore, the read coordinate point R immediately before this point substantially indicates a point on the lower envelope C of the digital signal.

Hereinafter, the same processing is performed by setting the delay time Td to 3T /
The coordinates of the lower envelope C for one cycle of the digital signal A are obtained by repeating the process while increasing the value by ΔT every time 2 (S29, 30).

In this way, when the coordinate point P for determining the error-free area of the digital signal A and the coordinate points Q and R for determining the upper envelope B and the lower envelope C are obtained, the waveform display means 35 The eye pattern of the digital signal is displayed on the display device 41 as shown in FIG.

The eye pattern reference value Er
The height H (bias margin) and width W (phase margin) of the error-free region corresponding to (0), the distance L between the upper and lower envelopes B and C, the amount of overshoot OS, and the like are calculated and displayed numerically together with the eye pattern. Is done.

Therefore, compared with a method of simply observing a digital signal with an oscilloscope, the eye pattern can be grasped more accurately, the characteristic value of the pattern can be easily known, and the waveform quality of the digital signal can be more accurately measured. And quantitatively.

Since each coordinate point and characteristic value for determining the eye pattern are stored in the memory, it is possible to numerically compare the changes between the eye patterns obtained at different times.

In the above description, the processing for detecting the error-free area and the processing for detecting the upper and lower envelopes involve the delay time T
While the threshold Vs is varied by ΔV in a state where d is fixed, each coordinate point is obtained. Conversely, the delay time Td is varied by ΔT in a state where the threshold Vs is fixed, and each coordinate point is obtained. Alternatively, either the upper envelope or the lower envelope may be determined first.

Although not described in detail, when the bit error measurement is specified by operating the operation unit 40, the threshold Vs and the delay time Td specified by the operation unit 40 are compared with the analog comparator 21 and the delay circuit. Set to 23,
The reference pattern signal K is selected, the pull-in process is performed in the same manner as described above, the error rate is measured continuously for a specified time after the synchronization is determined, and the measurement result is displayed on the display device 42.

That is, the quality evaluation device 20 detects and displays the free error region and the upper and lower envelopes of the digital signal using substantially the same hardware as the measuring device for measuring the bit error. Therefore, there is an advantage that it can be shared with the bit error measuring device, and the evaluation of the waveform and the error rate of the digital signal can be performed by one device without complicating the configuration.

[0069]

As described above, the digital signal quality evaluation apparatus of the present invention receives an analog comparator for comparing the voltage of a digital signal to be evaluated with a threshold voltage, and receives the digital signal together with the digital signal. A delay circuit for delaying a clock signal, a reading circuit for reading an output level of an analog comparator with a clock signal delayed by the delay circuit, and a first reference signal for all bits 0 and a second reference signal for all bits 1 An error rate measuring device for detecting a bit error between a selection circuit for selectively outputting a signal and a signal output from a reading circuit and measuring an error rate thereof, and a state in which a first reference signal is selected from the selection circuit The threshold value is varied within a range intersecting with the upper envelope of the digital signal, and the delay time is varied so that the error rate is equal to a predetermined reference value. An upper envelope detecting means for obtaining a coordinate point consisting of a threshold value and a delay time at the time of passing as a coordinate point of an upper envelope of the digital signal, and a state where the second reference signal is selected from the selection circuit. The threshold value is varied within a range intersecting the lower envelope of the digital signal and the delay time is varied so that the coordinate point determined by the threshold value and the delay time when the error rate passes the reference value is determined by the digital signal. A lower envelope detecting means obtained as a coordinate point of the lower envelope, and an upper envelope detected by the upper envelope detecting means and a lower envelope detected by the lower envelope detecting means. Waveform display means for displaying on a coordinate comprising a time axis and a voltage axis.

For this reason, the waveform quality of the digital signal can be grasped accurately and quantitatively as compared with the conventional method of observing the digital signal with an oscilloscope.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure of a main part of the embodiment.

FIG. 3 is a diagram for explaining an eye pattern of a digital signal and an operation of the embodiment;

FIG. 4 is a schematic diagram for explaining the operation of the embodiment;

FIG. 5 is a flowchart showing a processing procedure of a main part of the embodiment.

FIG. 6 is a schematic diagram for explaining the operation of the embodiment;

FIG. 7 is a diagram showing a display example of the embodiment.

FIG. 8 is a diagram showing an eye pattern of a digital signal.

[Explanation of symbols]

 Reference Signs List 20 quality evaluation device 20a, 20b input terminal 21 analog comparator 22 D / A converter 23 frequency detection circuit 24 delay circuit 25 reading circuit 26 reference pattern signal generation circuit 27 selection circuit 28 error rate measurement device 30 control unit 31 cycle calculation means 32 Error-free area detection means 33 Upper envelope detection means 34 Lower envelope detection means 35 Waveform display means 37 Bit error measurement control means 40 Operation unit 41 Display device

[Procedure amendment]

[Submission Date] July 17, 2000 (2007.1)
7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

In order to achieve the above object, a digital signal quality evaluation apparatus according to the present invention comprises an analog comparator (21) for comparing a voltage of a digital signal to be evaluated with a threshold voltage. ), A delay circuit (24) for delaying a clock signal input together with the digital signal to be evaluated, and a reading circuit (25) for reading the output level of the analog comparator with the clock signal delayed by the delay circuit. A selection circuit (27) for selectively outputting either the first reference signal of all bits 0 or the second reference signal of all bits 1
An error rate measuring device (28) for detecting a bit error between a signal output from the reading circuit and a signal output from the selection circuit, and measuring an error rate thereof; With the reference signal selected, the threshold is varied within a range intersecting the upper envelope of the digital signal, and the delay time is varied so that the error rate of the error rate An upper envelope detection means (33) for obtaining an upper envelope indicated by a threshold value and a delay time when the signal passes through the threshold value, and the threshold value when the second reference signal is selected from the selection circuit. Is varied within a range intersecting the lower envelope of the digital signal, and the delay time is varied to indicate a threshold value and a delay time when the error rate of the error rate measuring instrument passes the reference value. Beneath
A lower envelope detector means for obtaining a lateral envelope (34), a display unit (41), the upper envelope lower envelope detected by the detected upper envelope and the lower envelope detection means by the detecting means and a waveform display means for displaying on the coordinates of the display device (35) line.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0069

[Correction method] Change

[Correction contents]

[0069]

As described above, the digital signal quality evaluation apparatus of the present invention receives an analog comparator for comparing the voltage of a digital signal to be evaluated with a threshold voltage, and receives the digital signal together with the digital signal. A delay circuit for delaying a clock signal, a reading circuit for reading an output level of an analog comparator with a clock signal delayed by the delay circuit, and a first reference signal for all bits 0 and a second reference signal for all bits 1 An error rate measuring device for detecting a bit error between a selection circuit for selectively outputting a signal and a signal output from a reading circuit and measuring an error rate thereof, and a state in which a first reference signal is selected from the selection circuit The threshold value is varied within a range intersecting with the upper envelope of the digital signal, and the delay time is varied so that the error rate is equal to a predetermined reference value. Threshold and delay time as it passes through
An upper envelope detector for determining the upper envelope shown in,
In a state where the second reference signal is selected from the selection circuit, the threshold value is changed in a range intersecting the lower envelope of the digital signal and the delay time is changed so that the error rate passes the reference value. lower the envelope detecting means, the lower is detected by the upper envelope and the lower envelope detection means detected by the upper envelope detector side for determining the lower envelope shown in thresholds and delay time when Waveform display means for displaying the envelope on coordinates of the display device on the time axis and the voltage axis is provided.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA09 AD06 AD07 AG07 5K014 AA01 EA01 EA08 FA09 GA02 GA03 5K029 AA03 BB01 FF05 HH11 KK25 LL08 9A001 BZ04 LL08

Claims (1)

[Claims] An analog comparator for comparing a voltage of a digital signal to be evaluated with a threshold voltage, and a delay circuit for delaying a clock signal input together with the digital signal to be evaluated. A reading circuit (25) for reading an output level of the analog comparator by a clock signal delayed by the delay circuit; and a reading circuit (25) for reading any one of the first reference signal of all bits 0 and the second reference signal of all bits 1 Selection circuit (2
7), an error rate measuring device (28) for detecting a bit error between a signal output from the reading circuit and a signal output from the selecting circuit, and measuring an error rate thereof; With the reference signal of No. 1 selected, the threshold value is varied within a range intersecting the upper envelope of the digital signal, and the delay time is varied so that the error rate of the error rate An upper envelope detection means (33) for obtaining a coordinate point consisting of a threshold value and a delay time when passing a reference value, and the threshold value in a state where the second reference signal is selected from the selection circuit. The value is varied within a range intersecting the lower envelope of the digital signal, and the delay time is varied so that a threshold value and a delay time when the error rate of the error rate measuring device passes the reference value are obtained. Find the coordinate point determined by An envelope detecting means (34); a display device (41); and an upper envelope detected by the upper envelope detecting means and a lower envelope detected by the lower envelope detecting means. An apparatus for evaluating the quality of a digital signal, comprising: a waveform display means (35) for displaying on a coordinate system comprising a time axis and a voltage axis.