TWI760134B - 包含多襯墊半導體穿孔的半導體結構及其形成方法 - Google Patents
包含多襯墊半導體穿孔的半導體結構及其形成方法 Download PDFInfo
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- TWI760134B TWI760134B TW110108221A TW110108221A TWI760134B TW I760134 B TWI760134 B TW I760134B TW 110108221 A TW110108221 A TW 110108221A TW 110108221 A TW110108221 A TW 110108221A TW I760134 B TWI760134 B TW I760134B
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- 238000000034 method Methods 0.000 title claims abstract description 154
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 230000008569 process Effects 0.000 claims abstract description 136
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 238000000151 deposition Methods 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000227 grinding Methods 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 238000000137 annealing Methods 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 205
- 229910052751 metal Inorganic materials 0.000 description 52
- 239000002184 metal Substances 0.000 description 52
- 241000724291 Tobacco streak virus Species 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 239000000463 material Substances 0.000 description 22
- 229910052581 Si3N4 Inorganic materials 0.000 description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 13
- 229910010271 silicon carbide Inorganic materials 0.000 description 12
- 238000002955 isolation Methods 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 9
- 229920000642 polymer Polymers 0.000 description 9
- 239000007789 gas Substances 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000002243 precursor Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 239000003361 porogen Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- REJKHFAZHZLNOP-UHFFFAOYSA-N (tert-butylamino)silicon Chemical compound CC(C)(C)N[Si] REJKHFAZHZLNOP-UHFFFAOYSA-N 0.000 description 1
- UJMDDKJVWXXLIV-UHFFFAOYSA-N 1-(4-fluorophenyl)-4-(4-hydroxy-4-methylpiperidin-1-yl)butan-1-one Chemical compound C1CC(C)(O)CCN1CCCC(=O)C1=CC=C(F)C=C1 UJMDDKJVWXXLIV-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
一種形成半導體結構的方法包含:蝕刻基底以形成開口、
沉積延伸至開口中的第一介電襯墊、以及將第二介電襯墊沉積在第一介電襯墊上方。第二介電襯墊延伸至開口中。將導電材料填充至開口中。方法更包含:執行第一平坦化製程以使導電材料平坦化,使得開口中的導電材料的一部分形成穿孔、對基底執行背側研磨製程,直到穿孔自基底的背側顯露為止、以及在基底的背側上形成導電特徵。導電特徵電性連接至穿孔。
Description
本發明的實施例是有關於一種半導體結構及其形成方法,且特別是關於一種包含多襯墊半導體穿孔的半導體結構及其形成方法。
矽穿孔(Through-Silicon Via)作為裝置晶粒中的導電路徑,使得裝置晶粒的相對側上的導電特徵可內連。
根據一些實施例,一種形成半導體結構的方法包括:蝕刻基底以形成開口、沉積延伸至所述開口中的第一介電襯墊、將第二介電襯墊沉積在所述第一介電襯墊上方,其中所述第二介電襯墊延伸至所述開口中、將導電材料填充至所述開口中、執行第一平坦化製程以使所述導電材料平坦化,其中所述開口中的所述導電材料的一部分形成穿孔、對所述基底執行背側研磨製程,直至所述穿孔自所述基底的背側顯露為止、以及在所述基底的所述背側上形成導電特徵,其中所述導電特徵電連接至所述穿孔。
根據一些實施例,一種半導體結構包括:半導體基底、位於所述半導體基底的第一側上的第一導電特徵、位於所述半導體基底的第二側上的第二導電特徵、穿透所述半導體基底的穿孔、環繞所述穿孔的第一介電襯墊、以及環繞所述第一介電襯墊的第二介電襯墊,其中所述穿孔將所述第一導電特徵及所述第二導電特徵電性內連,所述第一介電襯墊及所述第二介電襯墊由不同材料形成,並且所述第二介電襯墊具有比所述第一介電襯墊更佳的濕氣隔離能力。
根據一些實施例,一種半導體結構包括晶粒,所述晶粒包括:半導體基底、位於所述半導體基底上方的多個低介電係數介電層、位於所述低介電係數介電層上方的非低介電係數鈍化層、穿透所述半導體基底、所述低介電係數介電層以及所述非低介電係數鈍化層的穿孔、環繞所述穿孔的多層介電襯墊、位於所述非低介電係數鈍化層上方且在所述晶粒的頂部表面處的第一電連接件、以及位於所述半導體基底之下且在所述晶粒的底部表面處的第二電連接件,其中所述第一電連接件及所述第二電連接件經由所述穿孔電性內連。
20:晶圓
22:晶片/晶粒
24:半導體基底
24A:頂部表面
25、38、38A、44、72、76:介電層
26:積體電路裝置
28:層間介電質
30:接觸插塞
32:內連線結構
34:金屬線
34A、36、59:通孔
37、40:蝕刻終止層
42、64:鈍化層
46:蝕刻罩幕
48:開口
48E:邊緣
50:第一介電襯墊
52:第二介電襯墊
54:晶種層
56:導電材料
58:退火製程
58':隆起
60:隔離層
61:半導體穿孔(TSV)
62:金屬墊
66:聚合物層
68:凸塊下金屬
70、78、92:電連接件
74:重佈線路層(RDL)
80:切割道
84:封裝組件
86:扇出型重佈線結構
88:包封體
90:穿孔
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230:製程
DS50、DS52:密度
H1/W1:高寬比
T1、T2:厚度
W1:頂部寬度
W2:底部寬度
α:下傾角
當結合附圖閱讀時,自以下詳細描述最佳地理解本揭露的態樣。應注意,根據業界中的標準慣例,各種特徵未按比例繪製。實際上,可為了論述清楚起見而任意地增大或減小各種特徵的尺寸。
圖1至圖16示出了根據一些實施例的形成包含穿孔的裝置晶
粒的中間階段的剖面圖。
圖17至圖22示出了根據一些實施例的形成包含穿孔的中介物的中間階段的剖面圖。
圖23示出了根據一些實施例的多襯墊穿孔的平面圖。
圖24示出了根據一些實施例的包含裝置晶粒的三維(three-dimensional;3D)積體電路(Integrated Circuit;IC)。
圖25示出了根據一些實施例的用於形成包含多襯墊穿孔的裝置晶粒的製程流程。
以下揭露提供用於實施本發明的不同特徵的多個不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然,此等特定實例僅為實例且不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例,並且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露可在各種實例中重複附圖標記及/或字母。此重複是出於簡單及清楚的目的,並且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外,為易於描述,可在本文中使用諸如「在...之下(underlying)」、「在...下方(below)」、「下部(lower)」、「上覆(overlying)」、「上部(upper)」以及其類似者的空間相對術語以描述一個部件或特徵與另一部件或特徵的關係,如圖中所示出。除圖中所描繪的定向之外,空間相對術語亦意欲涵蓋元件在使用或
操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向),並且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例提供一種包含多襯墊穿孔(multi-liner through-via)的晶粒及其形成方法。晶粒包含多個介電襯墊,所述介電襯墊由不同材料形成。舉例而言,外部襯墊可由氮化矽、碳化矽或氮氧化矽形成,並且內部襯墊可由氧化矽形成。多個襯墊可用作不同的功能。舉例而言,外部襯墊可具有良好耐濕氣性以用於防止濕氣到達低介電係數(以下簡稱低k)介電層及金屬線。內部襯墊可具有低洩漏。根據一些實施例示出形成裝置晶粒的中間階段並說明一些實施例的一些變化。在各個視圖及說明性實施例中,相似的附圖標號用於指代相似部件。
圖1至圖16示出了根據本揭露的一些實施例的形成包含穿孔的裝置晶粒的中間階段的剖面圖。對應的製程亦示意性地反映在如圖25所示的製程流程200中。
圖1示出了晶圓20的剖面圖。根據本揭露的一些實施例,晶圓20為或包括裝置晶圓,所述裝置晶圓包含主動裝置及可能的被動裝置,所述主動裝置及被動裝置表示為積體電路裝置26。晶圓20中可包含多個晶片/晶粒22,其中示出了晶片22中的一者。根據本揭露的替代性實施例,晶圓20是中介物晶圓(interposer wafer),其不含主動裝置且可包含或可不包含被動裝置。
根據本揭露的一些實施例,晶圓20包含半導體基底24及形成於半導體基底24的頂部表面處的特徵。半導體基底24可
由結晶矽、結晶鍺、矽鍺、碳摻雜矽或III-V化合物半導體形成或包括結晶矽、結晶鍺、矽鍺、碳摻雜矽或III-V化合物半導體,所述III-V化合物半導體諸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其類似者。淺溝渠隔離(Shallow Trench Isolation;STI)區(未繪示)可形成於半導體基底24中,以隔離半導體基底24中的主動區。
根據本揭露的一些實施例,晶圓20包含積體電路裝置26,所述積體電路裝置26形成於半導體基底24的頂部表面上。根據一些實施例,積體電路裝置26可包含互補金屬氧化物半導體(Complementary Metal-Oxide Semiconductor;CMOS)電晶體、電阻器、電容器、二極體以及其類似者。本文中未示出積體電路裝置26的細節。根據替代性實施例,晶圓20用於形成中介物(其不含主動裝置),並且基底24可為半導體基底或介電基底。
層間介電質(Inter-Layer Dielectric;ILD)28形成於半導體基底24上方且填充積體電路裝置26中的電晶體(未繪示)的閘極堆疊之間的間隔。根據一些實施例,ILD 28由氧化矽、磷矽酸鹽玻璃(Phosphosilicate Glass;PSG)、硼矽酸鹽玻璃(Borosilicate Glass;BSG)、硼摻雜磷矽酸鹽玻璃(Boron-doped Phosphosilicate Glass;BPSG)、氟摻雜矽酸鹽玻璃(Fluorine-doped Silicate Glass;FSG)或其類似者形成。ILD 28可使用旋塗、可流動化學氣相沉積(Flowable Chemical Vapor Deposition;FCVD)或其類似者形成。根據本揭露的一些實施例,ILD 28亦可使用沉積方法(如電漿增強式化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition;PECVD)、低壓化學氣相沉積(Low Pressure
Chemical Vapor Deposition;LPCVD)或其類似者)形成。
接觸插塞30形成於ILD 28中,並且用於將積體電路裝置26電性連接至上面的金屬線及通孔。根據本揭露的一些實施例,接觸插塞30由導電材料形成或包括導電材料,所述導電材料選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或其多層。接觸插塞30的形成可包含在ILD 28中形成接觸開口,將導電材料填充至接觸開口中,以及執行平坦化製程(諸如化學機械研磨(Chemical Mechanical Polish;CMP)製程或機械研磨製程),以使接觸插塞30的頂部表面與ILD 28的頂部表面齊平。
在ILD 28及接觸插塞30上方駐存有內連線結構32。內連線結構32包含金屬線34及通孔36,金屬線34及通孔36形成於介電層38(亦稱為金屬間介電質(Inter-metal Dielectric;IMD))及蝕刻終止層37中。處於相同層級的金屬線在下文中統稱為金屬層。根據本揭露的一些實施例,內連線結構32包含多個金屬層,所述多個金屬層包含藉由通孔36內連的金屬線34。金屬線34及通孔36可由銅或銅合金形成,亦可由其他金屬形成。根據本揭露的一些實施例,介電層38由低k介電材料形成。舉例而言,低k介電材料的介電係數(k值)可小於約3.0。介電層38可包括含碳低k介電材料、氫倍半氧矽烷(Hydrogen SilsesQuioxane;HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane;MSQ)或其類似者。根據本揭露的一些實施例,介電層38的形成包含將含成孔劑(porogen-containing)的介電材料沉積在介電層38中,隨後執行固化製程以排除成孔劑,從而剩餘的介電層38為多孔的。蝕刻終止層37可由氮化矽、碳化矽、碳氧化矽、氮氧化矽或其類似者形
成或包括氮化矽、碳化矽、碳氧化矽、氮氧化矽或其類似者。
金屬線34及通孔36在介電層38中的形成可包含單金屬鑲嵌製程及/或雙金屬鑲嵌製程。在用於形成金屬線或通孔的單金屬鑲嵌製程中,溝渠或通孔開口首先形成於介電層38中的一者中,接著用導電材料填充溝渠或通孔開口。隨後執行如CMP製程的平坦化製程,以移除高於介電層的頂部表面的導電材料的過量部分,從而在對應的溝渠或通孔開口中留下金屬線或通孔。在雙金屬鑲嵌製程中,溝渠及通孔開口兩者皆形成於介電層中,其中通孔開口在溝渠之下且連接至所述溝渠。隨後,導電材料分別填充至溝渠及通孔開口中以形成金屬線及通孔。導電材料可包含擴散障壁層以及擴散障壁層上方的含銅金屬材料。擴散障壁層可包含鈦、氮化鈦、鉭、氮化鉭或其類似者。
金屬線34包含在頂部介電層(表示為介電層38A)中的頂部導電(金屬)特徵,諸如金屬線、金屬墊或通孔(表示為34A),所述頂部介電層為介電層38的頂部層。根據一些實施例,介電層38A由類似於介電層38中下部介電層的材料的低k介電材料形成。頂部介電層38A中的金屬線34亦可由銅或銅合金形成,並且可具有雙金屬鑲嵌結構或單金屬鑲嵌結構。
根據一些實施例,蝕刻終止層40沉積於頂部介電層38A及頂部金屬層上。蝕刻終止層40可由氮化矽、碳化矽、碳氧化矽、氮氧化矽或其類似者形成或包括氮化矽、碳化矽、碳氧化矽、氮氧化矽或其類似者。
鈍化層42(有時稱為鈍化-1(passivation-1或pass-1)形成於蝕刻終止層40上方。根據一些實施例,鈍化層42由具有大
於氧化矽的介電常數的介電常數的非低k介電材料形成。鈍化層42可由無機介電材料形成或包括無機介電材料,所述無機介電材料可包含選自但不限於以下的材料:未摻雜矽酸鹽玻璃(Undoped Silicate Glass;USG)、氮化矽(silicon nitride;SiN)、氧化矽(silicon oxide;SiO2)、氮氧化矽(silicon oxy-nitride;SiON)、碳氧化矽(silicon oxy-carbide;SiOC)、碳化矽(silicon carbide;SiC)或其類似者、其組合以及其多層。根據一些實施例,頂部介電層38A的頂部表面及其中的金屬線34共面。因此,鈍化層42可為平面層。
根據一些實施例,介電層44沉積於鈍化層42上方。相應的製程在如圖25中所示的製程流程200中示出為製程202。介電層44由與鈍化層42的材料不同的材料形成或包括所述材料,並且可由SiC、SiN、SiON、SiOC或其類似者形成或包括SiC、SiN、SiON、SiOC或其類似者。
參考圖2,形成且隨後圖案化蝕刻罩幕46。根據一些實施例,蝕刻罩幕46包括光阻,並且可包含或可不包含由TiN、BN或其類似者形成的硬式罩幕。隨後執行非等向性蝕刻製程以形成穿透介電層的開口,所述介電層包含介電層44、鈍化層42、蝕刻終止層40、IMD 38、蝕刻終止層37、ILD 28等。進一步蝕刻半導體基底24以使開口48延伸至基底24的中間水平,其中中間水平處於半導體基底24的頂部表面與底部表面之間。據此形成開口48。相應的製程在如圖25中所示的製程流程200中示出為製程204。開口48用於形成半導體穿孔(Through-Semiconductor Via;TSV,有時亦稱為矽穿孔),從而在下文中稱為TSV開口48。非
等向性蝕刻製程包含多個蝕刻製程,所述多個蝕刻製程採取不同蝕刻氣體以蝕刻由不同材料形成的介電層且蝕刻半導體基底24。
根據一些實施例,TSV開口48具有頂部寬度W1及小於頂部寬度W1的底部寬度W2。TSV開口48可具有傾斜且直的邊緣48E,其中直邊緣48E的下傾角α小於90度,例如在約80度與約90度之間的範圍內。根據一些實施例,開口48的高寬比H1/W1可在約2與約10之間的範圍內。在形成TSV開口48之後例如藉由灰化製程移除蝕刻罩幕46。
參考圖3,沉積第一介電襯墊50。相應的製程在如圖25中所示的製程流程200中示出為製程206。介電襯墊50沉積為共形層或大致為共形層,以使介電襯墊50的水平部分及豎直部分具有接近於彼此的厚度,例如變化小於約20%或10%。沉積方法可包含原子層沉積(Atomic Layer Deposition;ALD)、電漿增強式化學氣相沉積(PECVD)或其類似者。舉例而言,在將形成SiN時,用於形成介電襯墊50的前驅物可包括含矽前驅物(如SiCl4、SiH2Cl2、Si2Cl6、Si3Cl8或其類似者)及含氮前驅物(如NH3)。根據一些實施例,介電襯墊50具有良好的耐濕氣能力,以使得濕氣難以例如藉由開口48穿透介電襯墊50而到達低k介電層38。由於低k介電層38為多孔的且可能容易吸收濕氣,而使濕氣可到達金屬線34及通孔36以引起銅結節(copper nodule)缺陷。因此,一旦沉積了耐濕氣介電襯墊50,即使開口48暴露於外部環境,亦可有效防止濕氣到達低k介電層38、金屬線34及通孔36。根據一些實施例,介電襯墊50由氮化矽、碳化矽、碳氧化矽或其類似者或其組合形成或包括氮化矽、碳化矽、碳氧化矽或其類似者或
其組合。介電襯墊50的厚度T1可在約50埃與約1,500埃之間的範圍內。
參考圖4,第二介電襯墊52沉積於第一介電襯墊50上。相應的製程在如圖25中所示的製程流程200中示出為製程208。介電襯墊52亦沉積為共形層,以使介電襯墊52的水平部分及豎直部分具有接近於彼此的厚度,例如變化小於約20%或10%。沉積方法可包含原子層沉積(ALD)、化學氣相沉積(Chemical Vapor Deposition;CVD)或其類似者。根據一些實施例,介電襯墊52由與介電襯墊50的材料不同的材料形成。舉例而言,介電襯墊52可由具有比介電襯墊50低的(電流)洩漏的材料形成。在另一方面,由於介電襯墊50已經具有耐濕氣能力,故介電襯墊52的耐濕氣能力可低於介電襯墊50的耐濕氣能力。根據一些實施例,介電襯墊52由氧化矽、氮氧化矽或其類似者形成或包括氧化矽、氮氧化矽或其類似者。介電襯墊52的厚度T2可在約500埃與約2,500埃之間的範圍內。介電襯墊50及介電襯墊52亦統稱為多層介電襯墊。
根據一些實施例,使用包括N2、O2、N2O、雙(第三丁胺基矽烷)(Bis(tertiary-butylamino silane);BTBAS)及/或其組合的前驅物形成介電襯墊52。因此,所得的介電襯墊52可包括氧化矽或氮氧化矽。根據一些實施例,介電襯墊52及介電襯墊50兩者皆包括矽,並且介電襯墊50具有比介電襯墊52高的氮原子百分比,介電襯墊52具有比介電襯墊50高的氧原子百分比。舉例而言,除了介電襯墊52具有比層50高的氮原子百分比(在沉積時)且介電襯墊50具有比層52高的氧原子百分比(在沉積時)之外,
介電襯墊52及介電襯墊50兩者皆可包括氮氧化矽。此可藉由導入含氧處理氣體及含氮處理氣體兩者來達成,並且採取不同的流動速率的處理氣體以用於沉積介電襯墊50及介電襯墊52。根據替代性實施例,介電襯墊50及介電襯墊52的形成可包含先將氮化矽層沉積為介電襯墊50,隨後逐漸轉變成將氧化矽沉積為介電襯墊52。在轉變製程中,逐漸增大含氧的處理氣體的流動速率,並逐漸減小含氮的處理氣體的流動速率直到斷開含氮的處理氣體,以將氧化矽進一步沉積為介電襯墊50。可根據此等實施例使用諸如CVD或PECVD的沉積方法。根據一些實施例,介電襯墊52是由均質材料(homogeneous material)形成的單層,所述均質材料與介電襯墊52及隨後形成的晶種層54實體接觸(圖5)。
介電襯墊50及介電襯墊52可具有不同密度。根據一些實施例,介電襯墊52比介電襯墊50更密。舉例而言,介電襯墊50可以具有在約2.5公克/立方公分(g/cm3)與約4.0g/cm3之間的範圍內的密度DS50。介電襯墊52可以具有在約2.0g/cm3與約3.0g/cm3之間的範圍內的密度DS52。密度差(DS52-DS50)可大於約0.5g/cm3,並且可在約0.5g/cm3與約1.0g/cm3之間的範圍內。
若不形成介電襯墊50,則介電襯墊52將被形成為與低k介電層38直接接觸。介電襯墊52(如氧化矽)的形成可能引起副產物,所述副產物可能侵蝕低k介電層38中的低k介電材料。藉由先形成介電襯墊50,介電襯墊52的形成中產生的副產物(若存在)藉由介電襯墊50與低k介電層38分離且不可能再侵蝕低k介電層38。
根據一些實施例,形成包含介電襯墊50及介電襯墊52
的雙襯墊(dual-liner)。根據替代性實施例,可形成包含多於兩層介電襯墊的多層襯墊。舉例而言,第三介電襯墊可沉積在介電襯墊50與介電襯墊52之間。根據一些實施例,第三介電襯墊具有介電襯墊50與介電襯墊52的性質之間的性質,從而可作為介電襯墊50與介電襯墊52之間的緩衝層。舉例而言,在介電襯墊50及介電襯墊52分別由SiN及SiO2形成時,介電襯墊50與介電襯墊52之間的額外介電層可由氮氧化矽形成或包括氮氧化矽。介電襯墊50與介電襯墊52之間的額外介電層亦可由碳化矽形成或包括碳化矽。三層或多於三層介電襯墊可在不同製程中使用不同前驅物來進行沉積。
圖5示出了金屬晶種層54的沉積。相應的製程在如圖25中所示的製程流程200中示出為製程210。根據一些實施例,藉由物理氣相沉積(Physical Vapor Deposition;PVD)形成金屬晶種層54。金屬晶種層54可為例如由銅形成的單層或可包含多層,所述多層例如包含導電障壁層及導電障壁層上的銅層。導電障壁層可由TiN、Ti或其類似者形成或包括TiN、Ti或其類似者。
圖6示出了導電材料56的沉積,所述導電材料56可為諸如銅或銅合金的金屬材料。相應的製程在如圖25中所示的製程流程200中示出為製程212。可使用電化學鍍覆(electrochemical plating;ECP)、無電鍍覆或其類似者來執行沉積製程。執行鍍覆直到鍍覆導電材料56的頂部表面高於介電襯墊50或介電襯墊52的頂部表面為止。
圖7示出了使導電材料56的頂部表面平坦化的平坦化製程,所述平坦化製程可為CMP製程或機械研磨(mechanical
grinding)製程。相應的製程在如圖25中所示的製程流程200中示出為製程214。根據一些實施例,使用介電襯墊52的水平部分作為CMP終止層來執行第一CMP製程,如圖7所示。根據替代性實施例,使用介電襯墊50的水平部分作為CMP終止層來執行第一CMP製程。因此,剩餘導電材料56的頂部表面將與介電襯墊50的水平部分的頂部表面共面。根據又一替代性實施例,使用介電層44作為CMP終止層來執行第一CMP製程。因此,剩餘導電材料56的頂部表面將與介電層44的頂部表面共面。
接下來,如圖8所示,執行退火製程58。相應的製程在如圖25中所示的製程流程200中示出為製程216。根據一些實施例,使用鍋爐退火(furnace annealing)、快速熱退火(rapid thermal annealing)、閃光退火(flash annealing)或其類似者執行退火製程58。退火的溫度可在約250℃與約450℃之間的範圍內。退火持續的時間與所使用的方法有關。舉例而言,在使用鍋爐退火時,退火的溫度可在約30分鐘與約120分鐘之間的範圍內。
作為退火製程58的結果,導電材料56可具有凸出的部分,從而形成隆起(hump)58',如圖8所示。在後續製程中,執行第二平坦化製程以移除隆起58',並在圖9中繪示所得結構。相應的製程在如圖25中所示的製程流程200中示出為製程218。根據一些實施例,第二平坦化製程進一步移除介電襯墊50及介電襯墊52的水平部分且可移除或可不移除介電層44,所述介電層44用於在前述製程中保護鈍化層42。第二平坦化製程可為CMP製程,並可使用鈍化層42作為CMP終止層來執行。因此,在第二CMP製程之後,根據一些實施例顯露出鈍化層42。導電材料56
及晶種層54的剩餘部分統稱為TSV 61。雖然只示出一個TSV 61,但同時形成多個TSV 61。
根據替代性實施例,在退火製程之前不執行平坦化製程並在退火製程之後執行單一次平坦化製程,而不是在執行退火製程之前和之後執行兩次平坦化製程。也就是說,跳過如圖7中所示的平坦化製程,而執行如圖8中所示的退火製程及如圖9中所示的CMP製程。
在圖9中所示的實例中,TSV 61的頂部表面與鈍化層42齊平(且可高於所述鈍化層42)。根據替代性實施例,TSV 61的頂部表面可在半導體基底24的頂部表面24A與鈍化層42的頂部表面之間(及包含所述半導體基底24的所述頂部表面24A及所述鈍化層42的所述頂部表面)的任何水平處。舉例而言,TSV 61的頂部表面可與內連線結構32中的任一個介電層的頂部表面齊平。根據此等實施例,將在形成TSV 61之後形成額外介電層,並且金屬線、通孔、重佈線等將形成於額外介電層中以將TSV電性連接至如隨後所述的上覆的電連接件(如圖16中的電連接件70)。
進一步參考圖9,形成通孔59以連接至頂部金屬線/墊34。相應的製程在如圖25中所示的製程流程200中示出為製程220。根據一些實施例,藉由單個金屬鑲嵌製程形成通孔59。形成製程可包含蝕刻鈍化層42以形成開口、沉積導電障壁(例如由鈦、氮化鈦、鉭、氮化鉭或其類似者形成)、以及鍍覆諸如銅、鎢或其類似者的導電材料。隨後可執行CMP製程以移除過量材料,從而留下通孔59。
參考圖10,根據一些實施例,沉積介電隔離層60。相應
的製程在如圖25中所示的製程流程200中示出為製程222。隔離層60可由耐濕氣的材料形成或包括耐濕氣的材料,使隔離層60可防止濕氣穿透隔離層60而到達下面的層。隔離層60的材料可選自用於形成介電襯墊50的候選材料的同一族群,並且可與介電襯墊50的材料相同或不同。舉例而言,在介電襯墊50由氮化矽形成時,隔離層60可由氮化矽或碳化矽形成。
參考圖11,蝕刻隔離層60,並且金屬墊62形成於鈍化層42上方。相應的製程在如圖25中所示的製程流程200中示出為製程224。金屬墊62可為鋁墊或鋁銅墊,並可使用其他金屬材料。形成製程可包含沉積金屬層,隨後圖案化金屬層以留下金屬墊62。根據一些實施例,金屬墊62亦可具有在隔離層60正上方延伸的一些部分。隨後形成鈍化層64(有時稱為鈍化-2(passivation-2))。鈍化層64可為單層或複合層,並可由諸如氧化矽、氮化矽、USG、氮氧化矽或其類似者的無孔材料形成。
接下來,圖案化鈍化層64,以使鈍化層64的一些部分覆蓋金屬墊62的邊緣部分,並且藉由鈍化層64中的開口暴露出金屬墊62的一些部分。舉例而言,隨後藉由以可流動形式分配聚合物層66,然後固化聚合物層66來形成聚合物層66。隨後圖案化聚合物層66以暴露出金屬墊62。相應的製程在如圖25中所示的製程流程200中示出為製程226。聚合物層66可由聚醯亞胺、聚苯并噁唑(polybenzoxazole;PBO)或其類似者形成。
隨後形成凸塊下金屬(Under-Bump-Metallurgy;UBM)68及導電區70以電性連接至之下金屬墊62,如圖12所示。相應的製程在如圖25中所示的製程流程200中示出為製程228。UBM
68及導電區70的形成製程可包含沉積延伸至鈍化層64及聚合物層66中的開口中的毯覆式金屬晶種層,在金屬晶種層上形成經圖案化鍍覆罩幕、鍍覆導電區70、移除鍍覆罩幕以及蝕刻先前由鍍覆罩幕覆蓋的毯覆式金屬晶種層的部分。毯覆式金屬晶種層的剩餘部分稱為UBM 68。金屬晶種層可包含鈦層及鈦層上方的銅層。導電區70可包括銅、鎳、鈀、鋁、金、其合金及/或其多層。導電區70中的每一者可包含銅區,所述銅區可或可不用焊料區封蓋,所述焊料區可由SnAg或類似材料形成。
圖13至圖15示出了用於在半導體基底24的背側上形成特徵的製程。相應的製程在如圖25中所示的製程流程200中示出為製程230。參考圖13,執行背側研磨(backside grinding)製程以移除基底24的一部分,直至顯露出TSV 61為止。接下來,基底24(例如藉由蝕刻)略微凹入,以使TSV 61從基底24的背部表面突出。
接下來,如圖14所示,沉積介電層72,接著進行CMP製程或機械研磨製程以再暴露出TSV 61。據此,TSV 61穿透介電層72。根據一些實施例,介電層72由氧化矽、氮化矽或其類似者形成。參考圖15,形成重佈線路層(redistribution layer;RDL)74,其包含與TSV 61接觸的接墊部分。根據一些實施例,RDL 74可由鋁、銅、鎳、鈦或其類似者形成。
圖16示出了介電層76及電連接件78的形成。根據一些實施例,電連接件78包含焊料區,所述焊料區可藉由在RDL 74的接墊上鍍覆焊球並對焊球進行回焊來形成。根據替代性實施例,電連接件78由非可回焊(非焊料)的金屬材料形成。舉例而
言,電連接件78可形成為銅墊或銅柱,並可包含或可不包含鎳頂蓋層。亦可藉由鍍覆來形成電連接件78。根據一些實施例,藉由鋸割製程,例如藉由切穿切割道80來單體化晶圓20。
圖17至圖22示出了根據本揭露的一些實施例的形成中介物的中間階段的剖面圖。除非另外說明,否則此等實施例中的組件的材料及形成製程基本上與類似組件相同,所述組件在圖1至圖16中所示的前述實施例中由類似的附圖標號表示。關於圖17至圖22中所示的組件的形成製程及材料的細節在前述實施例中說明。
參考圖17,形成晶圓20,其亦為基底24。根據一些實施例,基底24是半導體基底,例如矽基底。根據替代性實施例,基底24是矽鍺基底。根據又一替代性實施例,基底24是介電基底。基底24可為坯料基底(blank substrate),其中全部基底24由諸如矽、矽鍺、碳摻雜矽或其類似者的均質材料形成。此外,基底24其中不含裝置(如主動裝置及被動裝置)、導電線等。根據一些實施例,介電層25例如藉由執行熱氧化製程以將基底24的頂部表面層轉化成氧化物(例如氧化矽)而形成於基底24的頂部表面上。做為另一種選擇,介電層25可由氮化矽、碳化矽或其類似者形成。根據替代性實施例,不形成介電層25。因此,介電層25示出為虛線的以表示其可被形成或可不被形成。
蝕刻罩幕46形成於基底24上,然後經圖案化。蝕刻罩幕46可包括光阻,並且可包含或可不包含硬式罩幕。隨後蝕刻基底24以在基底24中形成開口48,其中開口48延伸至基底24的中間水平。若形成介電層25,則開口48進一步穿透介電層25。
接下來,參考圖18,藉由沉積製程形成介電襯墊50及介電襯墊52。可參考前述實施例所述的材料及沉積製程的細節,並於此不再重複。圖19示出了金屬晶種層54的沉積及導電材料56的後續沉積。
接下來,根據一些實施例,執行退火製程58,接著進行平坦化製程,諸如CMP製程或機械研磨製程,據此形成TSV 61。在圖20中繪示所得結構。根據替代性實施例,導電材料56的沉積製程之後依序為第一平坦化製程、退火製程58以及第二平坦化製程,所述製程基本上與圖7、圖8以及圖9中所示的製程相同。
圖21示出了內連線結構32的形成,所述內連線結構32包含介電層37及介電層38。介電層37可為蝕刻終止層,並且介電層38可包含ILD、IMD及/或其類似者。金屬線34及通孔36形成在介電層37及介電層38中,並且電性連接至TSV 61。在後續製程中,形成鈍化層42、鈍化層64以及聚合物層66。亦形成通孔59、金屬墊62、UBM 68以及導電區70。可參考前述實施例所述的材料及形成製程的細節。
圖22示出了在基底24的背側上的背側結構的形成。形成製程包含對基底24執行背側研磨以顯露出TSV 61、形成介電層72、形成RDL 74、形成介電層76以及形成電連接件78。晶圓20可沿著切割道80鋸割開來以形成中介物22。中介物22中不含主動裝置,並可能不含被動裝置(如電晶體、電容器、電感器或其類似者)。
在如圖22中所示的實施例中,TSV 61的頂部表面與基底24的頂部表面齊平(且可高於所述基底24的所述頂部表面)。根
據替代性實施例,TSV 61的頂部表面可處於半導體基底24的頂部表面24A與鈍化層42的頂部表面之間(及包含所述半導體基底24的所述頂部表面24A及所述鈍化層42的所述頂部表面)的任何水平處。舉例而言,TSV 61的頂部表面可與內連線結構32中的任何介電層的頂部表面齊平。
圖23示出了TSV 61的平面圖。根據一些實施例,介電襯墊50及介電襯墊52中的每一者形成環,所述環可具有圓形形狀、多邊形形狀(諸如六邊形形狀或八邊形形狀)或其類似者。金屬晶種層54(在包含與導電材料56的材料不同的材料的情況下)可為可區分辨別的。
圖24示出了封裝件80,所述封裝件80包含與封裝組件22接合的封裝組件84,所述封裝組件22可為裝置晶粒22(圖16)、中介物22(圖22)或其類似者。扇出型重佈線結構86形成於封裝組件22上方。重佈線結構86可包含一個或多個重佈線層。包封體88(可為模製化合物或模製底膠)將封裝組件22包封在其中。穿孔90穿透包封體88並將封裝組件84電性連接至重佈線結構86。形成電連接件92(可為焊料區)以電性連接至重佈線結構86。
本揭露的實施例具有一些有利特徵。藉由形成穿孔的多於一層介電襯墊,不同的介電襯墊可用作不同的功能。耐濕氣介電襯墊可有效地將低k介電層及導電特徵與可在形成穿孔期間及之後到達此等特徵的濕氣隔離,從而減少缺陷。耐濕氣介電襯墊可防止低k介電層被後續製程中所生成的副產物侵蝕。
根據本揭露的一些實施例,一種方法包含:蝕刻基底以
形成開口、沉積延伸至開口中的第一介電襯墊、將第二介電襯墊沉積在第一介電襯墊上方,其中第二介電襯墊延伸至開口中、將導電材料填充至開口中、執行第一平坦化製程以使導電材料平坦化,其中開口中的導電材料的一部分形成穿孔、對基底執行背側研磨製程,直至穿孔自基底的背側顯露為止、以及在基底的背側上形成導電特徵,其中導電特徵電連接至穿孔。在實施例中,第一介電襯墊具有比第二介電襯墊更佳的濕氣隔離能力。在實施例中,使用電漿增強式化學氣相沉積來執行沉積第一介電襯墊。在實施例中,沉積第一介電襯墊包括沉積氮化矽,並且沉積第二介電襯墊包括沉積氧化矽。在實施例中,沉積第一介電襯墊包括沉積碳化矽,並且沉積第二介電襯墊包括沉積氧化矽。在實施例中,方法更包括在蝕刻基底之前執行以下步驟:將多個低k介電層沉積在基底上方、將鈍化層沉積在多個低k介電層上方、以及蝕刻鈍化層及多個低k介電層以形成額外開口,其中額外開口連接至基底中的開口以形成連續開口。在實施例中,方法更包括使導電材料退火,其中在退火之後執行使導電材料平坦化。在實施例中,方法更包括在退火之前,對導電材料執行第二平坦化製程,其中第一介電襯墊的水平部分在第二平坦化製程之後保留,並且其中第一介電襯墊的水平部分藉由第一平坦化製程移除。
根據本揭露的一些實施例,一種結構包含:半導體基底、位於半導體基底的第一側上的第一導電特徵、位於半導體基底的第二側上的第二導電特徵、穿透半導體基底的穿孔,其中穿孔將第一導電特徵及第二導電特徵電性內連、環繞穿孔的第一介電襯墊、以及環繞第一介電襯墊的第二介電襯墊,其中第一介電襯墊
及第二介電襯墊由不同材料形成。在實施例中,第二介電襯墊具有比第一介電襯墊更佳的濕氣隔離能力。在實施例中,第一介電襯墊包括氧化矽,並且第二介電襯墊包括氮化矽。在實施例中,第一介電襯墊包括氧化矽,並且第二介電襯墊包括碳化矽。在實施例中,結構更包括:位於半導體基底上方的多個低k介電層、以及位於多個低k介電層上方的鈍化層,其中穿孔進一步穿透多個低k介電層及鈍化層。在實施例中,結構更包括多個低k介電層,位於半導體基底上方,其中穿孔的頂部表面在多個低k介電層之下。在實施例中,結構更包括半導體基底的頂部表面處的積體電路。在實施例中,穿孔位於中介物晶粒中,並且中介物晶粒中不含主動裝置及被動裝置。
根據本揭露的一些實施例,一種結構包含晶粒。晶粒包括:半導體基底、位於半導體基底上方的多個低k介電層、位於多個低k介電層上方的非低k鈍化層、穿透半導體基底、多個低k介電層以及非低k鈍化層的穿孔、環繞穿孔的多層介電襯墊、位於非低k鈍化層上方且在晶粒的頂部表面處的第一電連接件、以及位於半導體基底之下且在晶粒的底部表面處的第二電連接件,其中第一電連接件及第二電連接件藉由穿孔電性內連。在實施例中,多層介電襯墊包括與半導體基底及多個低k介電層接觸的外層及由外層環繞的內層。在實施例中,外層與內層實體接觸。在實施例中,外層及內層兩者包括矽,並且外層具有比內層高的氮原子百分比,內層具有比外層高的氧原子百分比。
前文概述若干實施例的特徵,以使得所屬領域中具通常知識者可較好地理解本揭露的態樣。所屬領域中具通常知識者應
瞭解,其可易於使用本揭露作為設計或修改用於實施本文中所引入的實施例的相同目的且/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到,此類等效構造不脫離本揭露的精神及範疇,並且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代及更改。
20:晶圓
22:晶片/晶粒
24:半導體基底
26:積體電路裝置
28:層間介電質
30:接觸插塞
32:內連線結構
42、64:鈍化層
50:第一介電襯墊
52:第二介電襯墊
54:晶種層
56:導電材料
59:通孔
60:隔離層
61:半導體穿孔(TSV)
62:金屬墊
66:聚合物層
68:凸塊下金屬
70、78:電連接件
72、76:介電層
74:重佈線路層(RDL)
80:切割道
Claims (10)
- 一種形成半導體結構的方法,包括:蝕刻基底以形成開口;沉積延伸至所述開口中的第一介電襯墊;將第二介電襯墊沉積在所述第一介電襯墊上方,其中所述第二介電襯墊延伸至所述開口中;將導電材料填充至所述開口中;對所述導電材料執行退火;在所述退火之後執行第一平坦化製程以使所述導電材料平坦化,其中所述開口中的所述導電材料的一部分形成穿孔;對所述基底執行背側研磨製程,直至所述穿孔自所述基底的背側顯露為止;以及在所述基底的所述背側上形成導電特徵,其中所述導電特徵電連接至所述穿孔。
- 如請求項1所述的形成半導體結構的方法,其中所述第一介電襯墊具有比所述第二介電襯墊更佳的濕氣隔離能力。
- 如請求項1所述的形成半導體結構的方法,更包括在蝕刻所述基底之前執行以下步驟:將多個低介電係數介電層沉積在所述基底上方;將鈍化層沉積在所述低介電係數介電層上方;以及蝕刻所述鈍化層及所述低介電係數介電層以形成額外開口,其中所述額外開口連接至所述基底中的所述開口以形成連續開口。
- 如請求項1所述的形成半導體結構的方法,其中將 所述第二介電襯墊形成為具有與所述第一介電襯墊的密度不同的密度。
- 如請求項1所述的形成半導體結構的方法,更包括:在所述退火之前,對所述導電材料執行第二平坦化製程,其中所述第一介電襯墊的水平部分在所述第二平坦化製程之後保留,並且其中所述第一介電襯墊的所述水平部分藉由所述第一平坦化製程移除。
- 一種使用如申請專利範圍請求項1-5中任一項所述之形成方法所形成的半導體結構。
- 如請求項6所述的半導體結構,其中所述穿孔具有與所述基底的表面共面的端部。
- 如請求項6所述的半導體結構,其中:所述穿孔穿透所述基底並進一步穿透所述低介電係數介電層及所述鈍化層。
- 一種半導體結構,包括:晶粒,包括:半導體基底;多個低介電係數介電層,位於所述半導體基底上方;非低介電係數鈍化層,位於所述低介電係數介電層上方;穿孔,穿透所述半導體基底、所述低介電係數介電層以及所述非低介電係數鈍化層;多層介電襯墊,環繞所述穿孔;第一電連接件,位於所述非低介電係數鈍化層上方且 在所述晶粒的頂部表面處;以及第二電連接件,位於所述半導體基底之下且在所述晶粒的底部表面處,其中所述第一電連接件及所述第二電連接件經由所述穿孔電性內連。
- 如請求項9所述的半導體結構,其中所述多層介電襯墊包括與所述半導體基底及所述低介電係數介電層接觸的外層及由所述外層環繞的內層,所述外層及所述內層兩者包括矽,並且所述外層具有比所述內層高的氮原子百分比,所述內層具有比所述外層高的氧原子百分比。
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CN105575828B (zh) * | 2014-10-16 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制作方法 |
US10535558B2 (en) * | 2016-02-09 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
US10658296B2 (en) * | 2016-09-30 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dielectric film for semiconductor fabrication |
US10505111B1 (en) * | 2018-07-20 | 2019-12-10 | International Business Machines Corporation | Confined phase change memory with double air gap |
DE102019130124A1 (de) * | 2018-11-30 | 2020-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Funktionale komponente innerhalb einer verbindungsstruktur einer halbleitervorrichtung und verfahren zum bilden derselben |
-
2020
- 2020-12-28 US US17/135,435 patent/US11823989B2/en active Active
- 2020-12-30 DE DE102020135142.9A patent/DE102020135142B4/de active Active
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2021
- 2021-02-15 KR KR1020210020125A patent/KR20220010412A/ko not_active Application Discontinuation
- 2021-03-08 TW TW110108221A patent/TWI760134B/zh active
- 2021-04-27 CN CN202110460002.9A patent/CN113594088A/zh active Pending
- 2021-07-16 JP JP2021117562A patent/JP2022019672A/ja active Pending
- 2021-07-16 EP EP21186106.7A patent/EP3940760A1/en not_active Withdrawn
-
2023
- 2023-07-25 US US18/358,570 patent/US20240021509A1/en active Pending
-
2024
- 2024-02-28 KR KR1020240028810A patent/KR20240032785A/ko not_active Application Discontinuation
Patent Citations (3)
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US20100090318A1 (en) * | 2008-10-09 | 2010-04-15 | Kuo-Ching Hsu | Backside Connection to TSVs Having Redistribution Lines |
US20110169168A1 (en) * | 2009-02-24 | 2011-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via formed with a post passivation interconnect structure |
US20200185330A1 (en) * | 2018-12-05 | 2020-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods of forming the same |
Also Published As
Publication number | Publication date |
---|---|
CN113594088A (zh) | 2021-11-02 |
DE102020135142A1 (de) | 2022-01-20 |
EP3940760A1 (en) | 2022-01-19 |
DE102020135142B4 (de) | 2024-05-16 |
US20220020675A1 (en) | 2022-01-20 |
US20240021509A1 (en) | 2024-01-18 |
KR20240032785A (ko) | 2024-03-12 |
US11823989B2 (en) | 2023-11-21 |
JP2022019672A (ja) | 2022-01-27 |
KR20220010412A (ko) | 2022-01-25 |
TW202205526A (zh) | 2022-02-01 |
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