TWI759066B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes pixel structures. Each of the pixel structures includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor. A first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern. The color filter pattern is disposed on the first insulating layer. The second insulating layer is disposed on the color filter pattern. The pixel electrode is disposed on the second insulating layer. In a top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode within an opening of the color filter pattern.

Description

pixel array substrate

The present invention relates to a pixel array substrate.

With the development of display technology, people's demands for display devices are no longer satisfied with optical characteristics such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect a display device with a narrow bezel or even no bezel.

Generally speaking, a display device includes a plurality of pixel structures disposed in the display area, a data driving circuit disposed below the display area, and gate driving circuits disposed on the left, right or left and right sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, both the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is arranged on the lower side of the display area, the gate lines arranged in the vertical direction can be electrically connected to the gate driving circuit only through the connecting wires arranged in the horizontal direction. However, the gate turn-on pulse signal of the patch cord will affect the potential of other pixel structures that are still being charged, thereby causing abnormal display (eg, oblique bright lines). Therefore, how to improve the problem of abnormal display is one of the challenges faced by current ultra-narrow bezel display devices. In addition, how to improve the aperture ratio of the display device, And making it less prone to bubble problems is another issue.

The present invention provides a pixel array substrate with high aperture ratio.

The pixel array substrate of the present invention includes a base and a plurality of pixel structures disposed on the base. Each pixel structure includes a first common electrode, a thin film transistor, a conductive pattern, a first insulating layer, a color filter pattern, a second insulating layer and a pixel electrode. The conductive pattern is electrically connected to the thin film transistor, wherein the first portion of the conductive pattern is disposed on the first common electrode. The first insulating layer is disposed on the conductive pattern and has an opening overlapping with the conductive pattern. The color filter pattern is disposed on the first insulating layer and has an opening overlapping with the conductive pattern. The second insulating layer is disposed on the color filter pattern and has an opening overlapping with the conductive pattern. The pixel electrode is disposed on the second insulating layer, and is electrically connected to the conductive pattern through the opening of the first insulating layer and the opening of the second insulating layer. In the top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode located in the opening of the color filter pattern.

In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a second common electrode. The second common electrode is separated from the first common electrode. The second portion of the conductive pattern is disposed on the second common electrode. In the top view of the pixel array substrate, the second portion of the conductive pattern covers all edges of the second common electrode located in the opening of the color filter pattern.

In an embodiment of the present invention, the above-mentioned conductive pattern further has a third portion; in a top view of the pixel array substrate, the third portion of the conductive pattern is located at the first common power between the electrode and the second common electrode, and the opening of the first insulating layer and the opening of the second insulating layer are located on the third part of the conductive pattern.

In an embodiment of the present invention, in the above-mentioned plan view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the second common electrode and do not overlap the first and second common electrodes. a common electrode and a second common electrode.

In an embodiment of the present invention, each of the above-mentioned pixel structures further includes a third common electrode. The third common electrode is separated from the first common electrode and the second common electrode. The fourth portion of the conductive pattern is disposed on the third common electrode. In the top view of the pixel array substrate, the fourth portion of the conductive pattern covers all the edges of the third common electrode located in the opening of the color filter pattern.

In an embodiment of the present invention, the edge of the first portion of the conductive pattern is substantially flush with the edge of the opening of the color filter pattern.

In an embodiment of the present invention, the above-mentioned conductive pattern further has a fifth portion; in a plan view of the pixel array substrate, the fifth portion of the conductive pattern overlaps with the first common electrode and is located outside the opening of the color filter pattern.

In an embodiment of the present invention, the above-mentioned thin film transistor has a gate electrode, which is separated from the first common electrode; the second part of the conductive pattern is disposed on the gate electrode; in the top view of the pixel array substrate, the second part of the conductive pattern Part of the gate covers all edges of the gate located within the openings of the color filter pattern.

In an embodiment of the present invention, the above-mentioned conductive pattern further has a third portion; in the top view of the pixel array substrate, the third portion of the conductive pattern is located between the first common electrode and the gate electrode, and the first insulating layer openings and the openings of the second insulating layer are located in the conductive on the third part of the electrical pattern.

In an embodiment of the present invention, in the above-mentioned plan view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the gate electrode, and the opening of the first insulating layer is located between the first common electrode and the gate electrode. The opening and the opening of the second insulating layer do not overlap the first common electrode and the gate electrode.

In an embodiment of the present invention, the above-mentioned multiple pixel structures are arranged into multiple pixel rows, and the multiple pixel rows are arranged in the first direction. The pixel array substrate further includes a plurality of scan lines, a plurality of data lines and a plurality of transfer lines. The plurality of scan lines are arranged in the second direction and are electrically connected to the plurality of pixel structures, wherein the first direction and the second direction are staggered. The plurality of data lines are arranged in the first direction and are electrically connected to the plurality of pixel rows. The plurality of transition lines are arranged in the first direction and are electrically connected to the plurality of scan lines. The plurality of scan lines include the x-nth scan line to the xth scan line sequentially arranged in the second direction, x is a positive integer greater than or equal to 2, n is a positive integer and less than x, and the xth scan line is The turn-on time of the gate driving signal and the turn-off time of the gate driving signals of the x-nth row overlap in timing. The plurality of transfer lines include an x-nth transfer line and an xth transfer line, which are electrically connected to the x-nth scan line and the xth scan line, respectively. The plurality of pixel rows include the k-1 th pixel row, the k th pixel row, and the k+1 th pixel row sequentially arranged in the first direction, where k is a positive integer greater than or equal to 2. The plurality of data lines include the k-1 th data line, the k th data line, and the k+1 th data line, which are respectively electrically connected to the k-1 th pixel row, the k th pixel row, and the k+1 th pixel row . In the top view of the pixel array substrate, the x-n th connecting line is disposed between the k-1 th data line and the k th data line, and the x th connecting line is disposed between the k th data line and the k+1 th data line between.

In an embodiment of the present invention, the above-mentioned plurality of scan lines include x-n th scan lines to x+n th scan lines arranged in sequence in the second direction. The end time of the gate pulse signal of the xth scan line and the start time of the gate pulse signal of the x+nth scan line overlap in timing. The plurality of transfer lines further include an x+nth transfer line, which is electrically connected to the x+nth scan line. The plurality of pixel rows further include the k+2 th pixel row. The k-1 th pixel row, the k th pixel row, the k+1 th pixel row, and the k+2 th pixel row are sequentially arranged in the first direction. The plurality of data lines further include a k+2 th data line, which is electrically connected to the k+2 th pixel row. In the top view of the pixel array substrate, the x+n th transition line is disposed between the k+1 th data line and the k+2 th data line.

In an embodiment of the present invention, the above-mentioned multiple pixel rows further include a k+2 th pixel row. The k-1 th pixel row, the k th pixel row, the k+1 th pixel row, and the k+2 th pixel row are sequentially arranged in the first direction. The plurality of data lines further include a k+2 th data line, which is electrically connected to the k+2 th pixel row. The pixel array substrate further includes a first common line. In the top view of the pixel array substrate, the first common line is disposed between the k+1 th data line and the k+2 th data line.

In an embodiment of the present invention, the above-mentioned multiple pixel rows further include a k+2 th pixel row. The k-1 th pixel row, the k th pixel row, the k+1 th pixel row, and the k+2 th pixel row are sequentially arranged in the first direction. The plurality of data lines further include a k+2 th data line, which is electrically connected to the k+2 th pixel row. The plurality of scan lines include the m-th scan line. The plurality of patch cords further include an mth patch cord, which is electrically connected to the mth scan line. m is a positive integer greater than 2, and |x-m| is not equal to n. In the top view of the pixel array substrate, the m th transition line is disposed between the k+1 th data line and the k+2 th data line.

In an embodiment of the present invention, the above-mentioned plurality of scan lines include y-n th scan lines to y th scan lines sequentially arranged in the second direction, y is a positive integer greater than or equal to 2, and n is positive Integer and less than y, the start time of the gate pulse signal of the yth scan line and the end time of the gate pulse signal of the y-nth scan line overlap in timing. The plurality of patch cords include a y-n th patch cable and a y th patch cable, which are electrically connected to the y-n th scan line and the y th scan line, respectively. The plurality of pixel rows include the q-1 th pixel row, the q th pixel row, and the q+1 th pixel row sequentially arranged in the first direction, and q is a positive integer greater than or equal to 2. The plurality of data lines include the q-1th data line, the qth data line and the q+1th data line, which are respectively electrically connected to the q-1th pixel row, the qth pixel row and the q+1th pixel row . In the top view of the pixel array substrate, the yth transition line is disposed between the q-1th data line and the qth data line, and the y-nth transition line is disposed between the qth data line and the q+1th data line between.

In an embodiment of the present invention, the above-mentioned multiple pixel rows further include the q+2th pixel row. The q-1 th pixel row, the q th pixel row, the q+1 th pixel row, and the q+2 th pixel row are sequentially arranged in the first direction. The plurality of data lines further include the q+2th data line, which is electrically connected to the q+2th pixel row. The pixel array substrate further includes a second common line. In the top view of the pixel array substrate, the second common line is disposed between the q+1 th data line and the q+2 th data line.

In an embodiment of the present invention, the above-mentioned multiple pixel rows further include the q+2th pixel row. The q-1 th pixel row, the q th pixel row, the q+1 th pixel row, and the q+2 th pixel row are sequentially arranged in the first direction. The plurality of data lines further include the q+2th data line, which is electrically connected to the q+2th pixel row. The multiple scan lines include the p-th scan traced. The plurality of transfer lines further include a pth transfer line, which is electrically connected to the pth scan line. p is a positive integer greater than 2, and |y-p| is not equal to n. In the top view of the pixel array substrate, the p th transition line is disposed between the q+1 th data line and the q+2 th data line.

In an embodiment of the present invention, the above n=4.

In an embodiment of the present invention, the above-mentioned n=8.

In an embodiment of the present invention, one of the above-mentioned scan lines belongs to the first conductive layer. One of the plurality of patch wires belongs to the second conductive layer. The pixel array substrate further includes an insulating layer disposed between the first conductive layer and the second conductive layer and having a contact window. One of the plurality of scan lines is electrically connected to one of the plurality of transfer lines through the contact window of the insulating layer.

100, 100A, 100B, 100C, 100D: pixel array substrate

110: Base

122: The first common electrode

122e, 124e, 126e, 142e, 142-1e, 162e, Tcs: Edge

124: The second common electrode

126: The third common electrode

130: Insulation layer

132: Contact window

142: Conductive Pattern

142-1: Part 1

142-2: Part II

142-3: Part Three

142-4: Part Four

142-5: Part 5

150: first insulating layer

152, 172, 162, 192: Openings

160: Color filter pattern

164: Sidewall

170: Second insulating layer

180: transparent conductive layer

190: The third insulating layer

194: Pixel Electrode

A: area

DL, DLk-1, DLk, DLk+1, DLk+2, DLq-1, DLq, DLq+1, DLq+2, DL1~DL23: Data line

d1: first direction

d2: the second direction

HG, HGm, HGp, HGx-n~HGx+n, HGy-n~HGy, HG1~HG18: Scan line

PX: pixel structure

R, Rk-1, Rk, Rk+1, Rk+2, Rq-1, Rq, Rq+1, Rq+2, R1 ~R23: pixel row

S _HGx-n ~S _HGx+n , S _HGy-n ~S _HGy , S _HG1 ~S _HG18 , S _VGx-n , S _VGx , S _VGx+n , S _VG1 ~S _VG18 : gate pulse signal

T: thin film transistor

Ta: source

Tb: drain

Tc: gate

Td: Semiconductor pattern

Tp: Pulse time length

t: time length of time delay

tonx, tonx+n, tony, ton1, ton3, ton5, ton7, ton9, ton11, ton13, ton14, ton15, ton16, ton17, ton18: start time

toffx-n, toffx, toffy-n, toff1, toff3, toff5, toff6, toff7, toff8, toff9, toff10: end time

VG, VGp, VGm, VGx-n, VGx, VGx+n, VGy-n, VGy, VG1~VG18: Adapter cable

VGa: at least a part

Vgh: high potential

Vgl: low potential

VSS1, VSS1a, VSS1b, VSS1c, VSS1d: first common line

VSS2: Second common line

I-I', II-II', III-III', IV-IV', V-V': cross-section

FIG. 1 is a schematic top view of one part of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 2 shows a plurality of gate pulse signals S _HGx-n to S _HGx+n of the xn th scan line HGx-n to the x+n th scan line HGx+n of FIG. 1 .

3 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 5 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 6 shows a plurality of gate pulse signals S _{HG1 ˜S} HG18 of the first scan line HG1 to the eighteenth scan line HG18 according to an embodiment of the present invention.

FIG. 7 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 8 shows a plurality of gate pulse signals S _HGx-n to S _HGx+n of the xn th scan line HGx-n to the x+n th scan line HGx+n of FIG. 7 .

FIG. 9 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 10 shows a plurality of gate pulse signals S _HGx-n to S _HGx+n of the xn th scan line HGx-n to the x+n th scan line HGx+n of FIG. 9 .

FIG. 11 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 12 shows a plurality of gate pulse signals S _HGy-n to S _HGy of the y-th scan line HGy-n to the y-th scan line HGy of FIG. 11 .

FIG. 13 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 14 shows a plurality of gate pulse signals S _HGy-n to S _HGy of the y-th scan line HGy-n to the y-th scan line HGy of FIG. 13 .

FIG. 15 is a schematic top view of one part of the pixel array substrate 100A according to an embodiment of the present invention.

FIG. 16 shows a plurality of gate pulse signals S _HG1 to S _HG9 of the first scan line HG1 to the ninth scan line HG9 in FIG. 15 .

17 is a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention cross-sectional schematic diagram.

18 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100B according to an embodiment of the present invention.

19 is a schematic cross-sectional view of the pixel structure PX of the pixel array substrate 100B according to an embodiment of the present invention.

FIG. 20 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100C according to an embodiment of the present invention.

21 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

22 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100D according to an embodiment of the present invention.

23 is a schematic cross-sectional view of the pixel structure PX of the pixel array substrate 100D according to an embodiment of the present invention.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present pieces. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specified amount of measurement-related error (ie, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic top view of one part of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 2 shows a plurality of gate pulse signals S _HGx-n to S _HGx+n of the xn th scan line HGx-n to the x+n th scan line HGx+n of FIG. 1 .

3 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100 according to an embodiment of the present invention. FIG. 3 corresponds to area A of FIG. 1 .

FIG. 4 is a schematic cross-sectional view of a pixel array substrate 100 according to an embodiment of the present invention. Fig. 4 corresponds to the section line I-I' of Fig. 3 .

Referring to FIG. 1 and FIG. 4 , the pixel array substrate 100 includes a base 110 . For example, in this embodiment, the material of the substrate 110 may be glass. However, the present invention is not limited thereto, and in other embodiments, the material of the substrate 110 can also be quartz, organic polymer, opaque/reflective material (eg, wafer, ceramic, etc.), or other applicable materials .

Referring to FIG. 1 , the pixel array substrate 100 further includes a plurality of pixel structures PX disposed on the substrate 110 . A plurality of pixel structures PX are arranged in a plurality of pixel rows R. The plurality of pixel rows R are arranged in the first direction d1.

Referring to FIG. 1 and FIG. 3 , each pixel structure PX includes a thin film transistor T and a pixel electrode 194 . The thin film transistor T has a source electrode Ta, a drain electrode Tb, a gate electrode Tc, and a semiconductor pattern Td. The insulating layer 130 (drawn in FIG. 4 ) is sandwiched between the gate electrode Tc and the semiconductor pattern Td. The insulating layer 130 may also be called a gate insulating layer. The source electrode Ta and the drain electrode Tb are respectively electrically connected to two different regions of the semiconductor pattern Td, and the pixel electrode 194 is electrically connected to the drain electrode Tb.

For example, in this embodiment, the gate electrode Tc of the thin film transistor T may belong to the first conductive layer, and the source electrode Ta and drain electrode Tb of the thin film transistor T may belong to the second conductive layer, but the present invention does not use this limited.

In this embodiment, the first conductive layer may be a first metal layer; that is, the material of the first conductive layer may be metal. However, the present invention is not limited to this. In other embodiments, the material of the first conductive layer may be other conductive materials, such as Such as: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials.

In this embodiment, the second conductive layer may be a second metal layer; that is, the material of the second conductive layer may be metal. However, the present invention is not limited thereto, and in other embodiments, the material of the second conductive layer can also be other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitride of metal materials material, or a stack of metal materials and other conductive materials.

Please refer to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of scan lines HG arranged in the second direction d2 , wherein the first direction d1 and the second direction d2 are staggered. For example, in this embodiment, the first direction d1 and the second direction d2 may be perpendicular, but the invention is not limited to this. The plurality of scan lines HG are electrically connected to the plurality of pixel structures PX. In detail, the plurality of scan lines HG are electrically connected to the plurality of gate electrodes Tc of the plurality of thin film transistors T of the plurality of pixel structures PX. In this embodiment, the scan line HG may belong to the first conductive layer, but the invention is not limited thereto.

Please refer to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of data lines DL arranged in the first direction d1 and electrically connected to the plurality of pixel rows R. In detail, in this embodiment, a plurality of data lines DL are electrically connected to a plurality of source electrodes Ta of a plurality of thin film transistors T of a plurality of pixel rows R, and the plurality of pixel structures PX of the same pixel row R are A plurality of source electrodes Ta are electrically connected to the same data line DL. In this embodiment, the data line DL may belong to the second conductive layer, but the invention is not limited thereto.

Referring to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a plurality of transfer wires VG, which are arranged in the first direction d1 and are electrically connected to the plurality of scanning wires HG. Please refer to 1 , 3 and 4 , for example, in this embodiment, the scan line HG belongs to the first conductive layer, and at least a part of VGa (marked in FIG. 4 ) of the patch line VG belongs to the second conductive layer. Conductive layer; the insulating layer 130 is disposed between the first conductive layer and the second conductive layer, and has a contact window 132 (marked in FIG. 4 ); at least a part of VGa of the patch wire VG passes through the insulating layer 130 The contact window 132 is electrically connected to the scan line HG.

Please refer to FIG. 1 , the plurality of scan lines HG include the x-nth scan line HGx-n to the x+nth scan line HGx+n sequentially arranged in the second direction d2, wherein x is a positive value greater than or equal to 2 Integer, n is a positive integer less than x.

Referring to FIG. 1 and FIG. 2 , the xn th scan line HGx-n to the x+n th scan line HGx+n have gate pulse signals S _HGx-n to S _HGx+n , respectively. Specifically, the xn th scan line HGx-n has a gate pulse signal S _HGx-n , the x-n+1 th scan line HGx-n+1 has a gate pulse signal S _HGx-n+1 , and the x th scan line HGx-n+1 has a gate pulse signal S HGx-n+1 . -n+2 scan lines HGx-n+2 have gate pulse signal S _HGx-n+2 ,..., the xth scan line HGx has gate pulse signal S _HGx , the x+1th scan line HGx+1 It has a gate pulse signal S _HGx+1 , the x+2th scan line HGx+2 has a gate pulse signal S _HGx+2 , ..., the x+nth scan line HGx+n has a gate pulse signal S _{HGx+ n} .

Referring to FIG. 1 and FIG. 2 , in this embodiment, the xn th scan line HGx-n to the x+n th scan line HGx+n are sequentially turned on with a time delay, wherein the time length of the time delay is t( As shown in FIG. 2 ), the pulse time length of each of the gate pulse signal S _HGx-n to the gate pulse signal S _HGx+n is Tp (as shown in FIG. 2 ), and n=Tp/t. The start time tonx of the gate pulse signal S _HGx of the x-th scan line HGx and the end time toffx-n of the gate pulse signal S _HGx-n of the xn-th scan line HGx-n overlap in timing. That is to say, the period during which the gate pulse signal S _HGx of the xth scan line HGx rises from the low potential Vgl to the high potential Vgh and the gate pulse signal S _HGx-n of the xnth scan line HGx-n rise from the high potential Vgh The time period falling to the low level Vgl is at least partially overlapped in timing. The end time toffx of the gate pulse signal S _HGx of the xth scan line HGx and the start time tonx+n of the gate pulse signal S _HGx+n of the x+nth scan line HGx+n overlap in timing. That is to say, the period during which the gate pulse signal S _HGx of the xth scan line HGx drops from the high potential Vgh to the low potential Vgl and the gate pulse signal S _HGx+n of the x+nth scan line HGx+n are changed from The time period during which the low voltage Vgl rises to the high voltage Vgh at least partially overlaps in timing.

Referring to FIG. 1 , the plurality of patch cords VG include an xnth patch cord VGx-n, an xth patch cord VGx, and an x+nth patch cord VGx+n, which are respectively electrically connected to the xnth scan line HGx -n, the xth scan line HGx and the x+nth scan line HGx+n. Please refer to FIG. 1 and FIG. 2 , the xn-th switching wire VGx-n, the x-th switching wire VGx, and the x+n-th switching wire VGx+n respectively have a gate pulse signal S _VGx-n and a gate pulse signal S _VGx and the gate pulse signal S _VGx+n , wherein the gate pulse signal S VGx-n of the xnth transfer wire VGx-n, the gate pulse signal S _VGx of the xth transfer wire _VGx and the x+nth transfer wire The gate pulse signal S _{VGx+n of the line VGx+n} is respectively the gate pulse signal S HGx-n of the xn th scanning line HGx-n , the gate pulse signal S _HGx of the x th scanning line HGx and the gate pulse signal S _HGx of the xth scanning line HGx The gate pulse signals S _HGx+n of the n scanning lines HGx+n are the same.

Referring to FIG. 1 , the plurality of pixel rows R include the k-1 th pixel row Rk-1, the k th pixel row Rk and the k+1 th pixel row arranged in sequence in the first direction d1 Rk+1, k is a positive integer greater than or equal to 2; the plurality of data lines DL include the k-1 th data line DLk-1, the k th data line DLk and the k+1 th data line DLk+1, which are respectively electrically connected To the k-1 th pixel row Rk-1, the k th pixel row Rk, and the k+1 th pixel row Rk+1.

Please refer to FIG. 1 , it is worth noting that, in the top view of the pixel array substrate 100 , the xnth transition line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, and the th The x transition line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1. In other words, the xn-th transition line VGx-n and the x-th transition line VGx are adjacent to the same k-th data line DLk, and are located on the left and right sides of the same k-th data line DLk, respectively. Please refer to FIG. 1 and FIG. 2 , in particular, since the start time tonx of the gate pulse signal S _VGx of the xth patch cord VGx and the end of the gate pulse signal S _VGx-n of the xnth patch cord VGx-n The time toffx-n overlaps in timing, so the capacitive coupling effect between the xn-th patch VGx-n and the k-th data line DLk and the capacitive coupling effect between the x-th patch VGx and the k-th data line DLk Can be offset, so that the potential of the pixel electrode 194 (drawn in FIG. 3 ) of the pixel structure PX located in the k-th pixel row Rk and electrically connected to the x-th scan line HGx is not easy to be set on the left and right sides thereof. Multiple patch cords VG deviate too much from the ideal value. In this way, the pixel structure PX located in the k-th pixel row Rk and electrically connected to the x-th scan line HGx is less likely to exhibit abnormal brightness (for example, excessive brightness), thereby making the oblique bright line described in the prior art difficult problem is improved. The following specific examples are described in conjunction with other drawings.

FIG. 5 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

FIG. 6 shows a plurality of gate pulse signals S _{HG1 ˜S} HG18 of the first scan line HG1 to the eighteenth scan line HG18 according to an embodiment of the present invention.

Referring to FIG. 5, a plurality of pixel structures PX are disposed on the substrate 110, and are arranged in the first pixel row R1 to the 23rd pixel row R23, wherein the first pixel row R1 to the 23rd pixel row R23 are in the first pixel row R1 to the 23rd pixel row R23. arranged in one direction d1. The plurality of scan lines HG include the first scan line HG1 to the eighteenth scan line HG18, and are sequentially arranged in the second direction d2. The plurality of data lines DL include a first data line DL1 to a 23rd data line DL23, which are electrically connected to the first pixel row R1 to the 23rd pixel row R23, respectively.

Referring to FIG. 5 and FIG. 6 , the first to eighteenth scan lines HG1 to HG18 respectively have gate pulse signals S _HG1 to S _HG18 . In this embodiment, the first scan line HG1 to the eighteenth scan line HG18 are sequentially turned on with a time delay, wherein the time length of the time delay is t (as shown in FIG. 6 ), and the gate pulse signal _SHG1 to the gate The pulse time length of each of the polar pulse signals _SHG18 is Tp (as shown in FIG. 6 ), n=Tp/t, and n is, for example, 8, but the invention is not limited thereto.

Referring to FIG. 5 , the plurality of transfer wires VG include a first transfer wire VG1 to an eighteenth transfer wire VG18 , which are electrically connected to the first scan line HG1 to the eighteenth scan line HG18 , respectively. Please refer to FIG. 5 and FIG. 6 , the first switching wire VG1 to the eighteenth switching wire VG18 respectively have the gate pulse signal S _VG1 to the gate pulse signal S _VG18 , wherein the gate pulse signal S of the first switching wire VG1 The gate pulse signals S _VG18 from _VG1 to the eighteenth transfer wire VG18 are respectively the same as the gate pulse signals S HG1 of the first scan line _HG1 to the gate pulse signals S _HG18 of the eighteenth scan line HG18 .

Please refer to FIG. 1 and FIG. 2 again, the plurality of scan lines HG include the xn-th scan line HGx-n to the x+n-th scan line HGx+n sequentially arranged in the second direction d2, where x is greater than or equal to A positive integer of 2, n is a positive integer and less than x; the start time tonx of the gate pulse signal S _HGx of the xth scan line HGx and the end time toffx of the gate pulse signal S _HGx-n of the xnth scan line HG -n overlaps in time sequence; the end time toffx of the gate pulse signal S _HGx of the xth scan line HG and the start time tonx+n of the gate pulse signal S _HGx+n of the x+nth scan line HG are in the time sequence Overlapping on top; the plurality of patch cords VG include the xnth patch cord VGx-n, the xth patch cord VGx and the x+nth patch cord VGx+n, which are respectively electrically connected to the xnth scan line HGx-n , the xth scan line HGx and the x+nth scan line HGx+n; the plurality of pixel rows R include the k-1th pixel row Rk-1, the kth pixel row Rk-1, the kth pixel row The pixel row Rk and the k+1 th pixel row Rk+1, k is a positive integer greater than or equal to 2; the plurality of data lines DL include the k-1 th data line DLk-1, the k th data line DLk and the k+1 th data line The data line DLk+1 is electrically connected to the k-1 th pixel row Rk-1, the k th pixel row Rk, and the k+1 th pixel row Rk+1, respectively. In the top view of the pixel array substrate 100 , the xn-th connecting line VGx-n is disposed between the k-1-th data line DLk-1 and the k-th data line DLk, and the x-th connecting line VGx is disposed on the k-th data line Between the line DLk and the k+1 th data line DLk+1; the following description is illustrated by taking FIG. 5 and FIG. 6 as an example.

Referring to FIG. 5 and FIG. 6 , in one part of the pixel array substrate 100 of the present embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 9, and 2, respectively (that is, n=8, x=9, k=2). Referring to FIG. 5 and FIG. 6 , in one part of the pixel array substrate 100 of the present embodiment, the plurality of scan lines HG include the first scan line HG1 to the 17th scan line arranged in sequence in the second direction d2 Line HG17; the start time ton9 of the gate pulse signal S _HG9 of the ninth scan line HG9 and the end time toff1 of the gate pulse signal S _HG1 of the first scan line HG1 overlap in timing; The end time toff9 of the gate pulse signal S _HG9 and the start time ton17 of the gate pulse signal S _HG17 of the 17th scan line HG17 overlap in time sequence; the plurality of transfer lines VG include the first transfer line VG1, the ninth turn The wiring VG9 and the 17th transition wiring VG17 are electrically connected to the first scan line HG1, the ninth scan line HG9 and the seventeenth scan line HG17 respectively; the plurality of pixel rows R are included in the first direction d1 in accordance with the The first pixel row R1, the second pixel row R2 and the third pixel row R3 arranged in sequence; the plurality of data lines DL include the first data line DL1, the second data line DL2 and the third data line DL3, which are electrically It is connected to the first pixel row R1, the second pixel row R2 and the third pixel row R3. In the top view of the pixel array substrate 100, the first transition line VG1 is disposed between the first data line DL1 and the second data line DL2, and the ninth transition line VG is disposed between the second data line DL2 and the third data line DL2 between lines DL3.

Referring to FIG. 5 , in other words, the first transfer line VG1 and the ninth transfer line VG9 are adjacent to the second data line DL2 and located on the left and right sides of the second data line DL2 , respectively. Please refer to FIG. 5 and FIG. 6 , in particular, since the start time ton9 of the gate pulse signal S _VG9 of the ninth patch cord VG9 and the end time toff1 of the gate pulse signal S _VG1 of the first patch cord VG1 are in the timing sequence Therefore, the capacitive coupling effect between the first connecting wire VG1 and the second data line DL2 and the capacitive coupling effect between the ninth connecting wire VG9 and the second data line DL2 can be canceled, so that the second connecting wire VG9 and the second data line DL2 The potentials of the pixel electrodes 194 (drawn in FIG. 3 ) of the pixel structure PX of the pixel row R2 and electrically connected to the ninth scan line HG9 are not easily deviated excessively due to the plurality of patch wires VG disposed on the left and right sides thereof. at the ideal value. In this way, the pixel structure PX located in the second pixel row R2 and electrically connected to the ninth scan line HG9 is less likely to exhibit abnormal brightness (for example, brighter), thereby making the oblique brightness described in the prior art possible. Line issues have been improved.

Please refer to FIG. 1 and FIG. 2 again, the plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n, which are sequentially arranged in the second direction d2, and the xth scan line The end time toffx of the gate pulse signal S _HGx of HGx and the start time tonx+n of the gate pulse signal S _HGx+n of the x+nth scan line HGx+n overlap in timing; Including the x+nth transition line VGx+n, which is electrically connected to the x+nth scan line HGx+n; the plurality of pixel rows R further includes the k+2th pixel row Rk+2, the k-1th pixel row Rk+2 The pixel row Rk-1, the k-th pixel row Rk, the k+1-th pixel row Rk+1, and the k+2-th pixel row Rk+2 are sequentially arranged in the first direction d1; the plurality of data lines DL are further Including the k+2 th data line DLk+2, which is electrically connected to the k+2 th pixel row Rk+2; in the top view of the pixel array substrate 100, the x+n th switching line VGx+n is disposed on the k th pixel row Rk+2 Between the +1 data line DLk+1 and the k+2 th data line DLk+2; the following description is illustrated by taking FIG. 5 and FIG. 6 as an example.

Referring to FIG. 5 and FIG. 6 , in one part of the pixel array substrate 100 of the present embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 9, and 2, respectively (that is, n=8, x=9, k=2). Referring to FIG. 5 and FIG. 6 , in one part of the pixel array substrate 100 of the present embodiment, the plurality of scan lines HG include the first scan line HG1 to the 17th scan line arranged in sequence in the second direction d2 Line HG17, the end time toff9 of the gate pulse signal S _HG9 of the ninth scan line HG9 and the start time ton17 of the gate pulse signal S _HG17 of the seventeenth scan line HG17 overlap in timing; Including the 17th transition line VG17, which is electrically connected to the 17th scan line HG17; the plurality of pixel rows R further includes the fourth pixel row R4, the first pixel row R1, the second pixel row R2, and the third pixel row R2. The pixel row R3 and the fourth pixel row R4 are sequentially arranged in the first direction d1; the plurality of data lines DL further include a fourth data line DL4, which is electrically connected to the fourth pixel row R4; on the pixel array substrate 100 In a plan view of , the 17th transition line VG17 is disposed between the third data line DL3 and the fourth data line DL4.

Referring to FIG. 5 , in other words, the ninth transition line VG9 and the seventeenth transition line VG17 are adjacent to the third data line DL3 and located on the left and right sides of the third data line DL3 , respectively. Referring to FIG. 5 and FIG. 6 , similarly, since the end time toff9 of the gate pulse signal S _VG9 of the ninth patch cord VG9 and the start time ton17 of the gate pulse signal S _VG17 of the seventeenth patch cord VG17 are The timing overlaps, so the capacitive coupling effect between the ninth patch cord VG9 and the third data line DL3 and the capacitive coupling effect between the seventeenth patch cord VG9 and the third data line DL3 can cancel out, so that the The potential of the pixel electrodes 194 (drawn in FIG. 3 ) of the pixel structure PX of the pixel structure PX of the 3 pixel rows R3 and electrically connected to the 17th scan line HG17 is not easily excessive due to the plurality of patch wires VG disposed on the left and right sides thereof. deviation from the ideal value. In this way, the pixel structure PX located in the third pixel row R3 and electrically connected to the seventeenth scan line HG17 is less likely to exhibit abnormal brightness (eg, brighter), thereby making the oblique brightness described in the prior art possible. Line issues have been improved.

FIG. 7 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 8 shows a plurality of gate pulse signals S _HGx-n to S _HGx+n of the xn th scan line HGx-n to the x+n th scan line HGx+n of FIG. 7 .

Please refer to FIG. 7 and FIG. 8 , the plurality of scan lines HG include the xnth scan line HGx-n to the xth scan line HGx arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, n is a positive integer less than x, the start time tonx of the gate pulse signal S _HGx of the xth scan line HGx and the end time toffx-n of the gate pulse signal S _HGx-n of the xnth scan line HGx-n are overlapping in timing; the plurality of patch cords VG include the xnth patch cord VGx-n and the xth patch cord VGx, which are respectively electrically connected to the xnth scan line HGx-n and the xth scan line HGx; a plurality of The pixel row R includes the k-1 th pixel row Rk-1, the k th pixel row Rk, the k+1 th pixel row Rk+1 and the k+2 th pixel row which are sequentially arranged in the first direction d1 Rk+2, k is a positive integer greater than or equal to 2; the plurality of data lines DL include the k-1 th data line DLk-1, the k th data line DLk, the k+1 th data line DLk+1 and the k+2 th data line The data line DLk+2 is electrically connected to the k-1 th pixel row Rk-1, the k th pixel row Rk, the k+1 th pixel row Rk+1, and the k+2 th pixel row Rk+2 respectively ; The pixel array substrate 100 further includes a first common line VSS1; in the top view of the pixel array substrate 100, the xnth transition line VGx-n is arranged between the k-1th data line DLk-1 and the kth data line DLk During this time, the x-th transition line VGx is arranged between the k-th data line DLk and the k+1-th data line DLk+1, and the first common line VSS1 is arranged between the k+1-th data line DLk+1 and the k+2-th data line DLk+1 Between the data lines DLk+2; the following description is given by taking FIG. 5 and FIG. 6 as an example.

Referring to FIGS. 5 and 6 , in one part of the pixel array substrate 100 of the present embodiment, n, x, and k described in the previous paragraph can be regarded as 8, 17, and 3, respectively (that is, n=8, x=17, k=3). Please refer to FIG. 5 and FIG. 6 , the plurality of scan lines HG include the ninth scan line HG9 to the seventeenth scan line HG17 arranged in sequence in the second direction d2, and the gate pulse signal S of the seventeenth scan line HG17 The start time _ton17 of HG17 and the end time toff9 of the gate pulse signal S _HG9 of the ninth scan line HG9 overlap in time sequence; the plurality of transfer lines VG include the ninth transfer line VG9 and the seventeenth transfer line VG17, respectively Electrically connected to the ninth scan line HG9 and the seventeenth scan line HG17; the plurality of pixel rows R include the second pixel row R2, the third pixel row R3, the fourth pixel row R2 and the fourth pixel row R2 arranged in sequence in the first direction d1 A pixel row R4 and a fifth pixel row R5; the plurality of data lines DL include a second data line DL2, a third data line DL3, a fourth data line DL4 and a fifth data line DL5, which are electrically connected to the second data line DL2 respectively. The pixel row R2, the third pixel row R3, the fourth pixel row R4, and the fifth pixel row R5; the pixel array substrate 100 further includes a first common line VSS1a; in the top view of the pixel array substrate 100, the ninth pixel row The transfer line VG9 is disposed between the second data line DL2 and the third data line DL3, the seventeenth transfer line VG17 is disposed between the third data line DL3 and the fourth data line DL4, and the first common line VSS1a is disposed on the between the fourth data line DL4 and the fifth data line DL5.

Referring to FIGS. 5 and 6 , in another part of the pixel array substrate 100 of the present embodiment, n, x, and k described in the previous two paragraphs can also be regarded as 8, 11, and 11, respectively (ie, n =8, x=11, k=11). Please refer to FIG. 5 and FIG. 6 , the plurality of scan lines HG include the third scan line HG3 to the eleventh scan line HG11 arranged in sequence in the second direction d2, and the gate pulse signal S of the eleventh scan line HG11 The start time ton11 of _HG11 and the end time toff3 of the gate pulse signal S _HG3 of the third scan line HG3 overlap in time sequence; the plurality of transfer lines VG include the third transfer line VG3 and the eleventh transfer line VG11, respectively Electrically connected to the 3rd scan line HG3 and the 11th scan line HG11; the plurality of pixel rows R include the 10th pixel row R10, the 11th pixel row R11, the 12th pixel row R10 and the 12th pixel row R10 arranged in sequence in the first direction d1 A pixel row R12 and a thirteenth pixel row R13; the plurality of data lines DL include a tenth data line DL10, an eleventh data line DL11, a twelfth data line DL12 and a thirteenth data line DL13, which are electrically connected to the tenth data line respectively The pixel row R10, the 11th pixel row R11, the 12th pixel row R12, and the 13th pixel row R13; the pixel array substrate 100 further includes a first common line VSS1b; in the top view of the pixel array substrate 100, the third The transfer line VG3 is disposed between the tenth data line DL10 and the eleventh data line DL11, the eleventh transfer line VG11 is disposed between the eleventh data line DL11 and the twelfth data line DL12, and the first common line VSS1b is disposed on the between the twelfth data line DL12 and the thirteenth data line DL13.

Referring to FIGS. 5 and 6 , in another part of the pixel array substrate 100 of the present embodiment, n, x, and k described in the previous three paragraphs can also be regarded as 8, 18, and 15, respectively (ie, n =8, x=18, k=15). Please refer to FIG. 5 and FIG. 6 , the plurality of scan lines HG include the tenth scan line HG10 to the eighteenth scan line HG18 arranged in sequence in the second direction d2, and the gate pulse signal S of the eighteenth scan line HG18 The start time _ton18 of HG18 and the end time toff10 of the gate pulse signal S _HG10 of the tenth scan line HG10 overlap in time sequence; the plurality of transfer lines VG include the tenth transfer line VG10 and the eighteenth transfer line VG18, respectively. Electrically connected to the 10th scan line HG10 and the 18th scan line HG18; the plurality of pixel rows R include the 14th pixel row R14, the 15th pixel row R15, the 16th pixel row R14 and the 16th pixel row R14 arranged in sequence in the first direction d1 A pixel row R16 and a 17th pixel row R17; the plurality of data lines DL include a 14th data line DL14, a 15th data line DL15, a 16th data line DL16 and a 17th data line DL17, which are electrically connected to the 14th data line respectively The pixel row R14, the 15th pixel row R15, the 16th pixel row R16, and the 17th pixel row R17; the pixel array substrate 100 further includes a first common line VSS1c; in the top view of the pixel array substrate 100, the 10th pixel row The transfer line VG10 is disposed between the 14th data line DL14 and the fifteenth data line DL15, the eighteenth transfer line VG18 is disposed between the fifteenth data line DL15 and the sixteenth data line DL16, and the first common line VSS1c is disposed on the Between the sixteenth data line DL16 and the seventeenth data line DL17.

Referring to FIG. 5 and FIG. 6 , in another part of the pixel array substrate 100 of the present embodiment, n, x, and k described in the previous four paragraphs can also be regarded as 8, 14, and 18, respectively (ie, n =8, x=14, k=18). Please refer to FIG. 5 and FIG. 6 , the plurality of scan lines HG include the sixth scan line HG6 to the fourteenth scan line HG14 arranged in sequence in the second direction d2, and the gate pulse signal S of the fourteenth scan line HG14 The start time _ton14 of HG14 and the end time toff6 of the gate pulse signal S _HG6 of the sixth scan line HG6 overlap in time sequence; the plurality of patch cords VG include the sixth patch cord VG6 and the 14th patch cord VG14, respectively. Electrically connected to the 6th scan line HG6 and the 14th scan line HG14; the plurality of pixel rows R include the 17th pixel row R17, the 18th pixel row R18, the 19th pixel row R17 and the 19th pixel row R17 arranged in sequence in the first direction d1 A pixel row R19 and a 20th pixel row R20; the plurality of data lines DL includes a 17th data line DL17, an 18th data line DL18, a 19th data line DL19 and a 20th data line DL20, which are electrically connected to the 17th data line respectively The pixel row R17, the 18th pixel row R18, the 19th pixel row R19, and the 20th pixel row R20; the pixel array substrate 100 further includes a first common line VSS1d; In the top view of the pixel array substrate 100, the sixth The transfer line VG6 is disposed between the seventeenth data line DL17 and the eighteenth data line DL18, the fourteenth transfer line VG14 is disposed between the eighteenth data line DL18 and the nineteenth data line DL19, and the first common line VSS1d is disposed on the Between the 19th data line DL19 and the 20th data line DL20.

FIG. 9 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 10 shows a plurality of gate pulse signals S _HGx-n to S _HGx+n of the xn th scan line HGx-n to the x+n th scan line HGx+n of FIG. 9 .

9 and FIG. 10 , the plurality of scan lines HG include the xnth scan line HGx-n to the xth scan line HGx arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, n is a positive integer less than x, the start time tonx of the gate pulse signal S _HGx of the xth scan line HGx and the end time toffx-n of the gate pulse signal S _HGx-n of the xnth scan line HGx-n are overlapping in timing; the plurality of scan lines HG further include the mth scan line HGm, where m is a positive integer greater than 2, and |xm| is not equal to n; the plurality of patch cords VG include the xnth patch cord VGx-n, the The x-th switching line VGx and the m-th switching line VGm are electrically connected to the xn-th scan line HGx-n, the x-th scan line HGx, and the m-th scan line HGm, respectively; the plurality of pixel rows R are included in the first direction The k-1 pixel row Rk-1, the k pixel row Rk, the k+1 pixel row Rk+1, and the k+2 pixel row Rk+2 are arranged in sequence on d1, where k is greater than or A positive integer equal to 2; the plurality of data lines DL include the k-1 th data line DLk-1, the k th data line DLk, the k+1 th data line DLk+1, and the k+2 th data line DLk+2, which are respectively electrically connected to the k-1 pixel row Rk-1, the k pixel row Rk, the k+1 pixel row Rk+1, and the k+2 pixel row Rk+2; on the pixel array substrate 100 In the top view, the xn th transition line VGx-n is disposed between the k-1 th data line DLk-1 and the k th data line DLk, and the x th transition line VGx is disposed between the k th data line DLk and the k+1 th data line Between the lines DLk+1, the m-th transition line VGm is disposed between the k+1-th data line DLk+1 and the k+2-th data line DLk+2; the following description is illustrated by taking FIG. 5 and FIG. 6 as an example.

Referring to FIG. 5 and FIG. 6 , in one part of the pixel array substrate 100 of the present embodiment, n, x, k, and m described in the previous paragraph can be regarded as 8, 16, 21, and 4, respectively (ie, n=8, x=16, k=21, m=4). Please refer to FIG. 5 and FIG. 6 , the plurality of scan lines HG include the eighth scan line HG8 to the sixteenth scan line HG16 arranged in sequence in the second direction d2, and the gate pulse signal S of the sixteenth scan line HG16 The start time _ton16 of HG16 and the end time toff8 of the gate pulse signal S _HG8 of the eighth scan line HG8 overlap in timing; the plurality of scan lines HG further include the fourth scan line HG4, and 4 is a positive integer greater than 2, |16-4| is not equal to 8; the multiple patch cables VG include the eighth patch cable VG8, the sixteenth patch cable VG16 and the fourth patch cable VG4, which are electrically connected to the eighth scan line HG8 and the fourth patch cable VG4 respectively. 16 scanning lines HG16 and the fourth scanning line HG4; the plurality of pixel rows R include the 20th pixel row R20, the 21st pixel row R21, the 22nd pixel row R22 and the 20th pixel row R22 arranged in sequence in the first direction d1. 23 pixel rows R23; the plurality of data lines DL include the 20th data line DL20, the 21st data line DL21, the 22nd data line DL22 and the 23rd data line DL23, which are respectively electrically connected to the 20th pixel row R20 and the 21st data line DL23. The pixel row R21, the 22nd pixel row R22 and the 23rd pixel row R23; in the top view of the pixel array substrate 100, the eighth transition line VG8 is disposed between the 20th data line DL20 and the 21st data line DL21 , the 16th transfer line VG16 is arranged between the 21st data line DL21 and the 22nd data line DL22, and the fourth transfer line VG4 is arranged between the 22nd data line DL22 and the 23rd data line DL23.

That is to say, in this embodiment, at one place of the pixel array substrate 100 , there are a plurality of transfer lines VG (for example: the 8th turn) located on the left and right sides of the same data line DL (for example, the 21st data line DL21 ). The starting times (eg: ton8, ton16) of the gate pulse signals (eg: S _VG8 , S _VG16 ) of the wiring VG8 and the 16th patch wiring VG16) may differ by the time length t of the time delay n (eg: 8 t); however, at another part of the pixel array substrate 100, there are a plurality of patch cords VG (eg, the 16th patch cord) located on the left and right sides of the same data line DL (eg, the 22nd data line DL22). The start times (eg, ton16, ton4) of the gate pulse signals (eg, S _VG16 , S _VG4 ) of VG16 and the fourth switching wire VG4) may not differ by n t (eg, 12 t).

FIG. 11 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 12 shows a plurality of gate pulse signals S _HGy-n to S _HGy of the y-th scan line HGy-n to the y-th scan line HGy of FIG. 11 .

Please refer to FIG. 11 , the plurality of scan lines HG include the y-nth scan line HGy-n to the yth scan line HGy arranged in sequence in the second direction d2, y is a positive integer greater than or equal to 2, and n is positive Integer and less than y.

Referring to FIG. 11 and FIG. 12 , the y-th scan line HGy-n to the y-th scan line HGy have gate pulse signals S _HGy-n to S _HGy , respectively. Specifically, the y-th scan line HGy-n has a gate pulse signal S _HGy-n , the y-n+1-th scan line HGy-n+1 has a gate pulse signal S _HGy-n+1 , and the y-th scan line HGy-n+1 has a gate pulse signal S HGy-n+1 . -n+2 scanning lines HGy-n+2 have gate pulse signals S _HGy-n+2 , . . . , and the y-th scanning line HGy has gate pulse signals S _HGy .

Referring to FIG. 11 and FIG. 12 , the y-th scan line HGy-n to the y-th scan line HGy are sequentially turned on with a time delay, wherein the time length of the time delay is t (as shown in FIG. 12 ), and the gate pulse signal The pulse time length of each of _SHGy-n to gate pulse signal _SHGy is Tp (drawn in FIG. 12 ), and n=Tp/t. The start time tony of the gate pulse signal S _HGy of the y-th scanning line HGy and the ending time toffy-n of the gate pulse signal S _HGy-n of the y-th scanning line HGy-n overlap in timing.

Referring to FIG. 11 , the plurality of patch cords VG include a yn-th patch cord VGy-n and a y-th patch cord VGy, which are electrically connected to the y-th scan line HGy-n and the y-th scan line HGy, respectively. Please refer to FIG. 11 and FIG. 12 , the yn-th switching wire VGy-n and the y-th switching wire VGy respectively have the gate pulse signal S _VGy-n and the gate pulse signal S _VGy , wherein the yn-th switching wire VGy-n The gate pulse signal S _VGy-n and the gate pulse signal S VGy of the y-th switching line VGy are respectively connected with the gate pulse signal S _{HGy -n} of the y-th scanning line HGy-n and the y-th scanning line HGy The gate pulse signal S _{HGy is} the same.

Referring to FIG. 11 , the plurality of pixel rows R include the q-1 th pixel row Rq-1, the q th pixel row Rq, the q+1 th pixel row Rq+1 and the The q+2th pixel row Rq+2, q is a positive integer greater than or equal to 2; the multiple data lines DL include the q-1th data line DLq-1, the qth data line DLq, and the q+1th data line DLq The +1 and q+2th data lines DLq+2 are electrically connected to the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+th pixel row, respectively 2 The pixel row Rq+2, q is a positive integer greater than or equal to 2.

Referring to FIG. 11 , it is worth noting that in the top view of the pixel array substrate 100 , the y-th transition line VGy is disposed between the q-1-th data line DLq-1 and the q-th data line DLq, and the y-nth transition line The wiring VGy-n is disposed between the qth data line DLq and the q+1th data line DLq+1; the following description is illustrated by taking FIG. 5 and FIG. 6 as an example.

Referring to FIGS. 5 and 6 , in one part of the pixel array substrate 100 of the present embodiment, the aforementioned n, y, and q corresponding to FIGS. 11 and 12 can be regarded as 8, 13, and 6, respectively (ie, n=8, y=13, q=6). Referring to FIGS. 5 and 6 , in one part of the pixel array substrate 100 of the present embodiment, the plurality of scan lines HG include the fifth scan line HG5 to the thirteenth scan line arranged in sequence in the second direction d2 Line HG13; the start time ton13 of the gate pulse signal S _HG13 of the thirteenth scan line HG13 and the end time toff5 of the gate pulse signal S _HG5 of the fifth scan line HG5 overlap in timing. The plurality of transfer lines VG include a fifth transfer line VG5 and a thirteenth transfer line VG13, which are electrically connected to the fifth scan line HG5 and the thirteenth scan line HG13, respectively. The fifth transfer line VG5 and the thirteenth transfer line VG13 respectively have the gate pulse signal S _VG5 and the gate pulse signal S _VG13 , wherein the gate pulse signal S _VG5 of the fifth transfer line VG5 and the thirteenth transfer line VG13 The gate pulse signal S _VG13 is the same as the gate pulse signal S _HG5 of the fifth scanning line HG5 and the gate pulse signal S _HG13 of the thirteenth scanning line HG13 , respectively. The plurality of pixel rows R include the fifth pixel row R5, the sixth pixel row R6, the seventh pixel row R7 and the eighth pixel row R8 arranged in sequence in the first direction d1; the plurality of data lines DL include The fifth data line DL5, the sixth data line DL6, the seventh data line DL7 and the eighth data line DL8 are respectively electrically connected to the fifth pixel row R5, the sixth pixel row R6, the seventh pixel row R7 and the The 8th pixel row R8.

Please refer to FIG. 5 , it is worth noting that in the top view of the pixel array substrate 100 , the thirteenth transition line VG13 is disposed between the fifth data line DL5 and the sixth data line DL6 , and the fifth transition line VG5 is disposed between the sixth data line DL6 and the seventh data line DL7. Similarly, the thirteenth patch cord VG13 and the fifth patch cord VG5 are adjacent to the sixth data line DL6 and are located on the left and right sides of the sixth data line DL6, respectively. Referring to FIG. 5 and FIG. 6 , similarly, since the end time toff5 of the gate pulse signal S _VG5 of the fifth patch cord VG5 and the start time ton13 of the gate pulse signal S _VG13 of the thirteenth patch cord VG13 are at The timings overlap, so the capacitive coupling effect between the thirteenth patch cord VG13 and the sixth data line DL6 and the capacitive coupling effect between the fifth patch cord VG5 and the sixth data line DL6 can cancel out, so that the The potential of the pixel electrodes 194 (drawn in FIG. 3 ) of the pixel structure PX of the 6 pixel rows R6 and electrically connected to the thirteenth scan line HG13 is not easily caused by the plurality of patch cords VG disposed on the left and right sides thereof. deviation from the ideal value. Therefore, the pixel structure PX located in the sixth pixel row R6 and electrically connected to the thirteenth scan line HG13 is less likely to exhibit abnormal brightness (eg, bright), thereby making the oblique brightness described in the prior art possible. Line issues have been improved.

It should be noted that, the two transition lines VG located on the left and right sides of the same data line DL and arranged in sequence in the first direction d1 can cancel the multiple capacitive effects of the same data line DL. However, the present invention is not limited, the start time of the gate pulse signal of one of the patch cords VG arranged first in the first direction d1 must be earlier than the start of the gate pulse signal of the other patch cord VG arranged later time; the present invention is also not limited, the gate of one of the transfer lines VG is arranged first in the first direction d1 The start time of the pole pulse signal must be later than the start time of the gate pulse signal of another patch cord VG arranged in the rear.

For example, in one part of the pixel array substrate 100 in FIG. 5 , two transitions are arranged on the left and right sides of the same data line (eg, the second data line DL2 ) and are sequentially arranged in the first direction d1 lines (eg: 1st patch cord VG1 and ninth patch cord VG9), which can cancel multiple capacitive effects of the same data line (eg: 2nd data line DL2), in the first direction The start time of the gate pulse signal of one of the patch cords VG arranged first on d1 can be earlier than the start time of the gate pulse signal of the other patch cord VG arranged later (for example: the first row in the first direction d1 ) The start time ton1 of the gate pulse signal S _VG1 of the first patch cord VG1 may be earlier than the start time ton9 of the gate pulse signal S _VG9 of the ninth patch cord VG9 arranged later; Another part of the array substrate 100 is a plurality of patch cords (eg, the thirteenth patch cord) disposed on the left and right sides of the same data line (eg, the sixth data line DL6 ) and arranged in sequence in the first direction d1 VG13 and the fifth patch cord VG5), which can cancel the capacitive effects of the same data line (eg, the sixth data line DL6), and arrange one patch cord first in the first direction d1 The start time of the gate pulse signal of VG may be later than the start time of the gate pulse signal of another patch cord VG arranged later (for example: the gate of the thirteenth patch cord VG13 arranged first in the first direction d1 The start time ton13 of the pulse signal S _VG13 may be later than the start time ton5 of the gate pulse signal S _VG5 of the fifth switching wire VG5 arranged afterward.

11 and 12 again, the pixel array substrate 100 further includes a second common line VSS2; in the top view of the pixel array substrate 100, the y-th transition line VGy is arranged between the q-1th data line DLq-1 and the qth data line DLq, the y-nth transition line VGy-n is arranged between the qth data line DLq and the q+1th data line DLq+1, and the The two common lines VSS2 are disposed between the q+1 th data line DLq+1 and the q+2 th data line DLq+2; the following description is illustrated by taking FIG. 5 and FIG. 6 as an example.

Referring to FIG. 5 , in one part of the pixel array substrate 100 of the present embodiment, the aforementioned n, y, and q corresponding to FIG. 11 and FIG. 12 can be regarded as 8, 13, and 6, respectively (ie, n=8 , y=13, q=6). Referring to FIG. 5 , in the top view of the pixel array substrate 100 , the thirteenth connecting line VG13 is disposed between the fifth data line DL5 and the sixth data line DL6 , and the fifth connecting line VG5 is disposed on the sixth data line DL6 and the seventh data line DL7, and the second common line VSS2 is disposed between the seventh data line DL7 and the eighth data line DL8.

FIG. 13 is a schematic top view of one part of the pixel array substrate 100 according to an embodiment of the present invention.

FIG. 14 shows a plurality of gate pulse signals S _HGy-n to S _HGy of the y-th scan line HGy-n to the y-th scan line HGy of FIG. 13 .

13 and FIG. 14 , the plurality of scan lines HG include the yth scan line HGy-n to the yth scan line HGy arranged in sequence in the second direction d2, where y is a positive integer greater than or equal to 2, n is a positive integer less than y, the start time tony of the gate pulse signal S _HGy of the y-th scan line HGy and the end time toffy-n of the gate pulse signal S _HGy-n of the y-th scan line HGy-n are at The timing overlaps; the plurality of scan lines HG further includes the p-th scan line HGp; the plurality of transfer lines VG include the yn-th transfer line VGy-n and the y-th transfer line VGy, which are respectively electrically connected to the yn-th scan line Line HGy-n and the yth scan line HGy; the plurality of transfer lines VG further include the pth transfer line VGp, which is electrically connected to the pth scan line HGp; the plurality of pixel rows R are included in the first direction d1 The q-1 th pixel row Rq-1, the q th pixel row Rq, the q+1 th pixel row Rq+1, and the q+2 th pixel row Rq+2 are arranged in sequence, and q is greater than or equal to 2 A positive integer of ; the plurality of data lines DL include the q-1th data line DLq-1, the qth data line DLq, the q+1th data line DLq+1, and the q+2th data line DLq+2, which are respectively electrically connected to the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1, and the q+2th pixel row Rq+2; in the top view of the pixel array substrate 100 , the yth transition line VGy is arranged between the q-1th data line DLq-1 and the qth data line DLq, and the ynth transition line VGy-n is arranged between the qth data line DLq and the q+1th data line DLq +1, the p-th transition line VGp is arranged between the q+1-th data line DLq+1 and the q+2-th data line DLq+2; in particular, p is a positive integer greater than 2, and |yp| Not equal to n; the following description will be given by taking FIG. 5 and FIG. 6 as an example.

Referring to FIGS. 5 and 6 , in one part of the pixel array substrate 100 of the present embodiment, the aforementioned n, y, q, and p corresponding to FIGS. 13 and 14 can be regarded as 8, 15, 9, 3 (ie, n=8, y=15, q=9, p=3). Referring to FIGS. 5 and 6 , in the top view of the pixel array substrate 100 , the plurality of scan lines HG include the seventh scan line HG7 to the fifteenth scan line HG15 arranged in sequence in the second direction d2 , the fifteenth scan line HG15 The start time ton15 of the gate pulse signal S _HG15 of one scan line HG15 and the end time toff7 of the gate pulse signal S _HG7 of the seventh scan line HG7 overlap in timing; the plurality of scan lines HG further includes the third scan line HG3; the plurality of transfer lines VG include the seventh transfer line VG7 and the fifteenth transfer line VG15, which are electrically connected to the seventh scan line HG7 and the fifteenth scan line HG15 respectively; the plurality of transfer lines VG further include The third switching wire VG3 is electrically connected to the third scanning line HG3; the plurality of pixel rows R include the 8th pixel row R8, the 9th pixel row R9, the 10th pixel row R8 and the 10th pixel row R8 arranged in sequence in the first direction d1 A pixel row R10 and an eleventh pixel row R11; the plurality of data lines DL include an eighth data line DL8, a ninth data line DL9, a tenth data line DL10 and an eleventh data line DL11, which are electrically connected to the eighth data line DL11 respectively. The pixel row R8, the 9th pixel row R9, the 10th pixel row R10, and the 11th pixel row R11; in the top view of the pixel array substrate 100, the 15th transition wire VG15 is disposed between the 8th data line DL8 and the 11th pixel row R11. Between the ninth data lines DL9, the seventh transfer line VG7 is set between the ninth data line DL9 and the tenth data line DL10, and the third transfer line VG3 is set between the tenth data line DL10 and the eleventh data line DL11 ; in particular, 3 is a positive integer greater than 2, and |15-3| is not equal to 8.

That is to say, in this embodiment, at one place of the pixel array substrate 100 , there are two transfer lines VG (for example: the 15th turn) located on the left and right sides of the same data line DL (for example, the ninth data line DL9 ). The starting times (eg: ton15, ton7) of the gate pulse signals (eg: S _VG15 , S _VG7 ) of the wiring VG15 and the seventh switching wiring VG7) may differ by n the time length t of the time delay (eg: 8 t; however, at another part of the pixel array substrate 100, there are a plurality of patch cords VG (eg, the seventh patch cord VG7 and The start times (eg, ton7, ton3) of the gate pulse signals (eg, S _VG7 , S _VG3 ) of the third switching wire VG3) may not differ by n t (eg, 4 t).

In the foregoing description, Tp/t=n=8 is taken as an example for description. However, the present It is not limited to this, in other embodiments, Tp/t=n, and n may also be other positive integers other than 8, which are illustrated below with reference to FIG. 15 and FIG. 16 .

FIG. 15 is a schematic top view of one part of the pixel array substrate 100A according to an embodiment of the present invention.

FIG. 16 shows a plurality of gate pulse signals S _HG1 to S _HG9 of the first scan line HG1 to the ninth scan line HG9 in FIG. 15 .

Please refer to FIG. 1 and FIG. 2 again, the plurality of scan lines HG include the xn-th scan line HGx-n to the x+n-th scan line HGx+n sequentially arranged in the second direction d2, where x is greater than or equal to A positive integer of 2, n is a positive integer and less than x; the start time tonx of the gate pulse signal S _HGx of the xth scan line HGx and the end time toffx of the gate pulse signal S _HGx-n of the xnth scan line HG -n overlaps in timing; the end time toffx of the gate pulse signal S _HGx of the xth scan line HGx and the start time tonx+n of the gate pulse signal S _HGx+n of the x+nth scan line HGx+n overlapping in timing; the plurality of patch cords VG include the xnth patch cord VGx-n, the xth patch cord VGx and the x+nth patch cord VGx+n, which are respectively electrically connected to the xnth scan line HGx -n, the x-th scanning line HGx and the x+n-th scanning line HGx+n; the plurality of pixel rows R include the k-1-th pixel row Rk-1, the k-th pixel row Rk-1 and the k-th pixel row Rk-1 arranged in sequence in the first direction d1 pixel row Rk, the k+1 th pixel row Rk+1 and the k+2 th pixel row Rk+2, where k is a positive integer greater than or equal to 2; the plurality of data lines DL includes the k-1 th data line DLk -1. The kth data line DLk, the k+1th data line DLk+1 and the k+2th data line DLk+2 are electrically connected to the k-1th pixel row Rk-1 and the kth pixel row respectively Rk, the k+1 th pixel row Rk+1, and the k+2 th pixel row Rk+2. In the top view of the pixel array substrate 100 , the xn-th connecting wire VGx-n is disposed between the k-1 th data line DLk-1 and the k-th data line DLk, and the x-th connecting wire VGx is disposed on the k-th data line Between DLk and the k+1 th data line DLk+1, and the x+n th transition line VGx+n is disposed between the k+1 th data line DLk+1 and the k+2 th data line DLk+2; the following 15 and FIG. 16 are used as examples to illustrate this.

In one part of the pixel array substrate 100A of this embodiment, n, x, and k described in the previous paragraph can be regarded as 4, 5, and 2, respectively (ie, n=4, x=5, k=2) . Please refer to FIG. 15 and FIG. 16 , the plurality of scan lines HG include the first scan line HG1 to the ninth scan line HG9 arranged in sequence in the second direction d2; the gate pulse signal S of the fifth scan line HG5 The start time ton5 of _HG5 and the end time toff1 of the gate pulse signal S _HG1 of the first scan line HG overlap in timing; the end time toff5 of the gate pulse signal S _HG5 of the fifth scan line HG5 and the ninth scan line The start times ton9 of the gate pulse signals S _HG9 of the lines HG9 overlap in time sequence; the plurality of transfer lines VG include a first transfer line VG1, a fifth transfer line VG5 and a ninth transfer line VG9, which are electrically connected respectively. to the first scan line HG1, the fifth scan line HG5 and the ninth scan line HG9; the plurality of pixel rows R include the first pixel row R1 and the second pixel row arranged in sequence in the first direction d1 R2, the third pixel row R3 and the fourth pixel row R4; the plurality of data lines DL include a first data line DL1, a second data line DL2, a third data line DL3 and a fourth data line DL4, which are electrically connected respectively to the first pixel row R1, the second pixel row R2, the third pixel row R3, and the fourth pixel row R4. In the top view of the pixel array substrate 100, the first transition line VG1 is disposed between the first data line DL1 and the second data line DL2, and the fifth transition line VG5 is disposed between the second data line DL2 and the third data line DL3, and the ninth transition line VG9 is disposed between the third data line DL3 and the fourth data line DL4.

17 is a schematic cross-sectional view of the pixel structure PX of the pixel array substrate 100 according to an embodiment of the present invention. Fig. 17 corresponds to line II-II' of Fig. 3 .

The specific structure of the pixel structure PX according to an embodiment of the present invention is illustrated below with reference to FIG. 3 and FIG. 17 . The pixel structure PX can be selectively applied to the aforementioned pixel array substrate 100 or 100A.

3 and FIG. 17 , in addition to the aforementioned thin film transistor T and the pixel electrode 194 electrically connected to the thin film transistor T, the pixel structure PX further includes a first common electrode 122 . The first common electrode 122 partially overlaps with the pixel electrode 194 to form a storage capacitor.

In this embodiment, the pixel structure PX can selectively include the second common electrode 124 , which is separated from the first common electrode 122 . Referring to FIG. 3 , in the top view of the pixel array substrate 100 , the first common electrodes 122 , the second common electrodes 124 and the scan lines HG are arranged in the second direction d2 and separated from each other.

For example, in this embodiment, the first common electrode 122, the second common electrode 124 and the scan line HG may belong to the first conductive layer and be separated from each other, and the gate Tc of the thin film transistor T may belong to the first conductive layer A conductive layer, and the gate electrode Tc of the thin film transistor T can be directly connected to the scan line HG; the source electrode Ta and drain electrode Tb of the thin film transistor T can belong to the second conductive layer and are separated from each other, and the data line DL can belong to the second conductive layer. The conductive layer, and the data line DL and the source electrode Ta of the thin film transistor T can be directly connected; but the invention is not limited to this.

Referring to FIG. 3 and FIG. 17 , the pixel structure PX further includes a conductive pattern 142 , which is electrically connected to the thin film transistor T. As shown in FIG. Specifically, the conductive pattern 142 is electrically connected to the drain electrode Tb of the thin film transistor T. As shown in FIG. For example, in this embodiment, the conductive pattern 142 and the drain electrode Tb of the thin film transistor T may belong to the same second conductive layer and may be directly connected, but the invention is not limited thereto.

The conductive pattern 142 has a first portion 142 - 1 disposed on the first common electrode 122 . Specifically, the conductive pattern 142 is disposed on the insulating layer 130 , and the first portion 142 - 1 of the conductive pattern 142 overlaps with the first common electrode 122 . In this embodiment, the conductive pattern 142 further has a second portion 142 - 2 disposed on the second common electrode 124 . Specifically, the conductive pattern 142 is disposed on the insulating layer 130 , and the second portion 142 - 2 of the conductive pattern 142 overlaps with the second common electrode 124 . In this embodiment, the conductive pattern 142 further has a third portion 142-3 connected between the first portion 142-1 and the second portion 142-2. In the top view of the pixel array substrate 100 , the third portion 142 - 3 of the conductive pattern 142 is located between the first common electrode 122 and the second common electrode 124 and does not overlap the first common electrode 122 and the second common electrode 124 .

Referring to FIG. 3 and FIG. 17 , the pixel structure PX further includes a first insulating layer 150 disposed on the conductive pattern 142 and having an opening 152 overlapping with the conductive pattern 142 . In this embodiment, the opening 152 of the first insulating layer 150 may overlap the third portion 142 - 3 of the conductive pattern 142 . For example, in this embodiment, the material of the first insulating layer 150 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials), an organic material or the above-mentioned materials. combination.

Please refer to FIG. 3 and FIG. 17 , the pixel structure PX further includes a color filter pattern 160 is disposed on the first insulating layer 150 and has an opening 162 overlapping with the conductive pattern 142 . Referring to FIG. 3 , for example, in the top view of the pixel array substrate 100 , the opening 152 of the first insulating layer 150 may be located within the opening 162 of the color filter pattern 160 .

Please refer to FIGS. 3 and 17 , the pixel structure PX further includes a second insulating layer 170 disposed on the color filter pattern 160 and having an opening 172 overlapping with the conductive pattern 142 . For example, in this embodiment, the material of the second insulating layer 170 may be an inorganic material (eg, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials), an organic material or the above-mentioned materials. combination.

In this embodiment, the pixel array substrate 100 can optionally include a transparent conductive layer 180 disposed on the second insulating layer 170 . The transparent conductive layer 180 is disposed between the film layer to which the patch cord VG belongs and the membrane layer to which the pixel electrode 194 belongs to shield the pixel electrode 194 so that the potential of the pixel electrode 194 is not easily affected by the patch cord VG. For example, in this embodiment, the material of the transparent conductive layer 180 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, Other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto.

The pixel electrode 194 is disposed on the second insulating layer 170 and is electrically connected to the conductive pattern 142 through the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 . For example, in this embodiment, the pixel structure PX may selectively include a third insulating layer 190 disposed on the second insulating layer 170 and covering the transparent conductive layer 180; the third insulating layer 190 has an opening 192, Overlaid on conductive pattern 142; draw The element electrode 194 may be disposed on the third insulating layer 190 and electrically contact the second portion of the conductive pattern 142 through the opening 192 of the third insulating layer 190 , the opening 172 of the second insulating layer 170 and the opening 152 of the first insulating layer 150 . Three parts 142-3, but the present invention is not limited to this.

In this embodiment, the opening 192 of the third insulating layer 190, the opening 172 of the second insulating layer 170, and the opening 152 of the first insulating layer 150 may be located on the third portion 142-3 of the conductive pattern 142; the third insulating layer The openings 192 of 190 , the openings 172 of the second insulating layer 170 and the openings 152 of the first insulating layer 150 can be substantially aligned; but the invention is not limited thereto.

In this embodiment, in the top view of the pixel array substrate 100 , the openings 152 of the first insulating layer 150 and the openings 172 of the second insulating layer 170 may be located between the first common electrode 122 and the second common electrode 124 without It overlaps with the first common electrode 122 and the second common electrode 124 .

Please refer to FIG. 3 , it is worth noting that, in the top view of the pixel array substrate 100 , the first portion 142 - 1 of the conductive pattern 142 covers all edges of the first common electrode 122 located in the opening 162 of the color filter pattern 160 122e. 3 and FIG. 17 , that is to say, in the opening 162 of the color filter pattern 160, there is no overlap or intersection between the edge 142e of the conductive pattern 142 and the edge 122e of the first common electrode 122, and the first A common electrode 122 , the conductive pattern 142 and the insulating layer 130 sandwiched therebetween cannot easily form a stacked structure with steep sidewalls. In the vicinity of the edge 122e of the first common electrode 122, the second insulating layer 170 does not need to be formed on the stacked structure with steep sidewalls, but can be well disposed on the first insulating layer 150. Therefore, the second insulating layer 170 can well cover the color filter pattern 160 and the sidewalls 164 thereof, so that the gas in the color filter pattern 160 cannot easily pass through the second insulating layer 170 and leak to the outside of the pixel array substrate 100 . Causes bubbles in the display panel.

Referring to FIG. 3 , in the present embodiment, in the top view of the pixel array substrate 100 , the second portion 142 - 2 of the conductive pattern 142 covers all of the second common electrode 124 located in the opening 162 of the color filter pattern 160 Edge 124e. 3 and FIG. 17 , that is to say, in the opening 162 of the color filter pattern 160, there is no overlap or intersection between the edge 142e of the conductive pattern 142 and the edge 124e of the second common electrode 124, and the first The two common electrodes 124 , the conductive pattern 142 and the insulating layer 130 sandwiched therebetween cannot easily form a stacked structure with steep sidewalls. In the vicinity of the edge 124e of the second common electrode 124, the second insulating layer 170 does not need to be formed on the stacked structure with steep sidewalls, but can be well disposed on the first insulating layer 150. Therefore, the second insulating layer 170 can well cover the color filter pattern 160 and the sidewalls 164 thereof, so that the gas in the color filter pattern 160 cannot easily pass through the second insulating layer 170 and leak to the outside of the pixel array substrate 100 . Causes bubbles in the display panel.

18 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100B according to an embodiment of the present invention.

19 is a schematic cross-sectional view of the pixel structure PX of the pixel array substrate 100B according to an embodiment of the present invention. Fig. 19 corresponds to line III-III' of Fig. 18 .

The pixel structure PX of FIGS. 18 and 19 can also be selectively applied to the aforementioned pixel array substrate 100 or 100A.

The pixel structure PX of FIGS. 18 and 19 and the pixel structure of FIGS. 3 and 17 PX is similar, so the same or similar elements are denoted by the same or similar reference numerals. The difference between the two will be described below. For the same or similar parts, please refer to the foregoing description, which will not be repeated here.

Referring to FIG. 18 and FIG. 19 , in this embodiment, the pixel structure PX may not include the second common electrode 124 of the embodiment of FIG. 3 and FIG. 17 . In addition, the pixel structure PX may not include the third insulating layer 190 and the transparent conductive layer 180 in the embodiments of FIGS. 3 and 17 .

Referring to FIG. 18 and FIG. 19 , in this embodiment, the second portion 142 - 2 of the conductive pattern 142 may be disposed on the gate electrode Tc of the thin film transistor T. As shown in FIG. Referring to FIG. 18 , in the top view of the pixel array substrate 100B, the second portion 142 - 2 of the conductive pattern 142 can cover all the edges Tcs of the gate electrode Tc located in the opening 162 of the color filter pattern 160 .

In the top view of the pixel array substrate 100B, the third portion 142 - 3 of the conductive pattern 142 is located between the first common electrode 122 and the gate electrode Tc, the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 Located on the third portion 142 - 3 of the conductive pattern 142 , the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 do not overlap the first common electrode 122 and the gate electrode Tc.

FIG. 20 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100C according to an embodiment of the present invention.

21 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention. Fig. 21 corresponds to line IV-IV' of Fig. 20 .

The pixel structure PX of FIGS. 20 and 21 can also be selectively applied to the aforementioned in the pixel array substrate 100 or 100A.

The pixel structure PX in FIGS. 20 and 21 is similar to the pixel structure PX in FIGS. 3 and 17 , so the same or similar elements are denoted by the same or similar reference numerals. The differences between the two are described below. Please refer to the foregoing description, which will not be repeated here.

Different from the pixel structure PX shown in FIGS. 3 and 17 , in the embodiments of FIGS. 20 and 21 , the pixel structure PX further includes a third common electrode 126 , a first common electrode 122 and a second common electrode 124 . separation. In this embodiment, the third common electrode 126 may belong to the first conductive layer. Referring to FIG. 20 , the conductive pattern 142 further includes a fourth portion 142 - 4 disposed on the third common electrode 126 . In the top view of the pixel array substrate 100C, the fourth portion 142 - 4 of the conductive pattern 142 covers all the edges 126 e of the third common electrode 126 within the opening 162 of the color filter pattern 160 .

22 is a schematic top view of the layout of the pixel structure PX of the pixel array substrate 100D according to an embodiment of the present invention.

23 is a schematic cross-sectional view of the pixel structure PX of the pixel array substrate 100D according to an embodiment of the present invention. Fig. 23 corresponds to the line V-V' in Fig. 22 .

The pixel structure PX shown in FIGS. 22 and 23 can also be selectively applied to the aforementioned pixel array substrate 100 or 100A.

The pixel structure PX of FIGS. 22 and 23 is similar to the pixel structure PX of FIG. 3 and FIG. 17 , so the same or similar elements are denoted by the same or similar reference numerals. The differences between the two are described below. Please refer to the foregoing description, which will not be repeated here.

In the embodiments of FIGS. 3 and 17 , an edge 142-1e (marked in FIG. 3 ) of the first portion 142-1 of the conductive pattern 142 and an edge 162e of the opening 162 of the color filter pattern 160 (marked in FIG. 3) Substantially trimmed. That is to say, in the embodiments of FIGS. 3 and 17 , the first portion 142 - 1 of the conductive pattern 142 does not exceed the opening 162 of the color filter pattern 160 .

In the embodiments of FIGS. 22 and 23 , the conductive pattern 142 further has a fifth portion 142 - 5 ; in the top view of the pixel array substrate 100D, the fifth portion 142 - 5 of the conductive pattern 142 overlaps with the first common electrode 122 and located outside the opening 162 of the color filter pattern 160 . That is, in the embodiments of FIGS. 22 and 23 , the conductive patterns 142 may extend beyond the openings 162 of the color filter patterns 160 .

100: Pixel Array Substrate 122: first common electrode 122e, 124e, 142e, 142-1e, 162e: Edge 124: Second Common Electrode 142: Conductive Pattern 142-1: Part 1 142-2: Part II 142-3: Part Three 152, 172, 162, 192: openings 180: Transparent Conductive Layer 194: Pixel Electrode DL: Data Line d1: first direction d2: second direction HG: scan line PX: pixel structure T: Thin Film Transistor Ta: source Tb: drain Tc: gate Td: semiconductor pattern VG: Adapter cable I-I’, II-II’: Section Line

Claims (20)

A pixel array substrate, comprising: a base; and A plurality of pixel structures disposed on the substrate, wherein each of the pixel structures includes: a first common electrode; a thin film transistor; a conductive pattern electrically connected to the thin film transistor, wherein a first portion of the conductive pattern is disposed on the first common electrode; a first insulating layer disposed on the conductive pattern and having an opening overlapping with the conductive pattern; a color filter pattern disposed on the first insulating layer and having an opening overlapping with the conductive pattern; a second insulating layer disposed on the color filter pattern and having an opening overlapping with the conductive pattern; and a pixel electrode disposed on the second insulating layer and electrically connected to the conductive pattern through the opening of the first insulating layer and the opening of the second insulating layer; Wherein, in the top view of the pixel array substrate, the first portion of the conductive pattern covers all edges of the first common electrode located in the opening of the color filter pattern. The pixel array substrate of claim 1, wherein each of the pixel structures further comprises: a second common electrode, separated from the first common electrode, wherein a second portion of the conductive pattern is disposed on the second common electrode; In a top view of the pixel array substrate, the second portion of the conductive pattern covers all edges of the second common electrode located in the opening of the color filter pattern. The pixel array substrate of claim 2, wherein the conductive pattern further has a third portion; in a plan view of the pixel array substrate, the third portion of the conductive pattern is located between the first common electrode and the first common electrode. Between two common electrodes, the opening of the first insulating layer and the opening of the second insulating layer are located on the third portion of the conductive pattern. The pixel array substrate of claim 2, wherein in a plan view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located between the first common electrode and the second The common electrodes are not overlapped with the first common electrode and the second common electrode. The pixel array substrate of claim 2, wherein each of the pixel structures further comprises: a third common electrode, separated from the first common electrode and the second common electrode, wherein a fourth portion of the conductive pattern is disposed on the third common electrode; In a plan view of the pixel array substrate, the fourth portion of the conductive pattern covers all edges of the third common electrode located in the opening of the color filter pattern. The pixel array substrate as recited in claim 1, wherein an edge of the first portion of the conductive pattern is substantially flush with an edge of the opening of the color filter pattern. The pixel array substrate of claim 1, wherein the conductive pattern further has a fifth portion; in a plan view of the pixel array substrate, the fifth portion of the conductive pattern overlaps with the first common electrode and is located at outside the opening of the color filter pattern. The pixel array substrate of claim 1, wherein the thin film transistor has a gate electrode separated from the first common electrode; a second portion of the conductive pattern is disposed on the gate electrode; on the pixel array substrate In the top view of , the second portion of the conductive pattern covers all edges of the gate located in the opening of the color filter pattern. The pixel array substrate of claim 8, wherein the conductive pattern further has a third portion; in a plan view of the pixel array substrate, the third portion of the conductive pattern is located between the first common electrode and the gate between the electrodes, and the opening of the first insulating layer and the opening of the second insulating layer are located on the third portion of the conductive pattern. The pixel array substrate of claim 8, wherein in a plan view of the pixel array substrate, the opening of the first insulating layer and the opening of the second insulating layer are located at the first common electrode and the gate electrode and the opening of the first insulating layer and the opening of the second insulating layer do not overlap the first common electrode and the gate electrode. The pixel array substrate of claim 1, wherein the pixel structures are arranged in a plurality of pixel rows, and the pixel rows are arranged in a first direction, and the pixel array substrate further comprises: a plurality of scan lines arranged in a second direction and electrically connected to the pixel structures, wherein the first direction and the second direction are staggered; a plurality of data lines arranged in the first direction and electrically connected to the pixel rows; and a plurality of patch cords arranged in the first direction and electrically connected to the scan lines; The scan lines include the x-nth scan line to the xth scan line sequentially arranged in the second direction, x is a positive integer greater than or equal to 2, n is a positive integer and less than x, the xth scan line an on time of a gate drive signal of the line overlaps in timing with an off time of a gate drive signal of the x-nth line; The patch cords include an x-nth patch cord and an xth patch cord, which are electrically connected to the x-nth scan line and the xth scan line, respectively; The pixel rows include a k-1 th pixel row, a k th pixel row, and a k+1 th pixel row sequentially arranged in the first direction, where k is a positive integer greater than or equal to 2; The data lines include a k-1 th data line, a k th data line, and a k+1 th data line, which are electrically connected to the k-1 th pixel row, the k th pixel row, and the k th pixel row, respectively. k+1 pixel rows; In the top view of the pixel array substrate, the x-n th connecting line is disposed between the k-1 th data line and the k th data line, and the x th connecting line is disposed between the k th data line and the k th data line Between the k+1th data line. The pixel array substrate of claim 11, wherein the scan lines include the x-n th scan line to the x+n th scan line sequentially arranged in the second direction, and the x th scan line is An end time of the gate pulse signal and a start time of a gate pulse signal of the x+nth scan line overlap in time sequence; the switch wires further include an x+nth switch wire electrically connected to the x+nth scan line; the pixel rows further include a k+2th pixel row, the k-1th pixel row, the kth pixel row, the k+1th pixel row and the The k+2 th pixel row is sequentially arranged in the first direction; the data lines further include a k+2 th data line, which is electrically connected to the k+2 th pixel row; on the pixel array substrate In the top view of , the x+n th transition line is disposed between the k+1 th data line and the k+2 th data line. The pixel array substrate of claim 11, wherein the pixel rows further include a k+2 th pixel row, the k-1 th pixel row, the k th pixel row, and the k+1 th pixel row The pixel row and the k+2 th pixel row are arranged in sequence in the first direction; the data lines further include a k+2 th data line, which is electrically connected to the k+2 th pixel row; the picture The pixel array substrate further includes: a first common line, wherein in a top view of the pixel array substrate, the first common line is disposed between the k+1 th data line and the k+2 th data line. The pixel array substrate of claim 11, wherein the pixel rows further include a k+2 th pixel row, the k-1 th pixel row, the k th pixel row, and the k+1 th pixel row The pixel row and the k+2 th pixel row are sequentially arranged in the first direction; the data lines further include a k+2 th data line electrically connected to the k+2 th pixel row; the The scan line includes the m th scan line; the patch cables further include an m th patch cable, which is electrically connected to the m th scan line; m is a positive integer greater than 2, and |x-m| is not equal to n; In a plan view of the pixel array substrate, the m th transition line is disposed between the k+1 th data line and the k+2 th data line. The pixel array substrate of claim 11, wherein the scan lines include the y-nth scan line to the yth scan line sequentially arranged in the second direction, and y is a positive integer greater than or equal to 2, n is a positive integer and less than y, a start time of a gate pulse signal of the y-th scan line and an end time of a gate pulse signal of the y-n-th scan line overlap in timing; the switching The lines include a y-nth transfer line and a y-th transfer line, which are respectively electrically connected to the y-nth scan line and the y-th scan line; the pixel rows include sequentially arranged in the first direction a q-1th pixel row, a qth pixel row and a q+1th pixel row, where q is a positive integer greater than or equal to 2; the data lines include a q-1th data line, a first A q data line and a q+1 th data line are respectively electrically connected to the q-1 th pixel row, the q th pixel row and the q+1 th pixel row; the top view of the pixel array substrate wherein, the yth patch cord is disposed between the q-1th data line and the qth data line, and the y-nth patch cord is disposed between the qth data line and the q+1th data line. The pixel array substrate of claim 15, wherein the pixel rows further comprise a q+2th pixel row, the q-1th pixel row, the qth pixel row, and the q+1th pixel row The pixel row and the q+2th pixel row are arranged in sequence in the first direction; the data lines further include a q+2th data line, which is electrically connected to the q+2th pixel row; the picture The pixel array substrate further includes: a second common line, wherein in the top view of the pixel array substrate, the second common line is disposed between the q+1th data line and the q+2th data line. The pixel array substrate of claim 15, wherein the pixel rows further comprise a q+2th pixel row, the q-1th pixel row, the qth pixel row, and the q+1th pixel row The pixel row and the q+2th pixel row are sequentially arranged in the first direction; the data lines further include a q+2th data line electrically connected to the q+2th pixel row; the The scan line includes the p-th scan line; the transition lines further include a p-th transition line, which is electrically connected to the p-th scan line; p is a positive integer greater than 2, and |y-p| is not equal to n; In a plan view of the pixel array substrate, the p th transition line is disposed between the q+1 th data line and the q+2 th data line. The pixel array substrate of claim 11, wherein n=4. The pixel array substrate of claim 11, wherein n=8. The pixel array substrate of claim 11, wherein one of the scan lines belongs to a first conductive layer, and one of the transition lines belongs to a second conductive layer; the pixel array substrate further comprises a an insulating layer, disposed between the first conductive layer and the second conductive layer, and having a contact window; the one of the scan lines is electrically connected to the patch cords through the contact window of the insulating layer the person.

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