TWI716676B - Display panel - Google Patents

Abstract

A display panel including a first substrate, a first data line, a second data line, a third data line, a fourth data line, first sub-pixels, second sub-pixels, third sub-pixels, fourth sub-pixels, a first color filter pattern, a second color filter pattern, a third color filter pattern and a fourth color filter pattern is provided. The first color filter pattern, the second color filter pattern, the third color filter pattern and the fourth color filter pattern respectively overlap the first sub-pixels, the second sub-pixels, the third sub-pixels and the fourth sub-pixels. The first color filter pattern and the fourth color filter pattern has a first color, the second color filter pattern has a second color, and the third color filter pattern has a third color. The first data line is located between the first color filter pattern and the second color filter pattern adjacent to each other. The second data line is located between the second color filter pattern and the third color filter pattern adjacent to each other. Third data line is located between the third color filter pattern and the fourth color filter pattern adjacent to each other.

Description

Display panel

The invention relates to an electronic device, and more particularly to a display panel.

In order to provide users with a good visual experience, the resolution of the display panel needs to be continuously improved, that is, the number of pixels per unit area is increased. Generally speaking, each pixel includes three sub-pixels. As the resolution increases, the distance between multiple sub-pixels becomes shorter, and the distance between the pixel electrode and the adjacent data line also becomes shorter. When the distance between the pixel electrode and the adjacent data line becomes shorter, the coupling capacitances formed by the pixel electrode and the data lines on both sides of the pixel electrode become larger. When the effects of multiple coupling capacitors on the voltage signals of the pixel electrodes at different frame times cannot complement each other, serious color cross-talk problems will occur. The following are shown in Figure 1, Figure 2 and Figure 3. Explain it.

FIG. 1 is a schematic top perspective view of a conventional display panel. 1, the display panel 10 includes a plurality of scan lines SL1, SL2 and a plurality of data lines DLR1, DLG, DLB, DLR2 intersecting the scan lines SL1, SL2. The display panel 10 also includes a plurality of sub-pixels SP1', SP2', SP3', and SP4'. A plurality of sub-pixels SP1' are arranged along the extending direction of the data line DLR1, and are electrically connected to the data line DLR1. A plurality of sub-pixels SP2' are arranged along the extending direction of the data line DLG, and are electrically connected to the data line DLG. A plurality of sub-pixels SP3' are arranged along the extending direction of the data line DLB, and are electrically connected to the data line DLB. A plurality of sub-pixels SP4' are arranged along the extending direction of the data line DLR2, and are electrically connected to the data line DLR2. Each sub-pixel SP1', SP2', SP3' or SP4' includes an active element T1, T2, T3, or T4 and sub-pixel electrodes E1, E2, E3, or E3 electrically connected to the active element T1, T2, T3, or T4 E4.

The pixel electrodes E1 of the plurality of sub-pixels SP1' are located between the adjacent data line DLR1 and the data line DLG. The pixel electrodes E2 of the plurality of sub-pixels SP2' are located between the adjacent data line DLG and the data line DLB. The pixel electrodes E3 of the plurality of sub-pixels SP3' are located between the adjacent data line DLB and the data line DLR2. The plurality of pixel electrodes E1 overlap the red filter pattern F1. A plurality of sub-pixels SP1' are used to display red. The plurality of pixel electrodes E2 overlap the green filter pattern F2. A plurality of sub-pixels SP2' are used to display green. The plurality of pixel electrodes E3 overlap the blue filter pattern F3. Multiple sub-pixels SP3' are used to display blue. The plurality of pixel electrodes E4 overlap the red filter pattern F4. Multiple sub-pixels SP4' are used to display red.

2 shows the voltage signal V _SL1 of the scan line _SL1 , the voltage signal V _{SL2 of the} scan line SL2, the voltage signal V _DLR1 of the data line _DLR1 , the voltage signal V _DLG of the data line _DLG , and the voltage signal V of the data line DLB in _FIG . _DLB , the voltage signal V _{DLR2 of the} data line DLR2, the voltage signal V _E1 of the sub-pixel electrode _E1 , the voltage signal V _E2 of the sub-pixel electrode _E2, and the voltage signal V _{E3 of the} sub-pixel electrode _E3 . In Figure 2, the voltage signals V _DLR1 , V _DLG , V _DLB , and V _DLR2 represent 128 gray scale voltage, m gray scale voltage, 128 gray scale voltage, and 128 gray scale voltage, respectively, and all sub-pictures to be used to display red SP1' and SP4' switch to 128 gray scales, all sub-pixels SP2' to be used to display green switch to m gray scales, and all sub-pixels SP3' to display blue to switch to 128 gray scales, where m is 0 or a positive integer, and 0≤m≤255.

FIG. 3 shows the relationship between the root mean square voltage value of the voltage signal V _E1 of the sub-pixel electrode E1 of the conventional display panel 10 and the brightness of all the sub-pixels SP1' used to display red, the sub-pixel electrode The relationship between the rms voltage value of the voltage signal V _{E2 of E2} and the brightness of all the sub-pixels SP2' used to display green, and the rms voltage value of the voltage signal V _E3 of the sub-pixel electrode E3 and the application To display the relationship curve SB' of the brightness of all the sub-pixels SP3' of blue.

1 to 3, within a frame time t1, affected by the coupling capacitance between the sub-pixel electrode E1 and the data line DLR1 and the coupling capacitance between the sub-pixel electrode E1 and the data line DLG, The amplitude of the voltage signal V _E1 of the pixel electrode E1 decreases by ΔV1. In the next frame time t2, the voltage signal of the sub-pixel electrode E1 is affected by the coupling capacitance between the sub-pixel electrode E1 and the data line DLR1 and the coupling capacitance between the sub-pixel electrode E1 and the data line DLG The amplitude of VE1 also decreases by ΔV1. The two reduced amplitudes ΔV1 at the frame time t1 and t2 will make the rms voltage value of the voltage signal V _E1 of the sub-pixel electrode E1 Vr128-ΔVr (marked in Fig. 3) compared with the voltage signal V _DLR1 of the data line DLR1 The root mean square voltage value Vr128 (labeled in Figure 3) is smaller than ΔVr (labeled in Figure 3). ΔVr will be used to display the brightness Lr128-ΔLr (marked in Figure 3) of the sub-pixel SP1' where the red sub-pixel electrode E1 is located. Compared with the correct brightness Lr128 (marked in Figure 3), the brightness Lr128 is greatly reduced by ΔLr, where the brightness Lr128 corresponds to the data line DLR1 The root mean square voltage value of the voltage signal V _DLR1 is Vr128.

In a frame time t1, the voltage signal V of the sub-pixel electrode E2 is affected by the coupling capacitance between the sub-pixel electrode E2 and the data line DLG and the coupling capacitance between the sub-pixel electrode E2 and the data line DLB The amplitude of _E2 increases by ΔV ₂ . In the next frame time t2, the voltage of the second sub-pixel electrode E2 is affected by the coupling capacitance between the sub-pixel electrode E2 and the data line DLG and the coupling capacitance between the pixel electrode E2 and the data line DLB The amplitude of the signal V _E2 also increases by ΔV ₂ . The two amplitudes of ΔV ₂ increased at the frame time t1 and t2 will make the voltage signal V _E2 of the sub-pixel electrode E2 have a root mean square voltage value Vgm+ΔVg (marked in Figure 3) than the voltage signal V _DLG of the data line DLG The root mean square voltage value Vgm (marked in Figure 3) is greater than ΔVg (marked in Figure 3). ΔVg will be used to display the brightness Lgm+ΔLg (marked in Figure 3) of the sub-pixel SP2' where the green sub-pixel electrode E2 is located, which is slightly increased by ΔLg compared to the correct brightness Lgm (marked in Figure 3), where the brightness Lgm corresponds to the data line The voltage signal V _{DLG is} the root mean square voltage value Vgm of _DLG .

In the frame time t1 and frame time t2, the amplitude of the voltage signal V _DLB of the data line DLB is the same as the amplitude of the voltage signal V _DLR2 of the data line DLR2, and the amplitude of the voltage signal V _E3 of the third sub-pixel electrode E3 is approximately The upper is not excessively affected by the coupling capacitance between the sub-pixel electrode E3 and the data line DLB and the coupling capacitance between the sub-pixel electrode E3 and the data line DLR2. The brightness of the sub-pixel SP3' where the blue sub-pixel electrode E3 is located has the correct brightness (that is, the brightness corresponding to 128 gray scales).

In summary, when all the sub-pixels SP1' and SP4' used to display red of the display panel 10 are switched to 128 gray scales, all the sub-pixels SP2' used to display green are switched to m gray scales, displaying blue When all the sub-pixels SP3' of the color are switched to 128 gray scales, in fact, the brightness of all the sub-pixels SP3' of the display panel 10 used to display blue is roughly the correct brightness, but all the sub-pixels used to display red The brightness of the pixels SP1' and SP4' is much lower than the correct brightness, and the brightness of all the sub-pixels SP2' used to display green is only slightly higher than the correct brightness and cannot compensate for the sub-pixel SP1' used to display red. The lost brightness, in turn, causes serious color crosstalk problems.

The invention provides a display panel with good performance.

The present invention provides a display panel including a first substrate, a first scan line, a second scan line, a first data line, a second data line, a third data line, a fourth data line, a plurality of first sub-pixels, multiple A second sub-pixel, a plurality of third sub-pixels, a plurality of fourth sub-pixels, a first filter pattern, a second filter pattern, a third filter pattern, and a fourth filter pattern. The first substrate has a plurality of sub-pixel regions. The first scan line and the second scan line are arranged on the first substrate. The first data line, the second data line, the third data line, and the fourth data line are sequentially arranged on the first substrate. The first data line, the second data line, the third data line, and the fourth data line are A scan line and a second scan line are intersected. A plurality of first sub-pixels are arranged along the extending direction of the first data line and are electrically connected to the first data line, wherein each first sub-pixel includes a first active element and an electrical connection to the first active element The first sub-pixel electrode. A plurality of second sub-pixels are arranged along the extension direction of the second data line and are electrically connected to the second data line, wherein each second sub-pixel includes a second active element and a second active element electrically connected to the second active element The second sub-pixel electrode. The plurality of third sub-pixels are arranged along the extension direction of the third data line and are electrically connected to the third data line, wherein each third sub-pixel includes a third active element and a third active element electrically connected to the third active element The third sub-pixel electrode. A plurality of fourth sub-pixels are arranged along the extension direction of the fourth data line, and are electrically connected to the fourth data line, wherein each fourth sub-pixel includes a fourth active element and a fourth active element electrically connected The fourth sub-pixel electrode. The first filter pattern has a first color, and the first filter pattern is overlapped with the first sub-pixel electrode. The second filter pattern has a second color, and the second filter pattern is overlapped with the second sub-pixel electrode. The third filter pattern has a third color, and the third filter pattern is overlapped with the third sub-pixel electrode. The fourth filter pattern has a first color, and the fourth filter pattern overlaps with the fourth sub-pixel electrode. In particular, the first data line is located between the adjacent first and second filter patterns, the second data line is located between the adjacent second and third filter patterns, and the third The data line is located between the adjacent third filter pattern and the fourth filter pattern.

In an embodiment of the present invention, the above-mentioned first active element and the first sub-pixel electrode are overlapped with the first filter pattern. The second active element and the second sub-pixel electrode are located between the first data line and the second data line, and overlap the second filter pattern. The third active element and the third sub-pixel electrode are located between the second data line and the third data line, and overlap the third filter pattern. The fourth active element and the fourth sub-pixel electrode are located between the third data line and the fourth data line, and overlap the fourth filter pattern.

In an embodiment of the present invention, the above-mentioned display panel further includes a light-shielding layer, wherein the first data line is located between the adjacent first active device and the second active device, and the second active device is located adjacent to the first data line Between the second data line and the second data line, the third active element is located between the adjacent second data line and the third data line, the fourth active element is located between the adjacent third data line and the fourth data line, and the light shielding layer is The first active element, the second active element, the third active element and the fourth active element are overlapped and arranged.

In an embodiment of the present invention, the aforementioned first scan line and second scan line extend in a first direction, and the first data line, the second data line, the third data line, and the fourth data line extend in the second direction It extends upward, and the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are respectively arranged along the second direction.

In an embodiment of the present invention, the aforementioned first color, second color, and third color are red, green, and blue, respectively.

In an embodiment of the present invention, the aforementioned first color, second color, and third color are blue, red, and green, respectively.

In an embodiment of the present invention, in the vertical projection direction, the above-mentioned first data line is located between the boundary of the adjacent first filter pattern and the boundary of the second filter pattern, and the second data line is located adjacent to Between the boundary of the second filter pattern and the boundary of the third filter pattern, and the third data line is located between the boundary of the adjacent third filter pattern and the boundary of the fourth filter pattern.

In an embodiment of the present invention, the aforementioned display panel further includes a display medium, wherein the display medium includes a liquid crystal layer.

In an embodiment of the present invention, the above-mentioned display panel further includes a second substrate, wherein the display medium is located between the first substrate and the second substrate, and the first filter pattern, the second filter pattern, and the third filter The pattern and the fourth filter pattern are disposed on the second substrate.

In an embodiment of the present invention, the above-mentioned first filter pattern, second filter pattern, third filter pattern, and fourth filter pattern are disposed on the first substrate.

Based on the above, in the display panel of an embodiment of the present invention, the first data line is located between the adjacent first filter pattern and the second filter pattern, and the second data line is located between the adjacent second filter pattern And the third filter pattern, and the third data line is located between the adjacent third filter pattern and the fourth filter pattern, wherein the first filter pattern has a first color, and the second filter pattern has a Two colors, the third filter pattern has a third color, and the fourth filter pattern has a first color. In this way, the serious color crosstalk problem of the display panel can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

4 is a schematic top perspective view of a display panel according to an embodiment of the invention. 5 is a schematic cross-sectional view of the display panel drawn according to the section line A-A' and the section line B-B' of FIG. 4. 4 and 5, the display panel 100 includes a first substrate 110, a second substrate 120 disposed opposite to the first substrate 110, and a display medium 130 located between the first substrate 110 and the second substrate 120. In this embodiment, the display medium 130 is, for example, a liquid crystal layer, but the invention is not limited to this. In this embodiment, the material of the first substrate 110 and the material of the second substrate 120 may be selected from glass, quartz, organic polymer, or other applicable materials.

The display panel 100 further includes a first scan line SL1, a second scan line SL2, a first data line DL1, a second data line DL2, a third data line DL3, a fourth data line DL4, a plurality of first sub-pixels SP1, A plurality of second sub-pixels SP2, a plurality of third sub-pixels SP3, a plurality of fourth sub-pixels SP4, a first filter pattern F1, a second filter pattern F2, a third filter pattern F3, and a fourth Filter pattern F4.

The first scan line SL1 and the second scan line SL2 are disposed on the first substrate 110. The first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 are sequentially disposed on the first substrate 110, wherein the first data line DL1, the second data line DL2, and the third data line The DL3 and the fourth data line DL4 are intersected with the first scan line SL1 and the second scan line SL2. The first substrate 110 has a plurality of sub-pixel regions 112. In this embodiment, each sub-pixel area 112 refers to two adjacent scan lines (for example: the first scan line SL1 and the second scan line SL2) and two adjacent data lines (for example: the first data line DL1). And the area enclosed by the second data line DL2).

The first scan line SL1 and the second scan line SL2 extend in the direction x, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 extend in the direction y, and the direction x is the same as the direction y is interlaced. The first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 are sequentially arranged along the direction x. For example, in this embodiment, the direction x and the direction y may be substantially perpendicular, but the invention is not limited thereto.

In this embodiment, the first scan line SL1 and the second scan line SL2 can be formed in the first conductive layer, and the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 can be formed In the second conductive layer. There is a first insulating layer 140 between the first conductive layer and the second conductive layer to electrically isolate the first conductive layer and the second conductive layer from each other. Based on the consideration of conductivity, the first conductive layer and the second conductive layer generally use metal materials. However, the present invention is not limited to this. According to other embodiments, the first conductive layer and the second conductive layer may also use other conductive materials, such as alloys, nitrides of metallic materials, oxides of metallic materials, and oxynitride of metallic materials. Or a stacked layer of metal materials and other conductive materials.

The plurality of first sub-pixels SP1 are arranged along the extension direction y of the first data line DL1, and are electrically connected to the first data line DL1. Each first sub-pixel SP1 includes a first active device T1 and a first sub-pixel electrode E1 electrically connected to the first active device T1. The plurality of second sub-pixels SP2 are arranged along the extension direction y of the second data line DL2, and are electrically connected to the second data line DL2. Each second sub-pixel SP2 includes a second active device T2 and a second sub-pixel electrode E2 electrically connected to the second active device T2. The plurality of third sub-pixels SP3 are arranged along the extension direction y of the third data line DL3, and are electrically connected to the third data line DL3. Each third sub-pixel SP3 includes a third active element T3 and a third sub-pixel electrode E3 electrically connected to the third active element T3. The plurality of fourth sub-pixels SP4 are arranged along the extension direction y of the fourth data line DL4, and are electrically connected to the fourth data line DL4. Each fourth sub-pixel SP4 includes a fourth active element T4 and a fourth sub-pixel electrode E4 electrically connected to the fourth active element T4. In short, in this embodiment, multiple sub-pixels SP1, SP2, SP3, SP4 located in the same column are electrically connected to the same scan line SL1 or SL2, and multiple sub-pixels SP1, SP2 located in different rows , SP3, SP4 are respectively electrically connected to different data lines DL1, DL2, DL3, DL4, and the display panel 100 is driven in a 1G1D manner.

In this embodiment, the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 are located within the respective sub-pixel regions 112 without exceeding the respective sub-pixels.区112. For example, the data line DL0, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 are sequentially arranged along the direction x; the first active element T1 and the first sub-pixel electrode E1 is located between the data line DL0 and the first data line DL1 and between the first scan line SL1 and the second scan line SL2. The first active element T1 and the first sub-pixel electrode E1 do not cross the data line DL0 and the first data line SL1. Line DL1, first scan line SL1 and/or second scan line SL2; second active device T2 and second sub-pixel electrode E2 are located between first data line DL1 and second data line DL2 and first scan line SL1 Between and the second scan line SL2, the second active element T2 and the second sub-pixel electrode E2 do not cross the first data line DL1, the second data line DL2, the first scan line SL1 and/or the second scan line SL2; The third active device T3 and the third sub-pixel electrode E3 are located between the second data line DL2 and the third data line DL3 and between the first scan line SL1 and the second scan line SL2. The third active device T3 and the third The sub-pixel electrode E3 does not cross the second data line DL2, the third data line DL3, the first scan line SL1 and/or the second scan line SL2; the fourth active element T4 and the fourth sub-pixel electrode E4 are located in the third data line Between the line DL3 and the fourth data line DL4 and between the first scan line SL1 and the second scan line SL2, the fourth active element T4 and the fourth sub-pixel electrode E4 do not cross the third data line DL3 and the fourth data line DL4, the first scan line SL1 and/or the second scan line SL2.

In this embodiment, the first active device T1, the second active device T2, the third active device T3, and the fourth active device T4, for example, each include a thin film transistor T (TFT) to control the first data respectively. The line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 respectively align the first sub-pixel electrode E1, the second sub-pixel electrode E2, and the fourth data line within a specific frame time. The three sub-pixel electrodes E3 and the fourth sub-pixel electrode E4 are input with a predetermined voltage.

In this embodiment, the thin film transistor T includes a gate electrode G, a semiconductor pattern CH, and a source S and a drain D electrically connected to two different regions of the semiconductor pattern CH. The gate G of the thin film transistor T is linearly connected to the corresponding scan. For example, the gate G of the first active element T1, the gate G of the second active element T2, the gate G of the third active element T3 and the gate G of the fourth active element T4 in the same row are the same The scan line (for example: the first scan line SL1) is electrically connected. The source S of the thin film transistor T is electrically connected to the corresponding data line. For example, the source S of the first active device T1 of the first sub-pixels SP1 located in the same row is electrically connected to the first data line DL1, and the first active device T1 of the plurality of second sub-pixels SP2 located in the same row is electrically connected. The source S of the two active elements T2 is electrically connected to the second data line DL2, and the source S of the third active element T3 of the plurality of third sub-pixels SP3 in the same row is electrically connected to the third data line DL3, The source S of the fourth active element T4 of the fourth sub-pixels SP4 in the same row is electrically connected to the fourth data line DL4.

The drain electrode D of the thin film transistor T is electrically connected to the corresponding pixel electrode. For example, the drain D of the first active device T1 is electrically connected to the first sub-pixel electrode E1, the drain D of the second active device T2 is electrically connected to the second sub-pixel electrode E2, and the third The drain D of the active device T3 is electrically connected to the third sub-pixel electrode E3, and the drain D of the fourth active device T4 is electrically connected to the fourth sub-pixel electrode E4.

In this embodiment, the gate electrode G can be formed on the aforementioned first conductive layer, and the source electrode S and the drain electrode D can be formed on the aforementioned second conductive layer, but the invention is not limited thereto. In this embodiment, the display panel 100 may optionally include a flat layer F, which covers the first active element T1, the second active element T2, the third active element T3, and the fourth active element T4. The first sub-picture The element electrode E1, the second sub-pixel electrode E2, the third sub-pixel electrode E3, and the fourth sub-pixel electrode E4 can be selectively disposed on the flat layer F, and pass through a plurality of openings (not shown) in the flat layer F. Shown) is electrically connected to the corresponding drain D. In this embodiment, the first sub-pixel electrode E1, the second sub-pixel electrode E2, the third sub-pixel electrode E3, and the fourth sub-pixel electrode E4 are, for example, formed on a transparent conductive layer, which includes metal oxide, For example: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the present invention does not use this Is limited.

The first filter pattern F1 has a first color. The first filter pattern F1 is overlapped with a plurality of first sub-pixel electrodes E1 located in the same row. In this embodiment, the first filter pattern F1 is substantially elongated in the direction y. The second filter pattern F2 has a second color. The second filter pattern F2 is overlapped with a plurality of second sub-pixel electrodes E2 located in the same row. In this embodiment, the second filter pattern F2 is substantially elongated in the direction y. The third filter pattern F3 has a third color. The third filter pattern F3 is overlapped with a plurality of third sub-pixel electrodes E3 located in the same row. In this embodiment, the third filter pattern F3 is substantially in the shape of a strip extending in the direction y. The fourth filter pattern F4 has the same first color as the first filter pattern F1. The fourth filter pattern F4 is overlapped with a plurality of fourth sub-pixel electrodes E4 located in the same row. In this embodiment, the fourth filter pattern F4 is substantially in the shape of a strip extending in the direction y.

For example, in this embodiment, the first color of the first filter pattern F1, the second color of the second filter pattern F2, the third color of the third filter pattern F3, and the fourth filter pattern F4 The first color can be red, green, blue and red respectively. In other words, in this embodiment, the first sub-pixel SP1 is used to display red, the second sub-pixel SP2 is used to display green, the third sub-pixel SP3 is used to display blue, and the fourth sub-pixel SP4 is used It is displayed in red, but the present invention is not limited to this.

In addition, in this embodiment, the first filter pattern F1, the second filter pattern F2, the third filter pattern F3, and the fourth filter pattern F4 can be selectively disposed on the second substrate 120. However, the present invention is not limited to this. According to other embodiments, the first filter pattern F1, the second filter pattern F2, the third filter pattern F3, and the fourth filter pattern F4 may be disposed on the first substrate 110, as follows It will be illustrated with other illustrations in the subsequent paragraphs.

In this embodiment, the display panel 100 may include a light shielding layer BM. In this embodiment, the light-shielding layer BM is used to shield the first active device T1, the second active device T2, the third active device T3, and the fourth active device T4 to reduce damage caused by external light and/or backlight light. . The light shielding layer BM also shields the gaps between the plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, the plurality of third sub-pixels SP3, and the plurality of fourth sub-pixels SP4 to reduce adjacent sub-pixels. The display light between the pixels interferes with each other. For example, in this embodiment, the light-shielding layer BM may include a plurality of lateral portions BM1 and longitudinal portions BM2 staggered in a mesh shape, and each lateral portion BM1 shields a corresponding scan line (for example: the first scan line SL1 or the second scan line SL1 Scan line SL2) and the gaps between the first sub-pixels SP1, the second sub-pixels SP2, the third sub-pixels SP3, and the fourth sub-pixels SP4 in two adjacent columns, Each longitudinal portion BM2 shields the corresponding data line (for example: the first data line DL1, the second data line DL2, the third data line DL3, or the fourth data line DL4) and a plurality of first sub-pixels in two adjacent rows SP1, a gap between a plurality of second sub-pixels SP2, a plurality of third sub-pixels SP3, and a plurality of fourth sub-pixels SP4. However, the present invention is not limited to this, and in other embodiments, the light shielding layer BM may also have other forms. In addition, in this embodiment, the light shielding layer BM can be selectively disposed on the second substrate 120. However, the present invention is not limited to this. According to other embodiments, the light-shielding layer BM may also be disposed on the first substrate 110, which will be illustrated below in conjunction with other drawings in subsequent paragraphs.

4 and 5, it is worth noting that the first data line DL1 is located between the adjacent first filter pattern F1 and the second filter pattern F2, and the second data line DL2 is located between the adjacent second filter pattern. Between the light pattern F2 and the third filter pattern F3, and the third data line DL3 is located between the adjacent third filter pattern F3 and the fourth filter pattern F4. In other words, in the projection direction z, at least part of the first data line DL1 is located between the boundary F1b of the adjacent first filter pattern F1 and the boundary F2a of the second filter pattern F2, and the second data line DL2 is located The boundary F2b of the adjacent second filter pattern F2 and the boundary F3a of the third filter pattern F3, and the third data line DL3 is located between the boundary F3b of the adjacent third filter pattern F3 and the fourth filter pattern F4 Between boundary F4a. In this way, the serious color crosstalk problem described in the prior art can be improved. The improvement mechanism will be described below in conjunction with FIGS. 4, 6 and 7.

6 shows the voltage signal V _SL1 of the first scan line SL1, the voltage signal V SL2 of the second scan line _SL2 , the voltage signal V _DL0 of the data line DL0, and the first data line DL1 of the display panel 100 according to an embodiment of the present invention the voltage signal V _DL1, a second data line DL2, a voltage signal V _DL2, the third data line DL3 voltage signal V _DL3, the first sub-pixel electrode E1 is a voltage signal V _E1, E2 of the second sub-pixel electrode voltage The signal V _E2 and the voltage signal V _{E3 of the} third sub-pixel electrode _E3 .

7 shows the relationship between the root mean square voltage value of the voltage signal of the first sub-pixel electrode E1 of the display panel 100 and the brightness of all the first sub-pixels SP1 used to display the first color according to an embodiment of the present invention SR, the root mean square voltage value of the voltage signal of the second sub-pixel electrode E2 and the relationship curve SG of the brightness of all the second sub-pixels SP2 used to display the second color, and the voltage signal of the third sub-pixel electrode E3 The relationship curve SB between the root mean square voltage value of and the brightness of all the third sub-pixels SP3 used to display the third color.

4 and 6, in a frame time t1, the voltage signal V _{SL1 of} the first scan line SL1 has a high level, so that the first active element T1 and the second active element T1 arranged along the first scan line SL1 The device T2 and the third active device T3 are turned on. At this time, the voltage signals V _DL1 , V _DL2 , and V _{DL3 of the} first data line DL1, the second data line DL2 and the third data line _DL3 are respectively transmitted along the first scan line SL1 The first sub-pixel electrode E1, the second sub-pixel electrode E2, and the third sub-pixel electrode E3 of the arrangement. In the next frame time t2, the voltage signal V _{SL2 of} the second scan line SL2 has a high level so that the first active device T1, the second active device T2, and the third active device T3 arranged along the second scan line SL2 On, at this time, the voltage signals V _DL1 , V _DL2 , V _{DL3 of the} first data line DL1, the second data line DL2 and the third data line _DL3 are respectively transmitted to the first sub-pixels arranged along the second scan line SL2 The electrode E1, the second sub-pixel electrode E2, and the third sub-pixel electrode E3. Among them, the voltage signals V _DL0 , V _DL1 , V _DL2 , and V _DL3 represent 128 gray scale voltage, 128 gray scale voltage, n gray scale voltage and 128 gray scale voltage, respectively, n is 0 or a positive integer, and 0≦n≦255 .

In short, in this embodiment, in the frame time t1 and t2, it is desired that the first sub-pixel SP1 displaying red in the sub-pixel area 112 has a brightness corresponding to 128 gray scales. The second sub-pixel SP2 displaying green in 112 has a brightness of n gray scales, and it is desired that the third sub-pixel SP3 displaying blue in the pixel area 112 has a brightness corresponding to 128 gray scales.

In addition, in this embodiment, in each frame time t1 or t2, the voltage signals of two adjacent data lines have opposite polarities. For example, the voltage signal V _DL3 opposite polarity data lines DL0 and the first data line DL1 _DL1 polarity of voltage signal V, the polarity of the first data line DL1 _DL1 voltage signal V and the voltage of the second data signal line DL2 The polarity of V _DL2 is opposite, and the polarity of the voltage signal V _DL2 of the second data line DL2 is opposite to the polarity of the voltage signal V _DL3 of the third data line DL3.

4 and 6, in the frame time t1 and frame time t2, the amplitude of the voltage signal V _DL0 of the data line DL0 is substantially the same as the amplitude of the voltage signal V _DL1 of the first data line DL1, and the first The amplitude of the voltage signal V _E1 of the sub-pixel electrode E1 is not excessively affected by the coupling capacitance between the first sub-pixel electrode E1 and the data line DL0 and the difference between the first sub-pixel electrode E1 and the first data line DL1. Due to the influence of the coupling capacitor, the first sub-pixel SP1 has a brightness substantially corresponding to 128 gray scales. In other words, in this embodiment, the first sub-pixel SP1 that displays red has substantially the correct brightness.

4 and 6, in a frame time t1, the coupling capacitance between the second sub-pixel electrode E2 and the first data line DL1 and the second sub-pixel electrode E2 and the second data line DL2 The amplitude of the voltage signal V _E2 of the second sub-pixel electrode E2 increases by ΔV2 due to the influence of the coupling capacitance between the two. In the next frame time t2, affected by the coupling capacitance between the second sub-pixel electrode E2 and the first data line DL1 and the coupling capacitance between the second sub-pixel electrode E2 and the second data line DL2, The amplitude of the voltage signal V _E2 of the second sub-pixel electrode E2 also increases by ΔV2.

Please refer to FIG. 4, FIG. 6 and FIG. 7. The two amplitudes ΔV2 increased at the frame time t1 and t2 will make the voltage signal V _E2 of the second sub-pixel electrode E2 have a higher root mean square voltage value Vgn+ΔVg than the second data The root mean square voltage value Vgn of the voltage signal V _DL2 of the line DL2 is larger by ΔVg. ΔVg causes the second sub-pixel SP2 to have a brightness Lgn+ΔLg higher than the correct brightness Lgn, where the brightness Lgn refers to the brightness corresponding to the root mean square voltage value Vgn of the voltage signal V _DL2 of the second data line DL2. In other words, in this embodiment, the brightness of the second sub-pixel SP2 for displaying green is higher than the correct brightness by ΔLg. As shown in FIG. 7, the slope of the curve SG at the root mean square voltage value Vgn corresponding to the lower n gray scale is small, that is, ΔLg is very small, and ΔLg has little effect on the color crosstalk of the display panel 100.

4 and 6, in a frame time t1, the coupling capacitance between the third sub-pixel electrode E3 and the second data line DL2 and the third sub-pixel electrode E3 and the third data line DL3 The amplitude of the voltage signal V _E3 of the third sub-pixel electrode E3 is reduced by ΔV3 due to the influence of the coupling capacitance effect between them. In the next frame time t2, affected by the coupling capacitance between the third sub-pixel electrode E3 and the second data line DL2 and the coupling capacitance between the third sub-pixel electrode E3 and the third data line DL3, The amplitude of the voltage signal V _E3 of the third sub-pixel electrode E3 also decreases by ΔV3.

Please refer to Figure 4, Figure 6 and Figure 7, the two amplitudes ΔV3 reduced at the frame time t1 and t2 will make the voltage signal V _E3 of the third sub-pixel electrode E3 have a higher root mean square voltage value Vb128-ΔVb than the third data The root mean square voltage value Vb128 of the voltage signal V _DL3 on the line DL3 is smaller than ΔVb. ΔVb makes the third sub-pixel SP3 have a brightness Lb128-ΔLb that is less than the correct brightness Lb128, where the brightness Lb128 refers to the brightness of the root mean square voltage value Vb128 of the voltage signal V _DL3 corresponding to the third data line DL3. In other words, in this embodiment, the brightness of the third sub-pixel SP3 for displaying blue is lower by ΔLb than the correct brightness.

The root mean square voltage value of the voltage signal of the first sub-pixel electrode E1 of the display panel 100 of FIG. 7 and the brightness of all the first sub-pixels SP1 used to display the first color (for example, red) are related curves SR, The relationship curve SG between the root mean square voltage value of the voltage signal of the second sub-pixel electrode E2 and the brightness of all the second sub-pixels SP2 used to display the second color (for example: green) and the third sub-pixel electrode E3 The relationship curve SB between the root mean square voltage value of the voltage signal and the brightness of all the third sub-pixels SP3 used to display the third color (for example: blue) is substantially the same as that of the display panel described in the prior art of FIG. 3 10 The root mean square voltage value of the voltage signal of the first sub-pixel electrode E1 and the brightness of all the sub-pixels SP1' used to display red, the root mean square voltage signal of the second sub-pixel electrode E2 The relationship between the voltage value and the brightness of all sub-pixels SP2' used to display green and the root mean square voltage value of the voltage signal of the third sub-pixel electrode E3 and the relationship between all sub-pixels SP3' used to display blue The relationship curve of brightness is the same.

3 and 7, in the display panel 10 described in the prior art and the display panel 100 of this embodiment, the coupling capacitance between the pixel electrode and the data lines on both sides thereof will cause the same magnitude of ΔVb ( Labeled in Figure 7) and ΔVr (labeled in Figure 3). 3 and 7, it can be seen that the ΔVr caused by the coupling capacitor of the conventional display panel 10 acts on the relationship curve SR' with a steeper slope to produce a larger brightness difference ΔLr, and the display panel 100 of this embodiment uses The ΔVb caused by the above-mentioned layout coupling capacitor acts on the relationship curve SB with a slower slope to produce a smaller brightness difference ΔLb. Thereby, the display panel 100 of this embodiment can improve the color crosstalk problem.

FIG. 8 is a schematic top perspective view of a display panel according to another embodiment of the invention. 9 is a schematic cross-sectional view of the display panel drawn according to the section line C-C' and the section line D-D' of FIG. 8. 8 and 9, the display panel 100A of this embodiment is similar to the aforementioned display panel 100. The difference between the two is that the fourth data line DL4, the third data line DL3, and the fourth data line DL3 of the display panel 100A of this embodiment The second data line DL2 and the first data line DL1 are sequentially arranged along the direction x, and the first color of the first filter pattern F1, the second color of the second filter color F2, and the third color of the third filter pattern F3 The colors and the first colors of the fourth filter pattern F4 are blue, red, green, and blue, respectively.

FIG. 10 is a schematic top perspective view of a display panel according to still another embodiment of the invention. FIG. 11 is a schematic cross-sectional view of the display panel drawn according to the sectional line E-E' and the sectional line F-F' of FIG. 10. 10 and 11, the display panel 100B of this embodiment is similar to the aforementioned display panel 100. One difference between the display panel 100B and the display panel 100 is that the first filter pattern F1 of the display panel 100B of this embodiment The second filter pattern F2, the third filter pattern F3, and the fourth filter pattern F4 are disposed on the first substrate 110 to form a color filter on array (COA) structure. The first filter pattern F1 and the second filter pattern F2 partially overlap, and a stacked structure of the first filter pattern F1 and the second filter pattern F2 is formed on the first data line DL1. The second filter pattern F2 and the third filter pattern F3 partially overlap, and a stacked structure of the second filter pattern F2 and the third filter pattern F3 is formed on the second data line DL2. The third filter pattern F3 and the fourth filter pattern F4 partially overlap, and a stacked structure of the third filter pattern F3 and the fourth filter pattern F4 is formed on the third data line DL3. The multiple stacked structures can be used to replace the function of the longitudinal portion BM2 of the light shielding layer BM in FIG. 4, and the light shielding layer BM of the display panel 100B of this embodiment can omit the longitudinal portion BM2. In addition, another difference between the display panel 100B and the display panel 100 is that the light shielding layer BM1 (BM) of the display panel 100B is disposed on the first substrate 110 to form a black matrix on array (BOA) structure. In addition, in this embodiment, the display panel 100B may also optionally include a second insulating layer 150, wherein the second insulating layer 150 covers the second conductive layer (or in other words, the first data line DL1, the second data line DL2, The third data line DL3, the fourth data line DL4, the source S and the drain D) to separate the first filter pattern F1, the second filter pattern F2, the third filter pattern F3, and the fourth filter pattern F4 and the second conductive layer.

In summary, in the display panel of an embodiment of the present invention, the first data line is located between the adjacent first filter pattern and the second filter pattern, and the second data line is located between the adjacent second filter pattern. Between the light pattern and the third filter pattern, and the third data line is located between the adjacent third filter pattern and the fourth filter pattern, wherein the first filter pattern has a first color, and the second filter pattern Having a second color, the third filter pattern has a third color, and the fourth filter pattern has a first color. This can improve the serious color crosstalk problem of the display panel

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10, 100, 100A, 100B‧‧‧Display panel 110‧‧‧First substrate 120‧‧‧Second substrate 112‧‧‧Sub-pixel area 130‧‧‧Display medium 140‧‧‧First insulating layer 150‧ ‧‧Second insulation layer A-A', B-B', C-C', D-D', E-E', F-F'‧‧‧Section BM‧‧‧Light-shielding layer BM1‧‧‧ Horizontal part BM2‧‧‧Vertical part CH‧‧‧Semiconductor pattern D‧‧‧Drain DL0, DLR1, DLG, DLB, DLR2‧‧‧Data line DL1‧‧‧First data line DL2‧‧‧Second data line DL3‧‧‧The third data line DL4‧‧‧The fourth data line E1‧‧‧The first sub-pixel electrode E2‧‧‧The second sub-pixel electrode E3‧‧‧The third sub-pixel electrode E4‧‧‧ The fourth sub-pixel electrode F‧‧‧flat layer F1‧‧‧first filter pattern F2‧‧‧second filter pattern F3‧‧‧third filter pattern F4‧‧‧fourth filter pattern F1b, F2a, F2b, F3a, F3b, F4a‧‧‧Border G‧‧‧Gate S‧‧‧Source SL1‧‧‧First scan line SL2‧‧‧Second scan line SP1', SP2', SP3'‧ ‧‧Subpixel SP1‧‧‧First subpixel SP2‧‧‧Second subpixel SP3‧‧‧third subpixel SP4‧‧‧fourth subpixel SR, SG, SB, SR', SG', SB'‧‧‧Relationship curve T‧‧‧Thin film transistor T1‧‧‧First active element T2‧‧‧Second active element T3‧‧‧Third active element T4‧‧‧Fourth active element t1 ,T2‧‧‧Frame time V _DLR1 , V _DLR2 , V _DLG , V _DLB , V _DL1 , V _DL2 , V _DL3 , V _DL0 , V _E1 , V _E2 , V _E3 , V _SL1 , V _SL2 ‧‧‧Voltage Signal ΔV1, ΔV2, ΔV3‧‧‧Amplitude Vr128, Vgm, Vgn, Vb128, ΔVr, ΔVg, ΔVb‧‧‧Root mean square voltage value Lr128, Lgm, Lgn, Lb128‧‧‧Luminance ΔLr, ΔLg, ΔLb‧‧‧ Brightness difference x, y, z‧‧‧direction

FIG. 1 is a schematic top perspective view of a conventional display panel. 2 shows the voltage signal V _SL1 of the scan line _SL1 , the voltage signal V _{SL2 of the} scan line SL2, the voltage signal V _DLR1 of the data line _DLR1 , the voltage signal V _DLG of the data line _DLG , and the voltage signal V of the data line DLB in _FIG . _DLB , the voltage signal V _{DLR2 of the} data line DLR2, the voltage signal V _E1 of the sub-pixel electrode _E1 , the voltage signal V _E2 of the sub-pixel electrode _E2, and the voltage signal V _{E3 of the} sub-pixel electrode _E3 . FIG. 3 shows the relationship between the root mean square voltage value of the voltage signal V _E1 of the sub-pixel electrode E1 of the conventional display panel 10 and the brightness of all the sub-pixels SP1' used to display red, the sub-pixel electrode The relationship between the rms voltage value of the voltage signal V _{E2 of E2} and the brightness of all the sub-pixels SP2' used to display green, and the rms voltage value of the voltage signal V _E3 of the sub-pixel electrode E3 and the application To display the relationship curve SB' of the brightness of all the sub-pixels SP3' of blue. 4 is a schematic top perspective view of a display panel according to an embodiment of the invention. 5 is a schematic cross-sectional view of the display panel drawn according to the section line AA′ and the section line B-B′ of FIG. 4. 6 shows the voltage signal V _SL1 of the first scan line SL1, the voltage signal V SL2 of the second scan line _SL2 , the voltage signal V _DL0 of the data line DL0, and the first data line DL1 of the display panel 100 according to an embodiment of the present invention the voltage signal V _DL1, a second data line DL2, a voltage signal V _DL2, the third data line DL3 voltage signal V _DL3, the first sub-pixel electrode E1 is a voltage signal V _E1, E2 of the second sub-pixel electrode voltage The signal V _E2 and the voltage signal V _{E3 of the} third sub-pixel electrode _E3 . 7 shows the relationship between the root mean square voltage value of the voltage signal of the first sub-pixel electrode E1 of the display panel 100 and the brightness of all the first sub-pixels SP1 used to display the first color according to an embodiment of the present invention SR, the root mean square voltage value of the voltage signal of the second sub-pixel electrode E2 and the relationship curve SG of the brightness of all the second sub-pixels SP2 used to display the second color, and the voltage signal of the third sub-pixel electrode E3 The relationship curve SB between the root mean square voltage value of and the brightness of all the third sub-pixels SP3 used to display the third color. FIG. 8 is a schematic top perspective view of a display panel according to another embodiment of the invention. FIG. 9 is a schematic cross-sectional view of the display panel drawn according to the section line CC′ and the section line D-D′ of FIG. 8. FIG. 10 is a schematic top perspective view of a display panel according to still another embodiment of the invention. 11 is a schematic cross-sectional view of the display panel drawn according to the cross-sectional line E-E' and the cross-sectional line F-F' of FIG.

100‧‧‧Display Panel

112‧‧‧Sub-pixel area

A-A’, B-B’‧‧‧ Section

BM‧‧‧Shading layer

BM1‧‧‧Horizontal section

BM2‧‧‧Longitudinal section

DL0‧‧‧Data line

DL1‧‧‧First data line

DL2‧‧‧Second data line

DL3‧‧‧Third data line

DL4‧‧‧Fourth data line

E1‧‧‧The first sub-pixel electrode

E2‧‧‧Second sub-pixel electrode

E3‧‧‧The third sub-pixel electrode

E4‧‧‧Fourth sub-pixel electrode

F1‧‧‧First filter pattern

F2‧‧‧Second filter pattern

F3‧‧‧Third filter pattern

F4‧‧‧Fourth filter pattern

SL1‧‧‧First scan line

SL2‧‧‧Second scan line

SP1‧‧‧First sub-pixel

SP2‧‧‧Second sub-pixel

SP3‧‧‧The third sub-pixel

SP4‧‧‧Fourth sub-pixel

T1‧‧‧The first active component

T2‧‧‧Second active component

T3‧‧‧Third active component

T4‧‧‧Fourth active component

x, y, z‧‧‧direction

Claims (7)

A display panel includes: a first substrate having a plurality of sub-pixel regions; a first scan line and a second scan line, which are arranged on the first substrate; a first data line, a second data line, A third data line and a fourth data line are sequentially arranged on the first substrate, wherein the first data line, the second data line, the third data line, the fourth data line and the first The scan line and the second scan line are arranged crosswise; a plurality of first sub-pixels are arranged along an extension direction of the first data line, and are electrically connected to the first data line, wherein each first sub-pixel It includes a first active element and a first sub-pixel electrode electrically connected to the first active element; a plurality of second sub-pixels are arranged along an extension direction of the second data line and are electrically connected to In the second data line, each second sub-pixel includes a second active device and a second sub-pixel electrode electrically connected to the second active device; a plurality of third sub-pixels are arranged along the first The three data lines are arranged in an extension direction and are electrically connected to the third data line, wherein each third sub-pixel includes a third active element and a third sub-picture electrically connected to the third active element Pixel electrode; a plurality of fourth sub-pixels, arranged along an extension direction of the fourth data line, and electrically connected to the fourth data line, wherein each fourth sub-pixel includes a fourth active element and and A fourth sub-pixel electrode electrically connected to the fourth active element; a first filter pattern having a first color, wherein the first filter pattern is overlapped with the first sub-pixel electrodes; A second filter pattern has a second color, wherein the second filter pattern overlaps with the second sub-pixel electrodes; a third filter pattern has a third color, wherein the third filter pattern The light pattern is overlapped with the third sub-pixel electrodes; and a fourth filter pattern has the first color, wherein the fourth filter pattern is overlapped with the fourth sub-pixel electrodes; wherein the first A data line is located between the adjacent first filter pattern and the second filter pattern, the second data line is located between the adjacent second filter pattern and the third filter pattern, and the The third data line is located between the adjacent third filter pattern and the fourth filter pattern; and wherein the first color is red, the second color is green, and the third color is blue; the The first active devices and the first sub-pixel electrodes are arranged to overlap the first filter pattern; the second active devices and the second sub-pixel electrodes are located between the first data line and the second data Between the lines and overlap the second filter pattern; the third active elements and the third sub-pixel electrodes are located between the second data line and the third data line, and are connected to the third The filter patterns are overlapped; and the fourth active elements and the fourth sub-pixel electrodes are located between the third data line and the fourth data line, and overlap the fourth filter pattern. The display panel described in item 1 of the scope of patent application further includes: A light-shielding layer, wherein the first data line is located between the adjacent first active devices and the second active devices, and the second active devices are located adjacent to the first data line and the second data line In between, the third active devices are located between the adjacent second data line and the third data line, and the fourth active devices are located between the adjacent third data line and the fourth data line, and The light shielding layer is overlapped with the first active devices, the second active devices, the third active devices, and the fourth active devices. The display panel according to claim 1, wherein the first scan line and the second scan line extend in a first direction, the first data line, the second data line, and the third data line And the fourth data line extend in a second direction, and the first sub-pixels, the second sub-pixels, the third sub-pixels, and the fourth sub-pixels are respectively along the first Arranged in two directions. The display panel according to claim 1, wherein in a vertical projection direction, the first data line is located between the border of the adjacent first filter pattern and the border of the second filter pattern, The second data line is located between the boundary of the adjacent second filter pattern and the boundary of the third filter pattern, and the third data line is located between the boundary of the adjacent third filter pattern and the boundary of the third filter pattern. Between the borders of the four filter patterns. The display panel described in item 1 of the scope of patent application further includes: a display medium, wherein the display medium includes a liquid crystal layer. The display panel described in item 5 of the scope of patent application further includes: A second substrate, wherein the display medium is located between the first substrate and the second substrate, and the first filter pattern, the second filter pattern, the third filter pattern, and the fourth filter pattern are arranged On the second substrate. The display panel according to claim 1, wherein the first filter pattern, the second filter pattern, the third filter pattern, and the fourth filter pattern are disposed on the first substrate.

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