TW202207443A - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes pixel structures, data lines, gate lines and first common electrodes. The data lines are arranged along a first direction and electrically connected to the pixel structures. The gate lines are arranged along a second direction and electrically connected to the pixel structures. Each of the first common electrodes includes line segments arranged along the first direction, and two of the line segments adjacent to each other are structurally separated to define a gap. In a top view of the pixel array substrate, one of the data lines crosses over the gap.

Description

pixel array substrate

The present invention relates to a pixel array substrate.

Generally speaking, when the signal line of the display panel is disconnected, the display panel is repaired to improve the yield. Specifically, the disconnected signal line and the repair line can be welded and/or cut, so as to use the repair line to electrically connect the two parts of the disconnected signal line.

The repairing lines of the display panel can be divided into outer repairing lines arranged in the peripheral area and inner repairing lines arranged in the display area. The length of the external repair line is long, and the load itself is large. When the signal line is repaired by the external repair line, the multiple pixel structures electrically connected to the repaired signal line may easily cause abnormality (for example, bright lines/or dark lines) on the display screen. Therefore, the external repair lines are not suitable for application in large-area and/or high-resolution display panels. Currently, the mainstream repair technology for large-area and/or high-resolution display panels uses internal repair lines. However, the inner repair line is disposed in the display area, the distance between the inner repair line and the signal line is short, and the parasitic capacitance is large, which increases the load of the signal line, thereby reducing the charging efficiency of the pixel structure, which is not conducive to the display quality.

The present invention provides a pixel array substrate with good performance.

The pixel array substrate of the present invention includes a plurality of pixel structures, a plurality of data lines, a plurality of gate lines and a plurality of first common electrodes. Each pixel structure includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The plurality of data lines are arranged along the first direction and are electrically connected to the plurality of thin film transistors of the plurality of pixel structures. The plurality of gate lines are arranged along the second direction and are electrically connected to the plurality of thin film transistors of the plurality of pixel structures, wherein the first direction and the second direction are staggered. Each of the first common electrodes includes a plurality of line segments arranged along the first direction, and adjacent two of the plurality of line segments are structurally separated to define a gap. In the top view of the pixel array substrate, a corresponding data line passes through the gap.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may refer to the existence of other elements between the two elements.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, given the measurement in question and the A specific amount of measurement-related error (ie, the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately" or "substantially" may be used to select a more acceptable range of deviation or standard deviation depending on optical properties, etching properties or other properties, and not one standard deviation may apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present invention, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

FIG. 1 is a schematic top view of a pixel array substrate 10 according to an embodiment of the present invention.

FIG. 2 is a schematic top view of a region R of the pixel array substrate 10 according to an embodiment of the present invention. FIG. 2 corresponds to the region R of FIG. 1 .

FIG. 1 schematically illustrates the substrate 110 , the gate lines GL and the transition lines gl, and other components of the pixel array substrate 10 of FIG. 2 are omitted.

FIG. 3 is an enlarged schematic diagram of a part r of the pixel array substrate 10 according to an embodiment of the present invention. FIG. 3 corresponds to the part r of FIG. 2 .

FIG. 4 is a schematic cross-sectional view of the pixel array substrate 10 according to an embodiment of the present invention. Fig. 4 corresponds to the section line І-І' of Fig. 3 .

Referring to FIGS. 1 , 2 , 3 and 4 , the pixel array substrate 10 includes a base 110 . The substrate 110 is mainly used to carry a plurality of components of the pixel array substrate 10 . For example, in this embodiment, the material of the substrate 110 may be glass. However, the present invention is not limited thereto, and according to other embodiments, the material of the substrate 110 may also be quartz, organic polymer, opaque/reflective material (eg, wafer, ceramic, etc.), or other applicable materials.

Referring to FIGS. 1 , 2 and 3 , the pixel array substrate 10 includes a plurality of data lines DL and a plurality of gate lines GL. A plurality of data lines DL and a plurality of gate lines GL are disposed on the substrate 110 . The plurality of data lines DL are arranged along the first direction x, and the plurality of gate lines GL are arranged along the second direction y, wherein the first direction x and the second direction y are staggered. For example, in this embodiment, the first direction x and the second direction y may be perpendicular, but the invention is not limited to this.

Please refer to FIG. 3 and FIG. 4 , in addition, the data line DL and the gate line GL belong to different layers. For example, in this embodiment, the gate line GL can selectively belong to the first metal layer 120, and the data line DL can selectively belong to the second metal layer 140, but the invention is not limited thereto.

Based on the consideration of conductivity, in this embodiment, the data line DL and the gate line GL are made of metal materials. However, the present invention is not limited to this. According to other embodiments, the data line DL and the gate line GL can also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, and oxynitrides of metal materials. , or a stack of metal materials and other conductive materials.

Referring to FIG. 2 and FIG. 3 , the pixel array substrate 10 includes a plurality of pixel structures SPX disposed on the substrate 110 . Each pixel structure SPX includes a thin film transistor T and a pixel electrode 202 electrically connected to the thin film transistor T. As shown in FIG. The plurality of data lines DL are electrically connected to the plurality of thin film transistors T of the plurality of pixel structures SPX. The plurality of gate lines GL are electrically connected to the plurality of thin film transistors T of the plurality of pixel structures SPX.

Please refer to FIG. 3 and FIG. 4 . Specifically, in this embodiment, each thin film transistor T has a source electrode Ta, a drain electrode Tb, a gate electrode Tc and a semiconductor pattern Td, and the gate insulating layer 130 is sandwiched between the gate electrodes. Between Tc and the semiconductor pattern Td, the source Ta and the drain Tb are respectively electrically connected to two different regions of the semiconductor pattern Td, the source Ta is electrically connected to a corresponding data line DL, and the gate Tc is electrically connected to A corresponding gate line GL. For example, in this embodiment, the gate electrode Tc can selectively belong to the first metal layer 120, and the source electrode Ta and the drain electrode Tb can selectively belong to the second metal layer 140, but the invention is not limited to this .

The drain electrode Tb of each thin film transistor T is electrically connected to a corresponding pixel electrode 202 . For example, in this embodiment, each pixel structure SPX further includes a connection pattern 142 disposed on the gate insulating layer 130 and electrically connected to the drain electrode Tb of the thin film transistor T; the pixel array substrate 10 further includes It may include a first passivation layer 150 disposed on the second metal layer 140, a color filter pattern 160 disposed on the first passivation layer 150, a second passivation layer 170 disposed on the color filter pattern 160, and a second passivation layer 170 disposed on the first passivation layer 150. The flat layer 190 on the second passivation layer 170; the pixel electrode 202 can be disposed on the flat layer 190, and is electrically connected to the connection pattern 142 through the contact window 192 of the flat layer 190, wherein the connection pattern 142 is electrically connected to the pixel electrode 202 and the The drain electrode Tb of the thin film transistor T.

In this embodiment, the pixel electrodes 202 may belong to the second transparent conductive layer 200 . The material of the second transparent conductive layer 200 may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or The above-mentioned at least two stacked layers, but the present invention is not limited to this.

Referring to FIG. 2 , the pixel array substrate 10 further includes a plurality of first common electrodes 122 . Each first common electrode 122 includes a plurality of line segments 122a, 122b arranged along the first direction x; adjacent two of the plurality of line segments 122a, 122b are structurally separated to define a gap 122g; In a plan view, a corresponding data line DL passes through the gap 122g.

In other words, each first common electrode 122 includes a plurality of line segments 122a, 122b that are disconnected from each other; in the top view of the pixel array substrate 10, each data line DL of the pixel array substrate 10 at least passes through at least one first The disconnection of the common electrodes 122 (ie, the gap 122 g ) does not overlap with each of the first common electrodes 122 . Therefore, the parasitic capacitance between the data line DL and the first common electrode 122 is small, so that the load of the data line DL is reduced, thereby improving the charging efficiency of the pixel structure SPX and improving the performance of the pixel array substrate 10 .

In this embodiment, the plurality of line segments 122a, 122b of each first common electrode 122 includes a plurality of first line segments 122a and a plurality of second line segments 122b, and each first line segment 122a is interlaced with at least one data line DL It is arranged that each second line segment 122b intersects with the connection pattern 142 of a corresponding one of the pixel structures SPX and does not overlap with the data line DL.

Under normal circumstances (or in other words, when the first common electrode 122 is not used to repair the pixel array substrate 10 ), the plurality of first line segments 122 a and the plurality of second line segments of each first common electrode 122 are 122b are each electrically connected to a corresponding second common electrode 124; the plurality of first line segments 122a of the first common electrode 122, the plurality of second line segments 122b of the first common electrode 122 and the second common electrode 124 have the same the reference potential; but the present invention is not limited to this.

For example, in this embodiment, each of the first line segments 122a may be interleaved with three data lines DL, and two connection patterns 142 may be respectively provided between the two adjacent first line segments 122a on the left and right sides. The two second line segments 122b-1 and 122b-2 are staggered. However, the present invention is not limited to this, and the number of data lines DL interlaced with the same first line segment 122a and/or the number of second line segments 122b located between two adjacent first line segments 122a can be determined according to actual needs and change.

It is worth mentioning that, in this embodiment, the setting of the second line segment 122b can make the parasitic capacitance between the plurality of pixel structures SPX corresponding to the first line segment 122a and the second line segment 122b respectively and the first common electrode 122 closer. In this way, the plurality of pixel structures SPX corresponding to the first line segment 122 a and the second line segment 122 b respectively can have similar optical performance, so as to improve the overall display quality of the display panel (not shown) having the pixel array substrate 10 .

Referring to FIG. 2 , in this embodiment, the plurality of first line segments 122 a and the plurality of second line segments 122 b - 1 of the plurality of first common electrodes 122 respectively corresponding to the plurality of pixel rows Rspx may be in the first direction x Alternately arranged in the upper direction and the second direction y. In other words, the connection lines of the plurality of pixel structures SPX corresponding to the plurality of first line segments 122a may substantially form the first diamond pattern DM1, and corresponding to the plurality of pixels of the plurality of second line segments 122b-1 respectively The connection lines of the structure SPX may be substantially in the second diamond pattern DM2. Therefore, even if the optical performance (eg, brightness) of the pixel structures SPX corresponding to the plurality of first line segments 122 a and the plurality of second line segments 122 b is slightly different, the pixel array substrate 10 is not easily affected excessively. The overall display quality of the display panel.

For example, in this embodiment, the first common electrode 122 may selectively belong to the first metal layer 120, but the invention is not limited thereto. Based on the consideration of conductivity, in this embodiment, the first common electrode 122 is made of a metal material. However, the present invention is not limited thereto. According to other embodiments, the first common electrode 122 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or Stacked layers of metallic materials and other conductive materials.

Referring to FIG. 2, in this embodiment, the pixel array substrate 10 further includes a plurality of second common electrodes 124; a plurality of pixel structures SPX are arranged into a plurality of pixel rows Rspx, and each pixel row Rspx has a plurality of The pixel structures SPX are arranged along the first direction x; each second common electrode 124 partially overlaps the pixel electrodes 202 of the pixel structures SPX corresponding to a pixel row Rspx. Each of the second common electrodes 124 and the plurality of pixel electrodes 202 are used to form storage capacitors of the plurality of pixel structures SPX. In the top view of the pixel array substrate 10 , each of the first common electrodes 122 may be disposed between a corresponding one of the gate lines GL and a corresponding one of the second common electrodes 124 .

For example, in this embodiment, the second common electrode 124 may selectively belong to the first metal layer 120, but the invention is not limited thereto. Based on the consideration of conductivity, in this embodiment, the second common electrode 124 is made of a metal material. However, the present invention is not limited thereto. According to other embodiments, the second common electrode 124 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or Stacked layers of metallic materials and other conductive materials.

Referring to FIG. 1 and FIG. 2 , in this embodiment, the pixel array substrate 10 further includes a plurality of switching wires gl. A plurality of patch wires gl are disposed on the substrate 110 and are arranged in the first direction x. The plurality of transition lines gl arranged in the first direction x are respectively electrically connected to the plurality of gate lines GL arranged in the second direction y. Referring to FIG. 2, in this embodiment, a plurality of pixel structures SPX are arranged in a plurality of pixel rows Cspx, and the plurality of pixel structures SPX of each pixel row Cspx are arranged along the second direction y; on the pixel array substrate 10 In the top view of , each patch line gl is disposed between two adjacent ones of the plurality of pixel rows Cspx.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 . For example, in the present embodiment, a plurality of gate lines GL may selectively belong to the first metal layer 120 , and the main parts gla of the plurality of transition lines gl may be selected It belongs to the second metal layer 140, a gate insulating layer 130 (drawn in FIG. 4) is disposed between the first metal layer 120 and the second metal layer 140, and the gate insulating layer 130 has a plurality of contact windows 130a (drawn in FIG. 1 ). ), the main parts gla of the plurality of switching wires gl can be electrically connected to the plurality of gate wires GL through the plurality of contact windows 130a of the gate insulating layer 130, respectively, but the invention is not limited to this.

Referring to FIG. 2 , FIG. 3 and FIG. 4 , in this embodiment, the pixel array substrate 10 may optionally include a transparent shielding pattern 182 . The transparent shielding pattern 182 is disposed between at least one film layer to which the patch cord gl belongs and the membrane layer to which the pixel electrode 202 belongs to shield the potential of the pixel electrode 202 from interference by the gate driving signal of the patch cord gl. For example, in this embodiment, the first transparent conductive layer 180 to which the transparent shielding pattern 182 belongs can be disposed on the second metal layer 140 to which the main part gla of the patch wire gl belongs and the second transparent layer 140 to which the pixel electrode 202 belongs. between the conductive layers 200 .

Please refer to FIG. 4 , specifically, in this embodiment, the transparent shielding pattern 182 can be selectively disposed on the second passivation layer 170 and located between the flat layer 190 and the second passivation layer 170 , but the present invention does not This is the limit. According to other embodiments, the transparent shielding pattern 182 may also be disposed at other positions between the transition line gl and the pixel electrode 202 ; or, the arrangement of the transparent shielding pattern 182 may also be omitted.

Referring to FIG. 2, in this embodiment, in the top view of the pixel array substrate 10, the line segment 122a of the first common electrode 122 and the data line DL have a first intersection X1, and the first intersection X1 can overlap the transparent The openings 182a of the shielding pattern 182 are shielded. In other words, the entity of the transparent shielding pattern 182 is separated from the first intersection X1 of the first common electrode 122 and the data line DL and does not overlap with the first intersection X1.

Referring to FIG. 2 , in this embodiment, the pixel array substrate 10 further includes a plurality of third common electrodes 144 arranged along the first direction x; in the top view of the pixel array substrate 10 , each third common electrode 144 Set between two adjacent ones of multiple pixel rows Cspx.

For example, in this embodiment, the third common electrode 144 has a main portion 144m that spans a plurality of gate lines GL, and the main portion 144m of the third common electrode 144 may belong to the second metal layer 140, but the present invention does not This is limited. Based on the consideration of conductivity, in this embodiment, the third common electrode 144 is made of a metal material. However, the present invention is not limited thereto. According to other embodiments, the third common electrode 144 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or Stacked layers of metallic materials and other conductive materials.

In this embodiment, the line segment 122 a of the first common electrode 122 and the third common electrode 144 have a second intersection X2 , and the second intersection X2 overlaps the opening 182 a of the transparent shielding pattern 182 . In other words, the body of the transparent shielding pattern 182 is spaced at the second intersection X2 of the first common electrode 122 and the third common electrode 144 and does not overlap with the second intersection X2.

In the present embodiment, in the top view of the pixel array substrate 10, the line segment 122a of the first common electrode 122 and a transition line gl have a third intersection X3, and the third intersection X3 overlaps the transparent shielding pattern 182 opening 182a. In other words, the entity of the transparent shielding pattern 182 is spaced at the third intersection X3 of the first common electrode 122 and the transition wire g1 and does not overlap with the third intersection X3.

In this embodiment, in the top view of the pixel array substrate 10, the line segment 122a of the first common electrode 122 and the other third common electrode 144 have a fourth intersection X4, and the fourth intersection X4 overlaps the transparent shielding pattern 182 of the opening 182a. In other words, the entity of the transparent shielding pattern 182 is separated from the fourth intersection X4 of the line segment 122a of the first common electrode 122 and the other third common electrode 144 and does not overlap with the fourth intersection X4.

It is worth noting that when the signal line (for example, the data line DL and/or the transition line gl) is disconnected, the first common electrode 122 arranged horizontally and the third common electrode 144 arranged vertically can be used to repair it. Figure 5 is used as an example to illustrate the following.

FIG. 5 is a schematic top view of a pixel array substrate 10' according to an embodiment of the present invention. The pixel array substrate 10 ′ of FIG. 5 is similar to the pixel array substrate 10 of FIG. 2 , so the same or similar components are represented by the same or similar component symbols. The differences between the two are described below. Referring to the above description, it will not be repeated here. In addition, for the sake of clarity, the illustration of the pixel electrode 202 is omitted in FIG. 5 .

The pixel array substrate 10 of FIG. 2 is a normal (or, in other words, unrepaired) pixel array substrate, and the pixel array substrate 10' of FIG. 5 is a repaired pixel array substrate.

Please refer to FIG. 5 , specifically, in this embodiment, a data line DL has a disconnection DLo, and the disconnection DLo divides the data line DL into a first part DL-1 and a second part DL-2, wherein the data The first portion DL-1 of the line DL is located above the disconnection DLo, and the second portion DL-2 of the data line DL is located below the disconnection DLo.

In order to repair the disconnected data line DL, in this embodiment, the first portion DL-1 of the data line DL and the line segment 122a of the first common electrode 122 that intersects with it can be welded, so that the line segment of the first common electrode 122 can be welded. 122a and the first portion DL-1 of the data line DL have a first weld W1 and are electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the first welding portion W1 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.

In this embodiment, the line segment 122a of the first common electrode 122 and a portion 144a of a third common electrode 144 that intersect with the first portion DL-1 of the data line DL can also be welded, so that the line segment of the first common electrode 122 122a and the third common electrode 144 have a second welding point W2 and are electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the second welding portion W2 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, the other part 144b of the third common electrode 144 can also be welded with the line segment 122a of the other first common electrode 122 staggered therewith, so that the line segment 122a of the other first common electrode 122 and the first common electrode 122 can be welded together. The other part 144b of the three common electrodes 144 has a fifth welding part W5 and is electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the fifth welding portion W5 may overlap another opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, the second portion DL-2 of the data line DL can also be welded with the line segment 122a of the other first common electrode 122 that intersects with it, so that the line segment 122a of the other first common electrode 122 and the data The second portion DL-2 of the line DL has a sixth weld W6 and is electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the sixth welding portion W6 may overlap with another opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, a part of the third common electrode 144 having the second welding point W2 and the fifth welding point W5 can also be disconnected from other parts of the third common electrode 144 . Specifically, in this embodiment, the third common electrode 144 may have a first disconnection C1 located above the second welding point W2 and a third disconnection C3 located below the fifth welding point W5. In this embodiment, the opening 182a of the transparent shielding pattern 182 may have a concave portion 182a-1 overlapping the first disconnection C1, but the invention is not limited thereto.

In addition, in this embodiment, the line segment 122a having the first welding point W1 and the second welding point W2 and the adjacent second common electrode 124 can also have a fourth disconnection point C4, so as to have a fifth welding point The point W5 and the other line segment 122a of the sixth welding point W6 and the adjacent second common electrode 124 have a fifth disconnection point C5.

In the above-mentioned first welding point W1, second welding point W2, fifth welding point W6, sixth welding point W6, first breaking point C1, third breaking point C3, fourth breaking point C4 and th After the five disconnection points C5, the data signal S _DL of the first part DL-1 of the data line DL can pass through the first welding point W1 and a line segment of the first common electrode 122 staggered with the first part DL-1 of the data line DL 122a, the second welding point W2, a part of the third common electrode 144 cut out by the first disconnection C1 and the third disconnection C3, the fifth welding point W5, and the second part DL-2 of the data line DL The staggered line segment 122a of the other first common electrode 122 and the sixth welding point W6 are transmitted to the second portion DL-2 of the data line DL, so that the pixel array substrate 10' can operate normally.

Referring to FIG. 5 , in this embodiment, a patch cord gl has a disconnection glo, and the disconnection glo divides the patch cord gl into a first part gl-1 and a second part gl-2, wherein the patch cord gl The first portion of gl, gl-1, is located above the disconnection glo, and the second portion of the patch cord gl, gl-2, is located below the disconnection point glo.

In the present embodiment, the first part gl-1 of the patch cord gl can be welded to the line segment 122a of one of the first common electrodes 122 that intersect with it, so that the one line segment 122a of the first common electrode 122 and the line segment 122a of the patch cord gl can be welded together. The first portion gl-1 has a third weld W3 and is electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the third welding portion W3 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, the line segment 122a of the first common electrode 122 staggered with the first part gl-1 of the patch wire gl and a part 144c of the other third common electrode 144 can also be welded, so that the first common electrode 122 The line segment 122a and the third common electrode 144 have a fourth welding point W4 and are electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the fourth welding portion W4 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, the other part 144d of the other third common electrode 144 and the line segment 122a of the other first common electrode 122 staggered therewith can also be welded, so that the line segment 122a of the other first common electrode 122 The other part 144d and the third common electrode 144 have a seventh welding part W7 and are electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the seventh welding portion W7 may overlap with another opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, the second portion gl-2 of the transition wire gl can also be welded to the line segment 122a of the other first common electrode 122 that intersects with it, so that the line segment 122a of the other first common electrode 122 can be connected to the transition line 122a. The second portion gl-2 of the line gl has an eighth weld W8 and is electrically connected to each other. In this embodiment, in the top view of the pixel array substrate 10', the eighth welding portion W8 may overlap another opening 182a of the transparent shielding pattern 182, but the invention is not limited to this.

In this embodiment, a part of the third common electrode 144 having the fourth welding point W4 and the seventh welding point W7 can also be disconnected from other parts of the third common electrode 144 . Specifically, the third common electrode 144 may have a second disconnection C2 located above the fourth welding point W4 and a sixth disconnection C6 located below the seventh welding point W7. In this embodiment, the opening 182a of the transparent shielding pattern 182 may have a concave portion 182a-2 overlapping the second disconnection C2, but the invention is not limited thereto.

In addition, in this embodiment, the first line segment 122a of the first common electrode 122 having the third welding point W3 and the fourth welding point W4 and the adjacent second common electrode 124 can also have a seventh disconnection At C7, the first line segment 122a of the first common electrode 122 having the seventh welding point W7 and the eighth welding point W8 and the adjacent second common electrode 124 have an eighth disconnection point C8.

In the above-mentioned third welding point W3, fourth welding point W4, seventh welding point W7, eighth welding point W8, second breaking point C2, sixth breaking point C6, seventh breaking point C7 and th After the eight disconnection point C8, the gate drive signal S _{gl of the first part gl-1 of the patch cord gl} can pass through the third welding point W3 and the first common electrode interlaced with the first part gl-1 of the patch cord gl The line segment 122a of 122, the fourth welding point W4, a part of the third common electrode 144 cut off by the second breaking point C2 and the sixth breaking point C6, the seventh welding point W7, and the second part of the transition line g1 The line segment 122a of the other first common electrode 122 and the eighth welding point W8 interlaced by the part gl-2 are transmitted to the second part gl-2 of the patch wire gl, so that the pixel array substrate 10' can operate normally.

10, 10': pixel array substrate 110: substrate 120: first metal layer 122: first common electrode 122a, 122b, 122b-1, 122b-2: line segment 122g: gap 124: second common electrode 130: gate insulation Layer 140: Second metal layer 142: Connection pattern 144: Third common electrode 144a, 144b, 144c, 144d: One point 144m: Main part 150: First passivation layer 160: Color filter pattern 170: Second passivation layer 180 : first transparent conductive layer 182: transparent shield pattern 182a: openings 182a-1, 182a-2: depression 190: flat layer 130a, 192: contact window 200: second transparent conductive layer 202: pixel electrode Cspx: pixel row C1: first disconnection C2: second disconnection C3: third disconnection C4: fourth disconnection C5: fifth disconnection C6: sixth disconnection C7: seventh disconnection C8 : Eighth disconnection DL: Data line DLo: Disconnection DL-1: The first part DL-2: The second part DM1: The first diamond pattern DM2: The second diamond pattern GL: Gate line gl: Turn Wiring gla: main part glo: disconnection gl-1: first part gl-2: second part R: area r: local Rspx: pixel row S _DL : data signal S _gl : gate driving signal SPX: drawing Element structure T: thin film transistor Ta: source Tb: drain Tc: gate Td: semiconductor pattern W1: first weld W2: second weld W3: third weld W4: fourth weld W5: first weld The fifth weld W6: the sixth weld W7: the seventh weld W8: the eighth weld X1: the first intersection X2: the second intersection X3: the third intersection X4: the fourth intersection x: the first direction y: the second direction І-І': section line

FIG. 1 is a schematic top view of a pixel array substrate 10 according to an embodiment of the present invention. FIG. 2 is a schematic top view of a region R of the pixel array substrate 10 according to an embodiment of the present invention. FIG. 3 is an enlarged schematic diagram of a part r of the pixel array substrate 10 according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of the pixel array substrate 10 according to an embodiment of the present invention. FIG. 5 is a schematic top view of a pixel array substrate 10' according to an embodiment of the present invention.

10: Pixel array substrate

120: first metal layer

122: The first common electrode

122a, 122b, 122b-1, 122b-2: line segment

122g: gap

124: The second common electrode

140: Second metal layer

144: The third common electrode

144m: Main Department

180: the first transparent conductive layer

182: Transparent Shield Pattern

182a: Opening

202: Pixel electrode

Cspx: pixel row

DL: data line

DM1: The first diamond pattern

DM2: The second diamond pattern

GL: gate line

g1: transfer cable

R: region

r: local

Rspx: pixel column

SPX: pixel structure

T: thin film transistor

X1: the first stagger

X2: The second stagger

X3: The third stagger

X4: Fourth stagger

x: first direction

y: the second direction

Claims (16)

A pixel array substrate, comprising: a plurality of pixel structures, wherein each pixel structure includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor; a plurality of data lines arranged along a first direction and electrically connected to the plurality of thin film transistors of the pixel structures; a plurality of gate lines arranged along a second direction and electrically connected to the thin film transistors of the pixel structures, wherein the first direction and the second direction are interlaced; and a plurality of first common electrodes, wherein each first common electrode includes a plurality of line segments arranged along the first direction; adjacent two of the line segments are structurally separated to define a gap; on the pixel array substrate In the top view of , a corresponding data line passes through the gap. The pixel array substrate according to claim 1, further comprising: A plurality of second common electrodes, wherein the pixel structures are arranged in a plurality of pixel rows, the plurality of pixel structures of each pixel row are arranged along the first direction, and each second common electrode is associated with a corresponding one of the pixels a plurality of pixel electrodes of the pixel structures of the pixel row partially overlap; In a plan view of the pixel array substrate, each of the first common electrodes is disposed between a corresponding gate line and a corresponding and a second common electrode. The pixel array substrate of claim 1, wherein each pixel structure further includes a connection pattern electrically connecting the thin film transistor and the pixel electrode; the line segments of each of the first common electrodes include : a plurality of first line segments and a plurality of second line segments, each first line segment and at least one data line are alternately arranged, each second line segment is interlaced with the connection pattern of a corresponding pixel structure and is not interlaced with these Data lines overlap. The pixel array substrate of claim 3, wherein the first line segments and the second line segments of the first common electrodes are alternately arranged in the first direction and the second direction. The pixel array substrate according to claim 1, further comprising: a plurality of transfer wires arranged along the first direction and electrically connected to the gate wires; and a transparent shielding pattern disposed between at least one film layer to which the patch cables belong and a film layer to which a plurality of pixel electrodes of the pixel structures belong; Wherein, in the top view of the pixel array substrate, a line segment of a first common electrode and another data line have a first intersection, and the first intersection overlaps an opening of the transparent shielding pattern. The pixel array substrate according to claim 5, further comprising: A plurality of third common electrodes are arranged along the first direction, wherein the pixel structures are arranged in a plurality of pixel rows, and the plurality of pixel structures in each pixel row are arranged along the second direction; on the pixel array substrate , each third common electrode is disposed between adjacent two of the pixel rows; The line segment of the first common electrode and a third common electrode have a second intersection, and the second intersection overlaps the opening of the transparent shielding pattern. The pixel array substrate according to claim 1, further comprising: a plurality of transfer wires arranged along the first direction and electrically connected to the gate wires; and a transparent shielding pattern disposed between at least one film layer to which the patch cables belong and a film layer to which a plurality of pixel electrodes of the pixel structures belong; Wherein, a line segment of a first common electrode and another data line have a first welding point; in the top view of the pixel array substrate, the first welding point overlaps an opening of the transparent shielding pattern. The pixel array substrate according to claim 7, further comprising: A plurality of third common electrodes are arranged along the first direction, wherein the pixel structures are arranged in a plurality of pixel rows, and the plurality of pixel structures in each pixel row are arranged along the second direction; on the pixel array substrate , each third common electrode is disposed between adjacent two of the pixel rows; The line segment of the first common electrode and a third common electrode have a second welding point, and the second welding point overlaps the opening of the transparent shielding pattern. The pixel array substrate according to claim 8, wherein the third common electrode has a first disconnection; in a plan view of the pixel array substrate, the first disconnection and the opening of the transparent shielding pattern overlapping. The pixel array substrate of claim 9, wherein the opening of the transparent shielding pattern has a concave portion overlapping the first disconnection. The pixel array substrate according to claim 1, further comprising: a plurality of transfer wires arranged along the first direction and electrically connected to the gate wires; and a transparent shielding pattern disposed between at least one film layer to which the patch cables belong and a film layer to which a plurality of pixel electrodes of the pixel structures belong; Wherein, in the top view of the pixel array substrate, a line segment of a first common electrode and a patch wire have a third intersection, and the third intersection overlaps an opening of the transparent shielding pattern. The pixel array substrate according to claim 11, further comprising: A plurality of third common electrodes are arranged along the first direction, wherein the pixel structures are arranged in a plurality of pixel rows, and the plurality of pixel structures in each pixel row are arranged along the second direction; on the pixel array substrate , each third common electrode is disposed between adjacent two of the pixel rows; In a plan view of the pixel array substrate, the line segment of the first common electrode and a third common electrode have a fourth intersection, and the fourth intersection overlaps the opening of the transparent shielding pattern. The pixel array substrate according to claim 1, further comprising: a plurality of transfer wires arranged along the first direction and electrically connected to the gate wires; and a transparent shielding pattern disposed between at least one film layer to which the patch cables belong and a film layer to which a plurality of pixel electrodes of the pixel structures belong; Wherein, a line segment of a first common electrode and an adapter wire have a third welding point; in the top view of the pixel array substrate, the third welding point overlaps an opening of the transparent shielding pattern. The pixel array substrate according to claim 13, further comprising: A plurality of third common electrodes are arranged along the first direction, wherein the pixel structures are arranged in a plurality of pixel rows, and the plurality of pixel structures in each pixel row are arranged along the second direction; on the pixel array substrate , each third common electrode is disposed between adjacent two of the pixel rows; The line segment of the first common electrode and a third common electrode have a fourth welding point, and the fourth welding point overlaps the opening of the transparent shielding pattern. The pixel array substrate of claim 14, wherein the third common electrode has a second disconnection; in a plan view of the pixel array substrate, the second disconnection is connected to the opening of the transparent shielding pattern overlapping. The pixel array substrate of claim 15, wherein the opening of the transparent shielding pattern has a concave portion overlapping the second disconnection.

Images