TWI802393B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a base, pixels, pads, bus lines, a multiplexer, gate lines and transmission lines. The pixels are disposed on an active area of the base. The pads are disposed on a first peripheral region of the base. The bus lines are disposed on a second peripheral region of the base. The multiplexer is disposed on a third peripheral region of the base. The gate lines are electrically connected to the multiplexer and arranged in a first direction. The transmission lines are arranged in a second direction. The transmission lines includes first transmission lines. A first end and a second end of each of the first transmission lines are electrically connected to a corresponding pad and a corresponding bus line, respectively.

Description

Pixel Array Substrate

The invention relates to a pixel array substrate.

With the development of display technology, people's demand for display devices is no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect the display device to have an elegant appearance. For example, people expect display devices to have narrow bezels, or even no bezels.

Generally speaking, a display device includes a pixel array disposed on the active area, a plurality of pads disposed on the upper side of the active area, an external driving unit and a gate driving circuit electrically connected to the pads. In order to reduce the width of the left and right sides of the frame of the display device, the first part of the gate driving circuit can be arranged on the left, right or left and right sides of the frame, and the second part of the gate driving circuit can be dispersed in the active area. In order to make the first part of the gate drive circuit and the second part of the gate drive circuit cooperate with each other to display the screen, the external drive unit must be connected to the distributed through multiple pads and multiple fan-out line segments arranged on the upper side of the active area. The second part of the gate driving circuit in the active area is electrically connected. However, the arrangement of multiple fan-out line segments results in a larger upper width of the frame of the active area.

The invention provides a pixel array substrate with good performance.

The pixel array substrate of the present invention includes a substrate, a plurality of pixels, a plurality of pads, a plurality of bus lines, a multiplexer, a plurality of data lines, a plurality of gate lines, a plurality of switching transistors and a plurality of transmission lines . The substrate has an active area, a first peripheral area, a second peripheral area and a third peripheral area, wherein the first peripheral area, the active area and the second peripheral area are arranged in sequence in the first direction, and the third peripheral area and the active area are arranged in the first direction. They are arranged sequentially in the second direction, and the first direction and the second direction are interlaced. A plurality of pixels are arranged in the active area of the substrate, wherein each pixel includes a pixel transistor and a pixel electrode, the pixel transistor has a first end, a second end and a control end, and the pixel electrode is electrically connected to The second terminal of the pixel transistor. A plurality of pads are disposed on the first peripheral area of the base. A plurality of bus lines are arranged on the second peripheral area of the base and arranged in the first direction. The multiplexer is disposed on the third peripheral area of the substrate. A plurality of data lines are disposed on the substrate and arranged in a second direction, wherein the plurality of data lines are electrically connected to a plurality of first terminals of a plurality of pixel transistors of a plurality of pixels. A plurality of gate lines are disposed on the substrate and arranged in a first direction, wherein the plurality of gate lines are electrically connected to the multiplexer. A plurality of switching transistors are arranged in the active area of the substrate, wherein a plurality of pixels are arranged in a plurality of pixel rows, and a plurality of pixels of each pixel row are arranged in the second direction, and each switching transistor has a first terminal, a second terminal and a control terminal, the control terminal of each switching transistor is electrically connected to a corresponding gate line, and the second terminal of each switching transistor is electrically connected to a plurality of corresponding pixel columns Multiple control terminals of multiple pixel transistors of a pixel. A plurality of transmission lines are disposed on the substrate and arranged in the second direction, wherein each transmission line is electrically connected to a corresponding switching transistor The plurality of transmission lines includes a plurality of first transmission lines, and the first end and the second end of each first transmission line are respectively electrically connected to a corresponding pad and a corresponding bus line.

In an embodiment of the present invention, the above-mentioned plurality of transmission lines further includes a plurality of second transmission lines, wherein the first end of each second transmission line is structurally separated from the plurality of pads, and the first end of each second transmission line The two terminals are electrically connected to a corresponding bus line.

In an embodiment of the present invention, the above-mentioned plurality of pads include a group of pads electrically connected to the same film-on-chip package, the group of pads includes a plurality of first pads and a plurality of second pads, and a plurality of first pads. A pad is a plurality of pads farthest from the third peripheral area in the pad group, a plurality of second pads is a plurality of pads in the pad group closest to the third peripheral area, and a plurality of first transmission lines The plurality of first ends are respectively electrically connected to the plurality of first pads of the pad group. The plurality of transmission lines further includes a plurality of third transmission lines, wherein the plurality of first ends of the plurality of third transmission lines are respectively electrically connected to the plurality of second pads of the pad group, and the plurality of second ends of the plurality of third transmission lines The terminals are respectively electrically connected to a plurality of bus lines. In the top view of the pixel array substrate, the plurality of second transmission lines are located between the plurality of first transmission lines and the plurality of third transmission lines.

In an embodiment of the present invention, the above-mentioned plurality of bus lines and the plurality of second transmission lines belong to the first conductive layer and the second conductive layer respectively, and the insulating layer is arranged between the first conductive layer and the second conductive layer. Multiple second ends of the second transmission line are respectively electrically connected to multiple bus lines through multiple contact windows of the insulating layer, and multiple pads and multiple contact windows are respectively disposed on the first peripheral area and the second peripheral area.

In an embodiment of the present invention, each of the above-mentioned first transmission lines includes a fan-out line segment, a plurality of bus lines and a plurality of first transmission lines belong to the first conductive layer and the second conductive layer respectively, and the insulating layer is arranged on the first conductive layer. Between the layer and the second conductive layer, the multiple second ends of the multiple first transmission lines are respectively electrically connected to the multiple bus lines through the multiple contact windows of the insulating layer, and the multiple fan-out routing segments of the multiple first transmission lines and A plurality of contact windows are respectively disposed in the first peripheral area and the second peripheral area.

In an embodiment of the present invention, in the top view of the above-mentioned pixel array substrate, the plurality of pixels are located between the plurality of pads and the plurality of bus lines.

100:Pixel array substrate

110: base

110a: active area

110b-1: The first peripheral area

110b-2: Second peripheral area

110b-3: The third peripheral area

110b-4: The fourth peripheral area

120: Pad

121: The first pad

122: Second pad

130: drive element

140: insulating layer

142, 144: contact window

150: Thin film chip-on-chip package

A21: Switching transistor

A21a, A32a, Ta: first end

A21b, A32b, Tb: second terminal

A21c, A32c, Tc: control terminal

A32: Regulator transistor

BL, BL1, BL2, BL8: bus lines

DL: data line

d1: the first direction

d2: second direction

G-MUX: multiplexer

GL, GL1, GL2, GL8, GL9, GL10, GL16, GL17, GL18, GL24, GL25, GL32: gate line

GP, GP1, GP2, GP3, GP4: gate line group

G120: pad group

HC, HC1, HC2, HC8, HC9, HC10, HC16, HC17, HC18, HC24, HC25, HC26, HC32: transmission line

HCA: first transmission line

HCAa, HCBa, HCCa: first end

HCAb, HCBb, HCCb: second end

HCA-F, HCC-F: Fan-out line segment

HCB: second transmission line

HCC: third transmission line

M1: the first conductive layer

M2: second conductive layer

PE: pixel electrode

R: local

Rspx: pixel column

SPX: pixel

T: pixel transistor

W1, W2: Width

I-I', II-II': section line

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

FIG. 2 is a partial schematic diagram of a pixel array substrate according to an embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a multiplexer according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.

It should be understood that when elements such as layers, films, regions or substrates are referred to as When another element is "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.

As used herein, "about," "approximately," or "substantially" includes stated values and averages within acceptable deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the relative A specific amount of measurement-related error (ie, a limitation of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, "about", "approximately" or "substantially" used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and it is not necessary to use one standard deviation to apply to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

Referring to FIG. 1 , the pixel array substrate 100 includes a base 110 . The base 110 is used to carry the components of the pixel array substrate 100 . For example, in this example, The material of the substrate 110 can be glass, quartz, organic polymer, or opaque/reflective material (eg, wafer, ceramic, or other applicable materials), or other applicable materials.

The substrate 110 has an active region 110a, a first peripheral region 110b-1, a second peripheral region 110b-2 and a third peripheral region 110b-3, wherein the first peripheral region 110b-1, the active region 110a and the second peripheral region 110b- 2 are arranged sequentially in the first direction d1, the third peripheral region 110b-3 and the active region 110a are arranged sequentially in the second direction d2, and the first direction d1 and the second direction d2 are alternately arranged. In this embodiment, the first direction d1 and the second direction d2 are, for example, perpendicular to each other, but the present invention is not limited thereto.

In this embodiment, the substrate 110 further has a fourth peripheral region 110b-4, wherein the third peripheral region 110b-3, the active region 110a, and the fourth peripheral region 110b-4 are sequentially arranged in the second direction d2. For example, in this embodiment, the first peripheral area 110b-1, the second peripheral area 110b-2, the third peripheral area 110b-3, and the fourth peripheral area 110b-4 can be the pixel array substrate 100 respectively. Top border area, bottom border area, left border area and right border area.

FIG. 2 is a partial schematic diagram of a pixel array substrate according to an embodiment of the present invention. Figure 2 corresponds to the part R in Figure 1 . FIG. 1 omits the switching transistor A21 , the voltage stabilizing transistor A32 , the pixel SPX and the data line DL in FIG. 2 .

Please refer to FIG. 1 and FIG. 2, the pixel array substrate 100 also includes a plurality of pixels SPX, disposed in the active area 110a of the substrate 110, wherein each pixel SPX includes a pixel transistor T and a pixel electrode PE, the pixel The transistor T has a first terminal Ta, a second terminal Tb and a control terminal Tc, and the pixel electrode PE is electrically connected to the pixel electrode T. The second terminal Tb.

Referring to FIG. 1 , the pixel array substrate 100 further includes a plurality of pads 120 disposed on the first peripheral region 110 b - 1 of the substrate 110 . The pads 120 are used to electrically connect with the thin film chip-on-chip package 150 . The first peripheral region 110 b - 1 where the pad 120 is located is the signal input side of the pixel array substrate 100 . The driving element film 150 further includes a driving element 130 electrically connected to a plurality of data lines DL. For example, in this embodiment, the driving element 130 may include a chip, and the chip may be selectively bonded to the pads 120 through a Chip On Film (COF) package. However, the present invention is not limited thereto. According to other embodiments, the chip can also be bonded to the pads by Chip On Glass (COG), Tape Automated Bonding (TAB) or other methods. 120 engagement.

The pixel array substrate 100 further includes a plurality of bus lines BL disposed on the second peripheral region 110b-2 of the substrate 110 and arranged in the first direction d1. The bus lines BL are disposed opposite to the signal input side of the pixel array substrate 100 (ie, the first peripheral region 110 b - 1 ), rather than disposed on the signal input side of the pixel array substrate 100 . In the top view of the pixel array substrate 100 , the pixels SPX are located between the pads 120 and the bus lines BL.

FIG. 3 is a schematic circuit diagram of a multiplexer according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 3 , the pixel array substrate 100 further includes a multiplexer G-MUX disposed on the third peripheral area 110 b - 3 of the substrate 110 . In this embodiment, the pixel array substrate 100 may also optionally include another multiplexer G-MUX disposed on the fourth peripheral region 110 b - 4 of the substrate 110 . The circuit of the multiplexer G-MUX shown in Figure 3 is only an exemplary implementation Examples are not intended to limit the invention. In other embodiments, the circuits of the multiplexer G-MUX may also be of other types.

Referring to FIG. 1 and FIG. 2, the pixel array substrate 100 further includes a plurality of data lines DL disposed on the substrate 110 and arranged in the second direction d2, wherein the plurality of data lines DL are electrically connected to a plurality of pixels SPX Multiple first ends Ta of multiple pixel transistors T. The pixel array substrate 100 further includes a plurality of gate lines GL disposed on the substrate 110 and arranged in the first direction d1, wherein the plurality of gate lines GL are at least electrically connected to the third peripheral region 110b-3 The multiplexer G-MUX. In this embodiment, both ends of each gate line GL can be electrically connected to two multiplexers G-MUX located in the third peripheral region 110b-3 and the fourth peripheral region 110b-4 respectively, but the present invention This is not the limit.

Please refer to FIG. 1 and FIG. 2, the pixel array substrate 100 also includes a plurality of switching transistors A21, which are arranged in the active area 110a of the substrate 110, wherein a plurality of pixels SPX are arranged in a plurality of pixel columns Rspx, each pixel A plurality of pixels SPX in the row Rspx are arranged in the second direction d2, each switching transistor A21 has a first terminal A21a, a second terminal A21b and a control terminal A21c, and the control terminal A21c of each switching transistor A21 is electrically connected to a corresponding gate line GL, and the second end A21b of each switching transistor A21 is electrically connected to a plurality of control terminals Tc of a plurality of pixel transistors T in a corresponding pixel column Rspx.

The pixel array substrate 100 further includes a plurality of transmission lines HC disposed on the substrate 110 and arranged in the second direction d2, wherein each transmission line HC is electrically connected to a corresponding first terminal A21a of a switching transistor A21. In this example Among them, the pixel array substrate 100 can also optionally include a plurality of voltage stabilizing transistors A32 arranged corresponding to the plurality of switching transistors A21, wherein the first end A32a of each voltage stabilizing transistor A32 is electrically connected to a corresponding The control terminal A21c of the switching transistor A21, the control terminal A32c and the second terminal A32b of each voltage stabilizing transistor A32 are electrically connected to each other and electrically connected to a plurality of pixel transistors T of a corresponding pixel row Rspx Multiple control terminals Tc.

Please refer to FIG. 1, FIG. 2 and FIG. 3. In this embodiment, the multiple gate lines GL can be divided into multiple gate line groups GP, and the multiple gate line groups GP are arranged sequentially in the first direction d1. , each gate line group GP includes multiple gate lines GL, and multiple gate lines GL of each gate line group GP synchronously receive the gate open signal from the multiplexer G-MUX so that the corresponding Multiple switching transistors A21 are turned on simultaneously. On the other hand, multiple gate line groups GP receive gate open signals from the multiplexer G-MUX at different time intervals according to timing, so that the multiple switch circuits corresponding to multiple gate line groups GP Crystal A21 is turned on sequentially in different time intervals.

For example, in this embodiment, the multiple gate lines GL can be divided into multiple gate line groups GP1, GP2, GP3, and GP4, and the multiple gate line groups GP1, GP2, GP3, and GP4 are in the first direction. Arranged in sequence on d1, each gate line group GP1, GP2, GP3, GP4 includes 8 gate lines GL1~GL8, GL9~GL16, GL17~GL24, GL25~GL32, each gate line group GP1, GP2 The 8 gate lines GL1~GL8, GL9~GL16, GL17~GL24, GL25~GL32 of , GP3, GP4 receive the gate open signal from the multiplexer G-MUX synchronously, so that the corresponding multiple switching transistors A21 is turned on at the same time. On the other hand, multiple gates The pole line groups GP1, GP2, GP3, and GP4 receive the gate open signals from the multiplexer G-MUX in different time intervals according to the timing, so that the corresponding multiple gate line groups GP1, GP2, GP3, and GP4 A plurality of switching transistors A21 are turned on sequentially in different time intervals.

In this embodiment, each transmission line HC corresponds to one gate line GL. For example, in this embodiment, multiple transmission lines HC1~HC8, HC9~HC16, HC17~HC24, HC25~HC32 respectively correspond to multiple gate lines GL1~GL8, GL9~GL16, GL17~GL24, GL25~GL32 .

When multiple gate lines GL of a certain gate line group GP receive the gate open signal from the multiplexer G-MUX synchronously in a time interval, so that the multiple gates respectively corresponding to a certain gate line group GP Multiple switching transistors A21 of the polar line GL are turned on at the same time; within this time interval, the external drive unit will provide a pixel gate turn-on signal through the film-on-chip package 150 to the corresponding gate line group GP in sequence. The multiple transmission lines HC of the multiple gate lines GL enable the multiple pixel transistors T of the multiple pixel columns Rspx corresponding to the multiple gate lines GL of the same gate line group GP to be turned on sequentially, thereby making the corresponding The plurality of pixel electrodes PE of the plurality of pixel columns Rspx of the plurality of gate lines GL of the same gate line group GP are charged to a specified potential.

For example, the multiple gate lines GL1~GL8 of the gate line group GP1 receive the gate open signal from the multiplexer G-MUX synchronously in a time interval, so that the multiple gate lines corresponding to the gate line group GP1 respectively The multiple switching transistors A21 of the gate lines GL1~GL8 are turned on at the same time; during this time interval, the external drive unit will provide pixel gate open signals to the corresponding multiple gate lines in sequence through the thin film chip-on-chip package 150 The plurality of transmission lines HC1~HC8 of GL1~GL8 enable the plurality of pixel transistors T of the plurality of pixel columns Rspx corresponding to the plurality of gate lines GL1~GL8 of the same gate line group GP1 to be turned on in time sequence, thereby enabling The plurality of pixel electrodes PE of the plurality of pixel columns Rspx corresponding to the plurality of gate lines GL1 - GL8 of the same gate line group GP1 are charged to a specified potential.

The plurality of transmission lines HC of the pixel array substrate 100 includes a plurality of first transmission lines HCA, and the first end HCAa and the second end HCAb of each first transmission line HCA are respectively electrically connected to a corresponding pad 120 and a corresponding one. Bus line BL. The plurality of transmission lines HC of the pixel array substrate 100 further includes a plurality of second transmission lines HCB, wherein the first end HCBa of each second transmission line HCB is structurally separated from the plurality of pads 120, and each second transmission line HCB The second end HCBb is electrically connected to a corresponding bus line BL.

It is worth mentioning that the plurality of bus lines BL are arranged in the second peripheral area 110b-2 with a relatively large layout area, and the plurality of second transmission lines HCB are arranged in the second peripheral area 110b-2 using the existing plurality of first transmission lines HCA and The plurality of bus lines BL in the peripheral region 110b-2 receive the pixel gate turn-on signal from the thin film chip-on-chip package 150, and the second transmission line HCB itself may not have a fan-out line segment disposed in the first peripheral region 110b-1. Thereby, without excessively affecting the width W2 of the second peripheral region 110b-2 in the first direction d1 (that is, the width of the lower frame region), the first peripheral region 110b-1 of the pixel array substrate 100 is The width W1 in the first direction d1 (ie, the width of the upper frame area) is reduced.

For example, in this embodiment, a plurality of bus lines BL are included in the first A plurality of bus lines BL1~BL8 arranged in sequence in the direction d1, a plurality of first transmission lines HCA include transmission lines HC1~HC8, and a plurality of second transmission lines HCB include transmission lines HC17~HC24, wherein the transmission line HC17 utilizes the existing transmission line HC1 And the bus line BL1 arranged in the second peripheral area 110b-2 receives the pixel gate turn-on signal from the film-on-chip package 150, and the transmission line HC18 utilizes the existing transmission line HC2 and is arranged in the second peripheral area 110b-2. The bus line BL2 receives the pixel gate turn-on signal from the thin film chip-on-chip package 150, . The pixel gate turn-on signal of the flip-chip package 150 , but the present invention is not limited thereto.

Referring to FIG. 1, the multiple pads 120 of the pixel array substrate 100 include a pad group G120 electrically connected to the same thin film chip-on-chip package 150, and the pad group G120 includes a plurality of first pads 121 and a plurality of second pads. The pads 122, the plurality of first pads 121 are the plurality of pads 120 farthest from the third peripheral region 110b-3 among the pad group G120, and the plurality of second pads 122 are the most distant among the pad group G120. The plurality of pads 120 are adjacent to the third peripheral region 110b-3. In this embodiment, the first ends HCAa of the first transmission lines HCA are electrically connected to the first pads 121 of the pad group G120 respectively.

In this embodiment, the plurality of transmission lines HC further includes a plurality of third transmission lines HCC, wherein the plurality of first ends HCCa of the plurality of third transmission lines HCC are respectively electrically connected to the plurality of second pads 122 of the pad group G120 , and the plurality of second terminals HCCb of the plurality of third transmission lines HCC are respectively electrically connected to the plurality of bus lines BL. In the top view of the pixel array substrate 100, the plurality of second transmission lines HCB are located Between a transmission line HCA and multiple third transmission lines HCC. That is to say, there will be at least another group of transmission lines HC between the groups of transmission lines HC having fan-out routing segments HCA-F, HCC-F and electrically connected to the left and right outermost pads 120, and the other group of transmission lines HC There is no fan-out line segment in the first peripheral region 110b-1.

For example, in this embodiment, the multiple first transmission lines HCA include transmission lines HC1-HC8, the multiple second transmission lines HCB include transmission lines HC17-HC24 and HC25-HC32, and the multiple third transmission lines HCC include transmission lines HC9-HC16; In the top view of the pixel array substrate 100, the transmission lines HC17~HC24 and HC25~HC32 without fan-out routing segments in the first peripheral region 110b-1 are located on the multiple transmission lines HC1~HC8 with fan-out routing segments HCA-F and HCC-F and multiple transmission lines HC9~HC16, but the present invention is not limited thereto.

FIG. 4 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. Fig. 4 corresponds to section line I-I' of Fig. 1 . FIG. 5 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. FIG. 5 corresponds to the section line II-II of FIG. 1 .

Please refer to FIG. 1 and FIG. 4. In this embodiment, each first transmission line HCA includes a fan-out line segment HCA-F, and a plurality of bus lines BL and a plurality of first transmission lines HCA belong to the first conductive layer M1 and the second conductive layer respectively. The conductive layer M2, the insulating layer 140 is disposed between the first conductive layer M1 and the second conductive layer M2, the multiple second ends HCAb of the multiple first transmission lines HCA are electrically connected through the multiple contact windows 142 of the insulating layer 140 At most a plurality of bus lines BL. In particular, the plurality of fan-out segments HCA-F and the plurality of contact windows 142 of the plurality of first transmission lines HCA are respectively disposed in the first peripheral area 110b-1 and the second peripheral area 110b-2. That is, the fan of the first transmission line HCA The outgoing line segment HCA-F and the junction of the first transmission line HCA and the bus line BL are respectively located in the upper frame area and the lower frame area, not all of them are located in the upper frame area.

Please refer to FIG. 1 and FIG. 5 , in this embodiment, a plurality of bus lines BL and a plurality of second transmission lines HCB belong to the first conductive layer M1 and the second conductive layer M2 respectively, and the insulating layer 140 is disposed on the first conductive layer M1 Between the second conductive layer M2 and the plurality of second ends HCBb of the plurality of second transmission lines HCB are respectively electrically connected to the plurality of bus lines BL through the plurality of contact windows 144 of the insulating layer 140, and the plurality of pads 120 and the plurality of The contact windows 144 are respectively disposed on the first peripheral region 110b-1 and the second peripheral region 110b-2. That is to say, the bonding pads 120 for bonding with the thin film chip-on-chip package 150 and the connecting points of the second transmission line HCB and the bus line BL are respectively located in the upper frame area and the lower frame area, not both are located in the upper frame area.

100:Pixel array substrate

110: base

110a: active area

110b-1: First peripheral area

110b-2: Second peripheral area

110b-3: The third peripheral area

110b-4: The fourth peripheral area

120: Pad

121: The first pad

122: Second pad

130: drive element

142, 144: contact window

150: Thin film chip-on-chip package

BL, BL1, BL2, BL8: bus lines

d1: the first direction

d2: second direction

G-MUX: multiplexer

GL, GL1, GL2, GL8, GL9, GL10, GL16, GL17, GL18, GL24, GL25, GL32: gate line

GP, GP1, GP2, GP3, GP4: gate line group

G120: pad group

HC, HC1, HC2, HC8, HC9, HC10, HC16, HC17, HC18, HC24, HC25, HC26, HC32: transmission line

HCA: first transmission line

HCAa, HCBa, HCCa: first end

HCAb, HCBb, HCCb: second end

HCA-F, HCC-F: Fan-out line segment

HCB: second transmission line

HCC: third transmission line

R: local

W1, W2: Width

I-I', II-II': section line

Claims (6)

A pixel array substrate, comprising: A substrate having an active area, a first peripheral area, a second peripheral area and a third peripheral area, wherein the first peripheral area, the active area and the second peripheral area are sequentially arranged in a first direction arranged, the third peripheral area and the active area are arranged sequentially in a second direction, and the first direction and the second direction are staggered; A plurality of pixels are arranged in the active area of the substrate, wherein each pixel includes a pixel transistor and a pixel electrode, and the pixel transistor has a first terminal, a second terminal and a control terminal , and the pixel electrode is electrically connected to the second end of the pixel transistor; a plurality of pads disposed on the first peripheral area of the substrate; a plurality of bus lines disposed on the second peripheral region of the substrate and arranged in the first direction; a multiplexer disposed on the third peripheral area of the substrate; a plurality of data lines arranged on the substrate and arranged in the second direction, wherein the data lines are electrically connected to a plurality of first ends of a plurality of pixel transistors of the pixels; a plurality of gate lines arranged on the substrate and arranged in the first direction, wherein the gate lines are electrically connected to the multiplexer; A plurality of switching transistors are arranged in the active area of the substrate, wherein the pixels are arranged in a plurality of pixel columns, and a plurality of pixels in each pixel column are arranged in the second direction, and each switching transistor The crystal has a first terminal, a second terminal and a control terminal, the control terminal of each switching transistor is electrically connected to a corresponding gate line, and the second terminal of each switching transistor is electrically A plurality of control terminals of a plurality of pixel transistors of a plurality of pixels connected to a corresponding pixel row; and a plurality of transmission lines arranged on the substrate and arranged in the second direction, wherein each transmission line is electrically connected to the first end of a corresponding switching transistor, the transmission lines include a plurality of first transmission lines, and A first end and a second end of each first transmission line are respectively electrically connected to a corresponding pad and a corresponding bus line. The pixel array substrate as described in claim 1, wherein the transmission lines further include: A plurality of second transmission lines, wherein a first end of each second transmission line is structurally separated from the pads, and a second end of each second transmission line is electrically connected to a corresponding bus line. The pixel array substrate as claimed in claim 2, wherein the pads include a pad group electrically connected to the same thin film chip-on-chip package, and the pad group includes a plurality of first pads and a plurality of second pads Pads, the first pads are the plurality of pads in the group of pads that are farthest from the third peripheral area, and the second pads are the plurality of pads in the group of pads that are closest to the third peripheral area a plurality of pads, the plurality of first ends of the first transmission lines are respectively electrically connected to the first pads of the pad group, and the transmission lines further include: A plurality of third transmission lines, wherein a plurality of first ends of the third transmission lines are respectively electrically connected to the second pads of the pad group, and a plurality of second ends of the third transmission lines are respectively electrically connected connected to the bus lines; In the top view of the pixel array substrate, the second transmission lines are located between the first transmission lines and the third transmission lines. The pixel array substrate as described in claim 2, wherein the bus lines and the second transmission lines belong to a first conductive layer and a second conductive layer respectively, and an insulating layer is disposed on the first conductive layer and the second conductive layer Between the two conductive layers, the multiple second ends of the second transmission lines are respectively electrically connected to the bus lines through the multiple contact windows of the insulating layer, and the pads and the contact windows are respectively arranged on the The first peripheral area and the second peripheral area. The pixel array substrate as described in claim 1, wherein each of the first transmission lines includes a fan-out line segment, the bus lines and the first transmission lines belong to a first conductive layer and a second conductive layer, respectively, and a The insulating layer is disposed between the first conductive layer and the second conductive layer, and the plurality of second ends of the first transmission lines are respectively electrically connected to the bus lines through the plurality of contact windows of the insulating layer, and the The plurality of fan-out routing segments of the first transmission lines and the contact windows are respectively disposed in the first peripheral region and the second peripheral region. The pixel array substrate as claimed in claim 1, wherein in the top view of the pixel array substrate, the pixels are located between the pads and the bus lines.

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