TWI786924B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes common electrodes, driving elements, switches, a main signal line, connection lines and an auxiliary signal line. The common electrodes are arranged in common electrode columns and common electrode rows. First ends of the switches are electrically connected to the main signal line. Each of the connection lines is electrically connected to a second end of one of the switches and one of the common electrodes. The auxiliary signal line is electrically connected to at least one of the driving elements and the main signal line. In a top view of the pixel array substrate, the auxiliary signal line is located between the common electrode columns.

Description

Pixel Array Substrate

The invention relates to a pixel array substrate.

With the development of technology, touch display devices are widely used in daily life due to their advantages of a friendly human-machine interface. Among them, the capacitive touch technology judges the position of the touch point by reflecting the capacitance change caused by the touch object (such as a finger, a stylus). The touch display panel can be roughly divided into an external mount type and an in-cell type. The in-cell touch display panel has the advantages of thinner thickness and lighter weight, so it is widely favored by the public.

The in-cell touch display panel uses common electrodes divided into multiple blocks as touch electrodes. In order to provide a common signal to all common electrodes in the active area during the display time interval of the in-cell touch display panel, generally speaking, a signal line arranged in the peripheral area and electrically connected to the outermost driving element is used. to provide it. However, as the size of the in-cell touch display panel increases, the length of the signal lines disposed in the peripheral area becomes longer and longer, and the resistance-capacitance load (RC load) is large, resulting in many The multiple common signals received by a common electrode cannot all have ideal values.

The invention provides a pixel array substrate with good performance.

The pixel array substrate of the present invention includes a substrate, a plurality of pixel structures, a plurality of common electrodes, a plurality of driving elements, a plurality of switching elements, at least one main signal line, a main control line, a plurality of connection lines and at least one auxiliary signal line. The base has an active area, a first peripheral area and a second peripheral area, wherein the first peripheral area and the second peripheral area are disposed on opposite sides of the active area. Multiple pixel structures are disposed on the active area of the base. Multiple common electrodes overlap multiple pixel structures. A plurality of common electrodes are arranged into a plurality of common electrode columns and a plurality of common electrode rows, a plurality of common electrodes of each common electrode row are arranged in a first direction, and a plurality of common electrodes of each common electrode row are arranged in a second direction arranged, and the first direction and the second direction are staggered. A plurality of driving elements are disposed on the first peripheral area of the substrate, wherein the plurality of driving elements include the first driving element to the nth driving element arranged in sequence in the first direction, and n is a positive integer greater than or equal to 2 . A plurality of switching elements are disposed on the second peripheral area of the base, and each switching element has a first terminal, a second terminal and a control terminal. At least one main signal line is disposed on the second peripheral area of the substrate, wherein the plurality of first ends of the plurality of switching elements are electrically connected to the at least one main signal line, and the at least one main signal line is electrically connected to the first driver element and the nth drive element. The main control line is disposed on the second peripheral area of the substrate, wherein the plurality of control ends of the plurality of switching elements are electrically connected to the main control line, and the main control line is electrically connected to the first driving element and the nth driving element . A plurality of connection lines are electrically connected to a plurality of driving elements, wherein each connection line is electrically connected to a second terminal of one of the plurality of switching elements and one of the plurality of common electrodes. At least one auxiliary signal line is electrically connected to at least one of the driving elements and at least one main signal line. Especially, in the top view of the pixel array substrate, at least one auxiliary signal line is located between the plurality of common electrode rows.

In an embodiment of the present invention, the above-mentioned multiple common electrode columns are arranged sequentially in the first direction, and include multiple odd-numbered common electrode columns and multiple even-numbered common electrode columns; the multiple connecting lines include multiple first Connecting wires and a plurality of second connecting wires, the plurality of first connecting wires are electrically connected to a plurality of odd-numbered common electrode rows, and the plurality of second connecting wires are electrically connected to a plurality of even-numbered common electrode rows; the plurality of switching elements include a plurality of second A switch element and a plurality of second switch elements, the plurality of second ends of the plurality of first switch elements are electrically connected to the plurality of first connection lines, and the plurality of second ends of the plurality of second switch elements are electrically connected to the plurality of wires The second connection line; at least one main signal line includes a first main signal line and a second main signal line, a plurality of first ends of a plurality of first switching elements are electrically connected to the first main signal line, a plurality of second switches A plurality of first ends of the components are electrically connected to the second main signal line; at least one auxiliary signal line includes a first auxiliary signal line, and the first auxiliary signal line is electrically connected to at least one of the plurality of driving elements and the first main signal line lines, wherein in the top view of the pixel array substrate, the first auxiliary signal lines are located between adjacent two of the plurality of common electrode rows.

In an embodiment of the present invention, the above-mentioned at least one auxiliary signal line further includes a second auxiliary signal line, and the second auxiliary signal line is electrically connected to at least one of the plurality of driving elements and the second main signal line; In the top view of the array substrate, the second auxiliary signal lines are located between adjacent two of the plurality of common electrode rows.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes at least one data line electrically connected to a plurality of pixel structures, wherein at least one auxiliary signal line overlaps at least one data line.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes an auxiliary control line electrically connected to at least one of the plurality of driving elements and the main control line, wherein in the top view of the pixel array substrate, the auxiliary control line It is located between adjacent two of the multiple common electrode rows.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes at least one data line electrically connected to a plurality of pixel structures, wherein the auxiliary control line overlaps the at least one data line.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.

As used herein, "about," "approximately," or "substantially" includes stated values and averages within acceptable deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the relative A specific amount of measurement-related error (ie, the limit of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Moreover, "about", "approximately" or "substantially" used herein may select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and may not use one standard deviation to apply to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention.

1 shows a substrate 110, a common electrode 120, a driving element 130, a switching element SW, a main signal line 141, an auxiliary signal line 142, a main control line 151, and an auxiliary control line 152, while other components of the pixel array substrate 100 are omitted.

FIG. 2 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 corresponds to part A of FIG. 1 .

FIG. 3 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 3 corresponds to part B of FIG. 1 .

1, the pixel array substrate 100 includes a substrate 110, has an active region 110a, a first peripheral region 110b and a second peripheral region 110c, wherein the first peripheral region 110b and the second peripheral region 110c are disposed opposite to the active region 110a sides. For example, in this embodiment, the second peripheral area 110c and the first peripheral area 110b can be respectively an upper frame area and a lower frame area disposed on the upper and lower sides of the active area 110a, but the present invention is not limited thereto . In this embodiment, the material of the substrate 110 can be glass, quartz, organic polymer, or opaque/reflective material (for example: wafer, ceramic, or other applicable materials), or other applicable Material.

Referring to FIG. 1 and FIG. 2 , the pixel array substrate 100 further includes a plurality of pixel structures PX disposed on the active region 110 a of the substrate 110 . For example, in this embodiment, each pixel structure PX may include a thin film transistor T and a pixel electrode PE, wherein the thin film transistor T has a first end Ta, a second end Tb and a control end Tc, and the drawing The prime electrode PE is electrically connected to the second terminal Tb of the TFT T. In this embodiment, the pixel array substrate 100 further includes a plurality of data lines DL and a plurality of scan lines SL arranged alternately, wherein the data lines DL are electrically connected to the first end Ta of the thin film transistor T of the pixel structure PX , and the scan line SL is electrically connected to the control terminal Tc of the thin film transistor T of the pixel structure PX.

Referring to FIG. 1 and FIG. 2 , the pixel array substrate 100 further includes a plurality of common electrodes 120 overlapping the plurality of pixel structures PX. For example, in this embodiment, each common electrode 120 can overlap the pixel electrodes PE of a plurality of pixel structures PX. In this embodiment, during the display time interval, the common electrode 120 has a common signal, and the electric field between the common electrode 120 and the pixel electrode PE is used to drive the display medium (not shown). In this embodiment, during the touch time interval, the common electrode 120 is used as a touch sensing electrode and has a touch signal.

Please refer to FIG. 1, a plurality of common electrodes 120 are arranged into a plurality of common electrode columns R and a plurality of common electrode rows C, and a plurality of common electrodes 120 of each common electrode row C are arranged in the first direction d1, and each common electrode The plurality of common electrodes 120 of the row R are arranged in the second direction d2, and the first direction d1 and the second direction d2 are intersected. For example, in this embodiment, the first direction d1 and the second direction d2 may be perpendicular, but the invention is not limited thereto.

Referring to FIG. 1, the pixel array substrate 100 further includes a plurality of driving elements 130 disposed on the first peripheral region 110b of the substrate 110, wherein the plurality of driving elements 130 include first driving elements arranged in sequence in the first direction d1. The element 130 to the nth driving element 130 , and n is a positive integer greater than or equal to 2. For example, in this embodiment, n=6. That is to say, in this embodiment, the number of driving elements 130 is six. However, the present invention is not limited thereto, and in other embodiments, the number of driving elements 130 may also be 3, 4, 5, 7 or more than 8. In addition, in this embodiment, the driving element 130 is, for example, an integrated circuit (integrated circuit; IC), but the present invention is not limited thereto.

Please refer to FIG. 1, the pixel array substrate 100 further includes a plurality of switching elements SW disposed on the second peripheral region 110c of the substrate 110, wherein each switching element SW has a first end SWa, a second end SWb and a control end SWc . In this embodiment, the switch element SW is, for example, a thin film transistor formed on the second peripheral region 110c of the substrate 110, but the invention is not limited thereto.

Please refer to FIG. 1 , the pixel array substrate 100 further includes a main signal line 141 disposed on the second peripheral region 110c of the substrate 110 , wherein a plurality of first terminals SWa of a plurality of switching elements SW are electrically connected to the main signal line 141 , and the main signal line 141 is electrically connected to the first driving element 130 and the nth driving element 130 . For example, in the present embodiment, the two ends of the main signal line 141 are respectively electrically connected to the two driving elements 130 located on the leftmost and the rightmost of the substrate 110 .

Referring to FIG. 1, the pixel array substrate 100 further includes a main control line 151 disposed on the second peripheral region 110c of the substrate 110, wherein a plurality of control ends SWc of a plurality of switching elements SW are electrically connected to the main control line 151, And the main control line 151 is electrically connected to the first driving element 130 and the nth driving element 130 . For example, in this embodiment, both ends of the main control line 151 are electrically connected to the two driving elements 130 located on the leftmost and rightmost sides of the substrate 110 respectively.

Referring to FIG. 1, the pixel array substrate 100 further includes a plurality of connection lines 160 electrically connected to a plurality of driving elements 130, wherein each connection line 160 is electrically connected to the second end SWb and the second end SWb of one of the plurality of switching elements SW. One of the plurality of common electrodes 120 .

Referring to FIG. 1 , it is worth noting that the pixel array substrate 100 further includes an auxiliary signal line 142 electrically connected to at least one of the driving elements 130 and the main signal line 141 . For example, in this embodiment, one end of the auxiliary signal line 142 can be electrically connected to the main signal line 141 , and the other end of the auxiliary signal line 142 can be electrically connected to two adjacent driving elements 130 left and right. In particular, in the top view of the pixel array substrate 100 , the auxiliary signal line 142 is located between two adjacent common electrode rows C. As shown in FIG. That is to say, the auxiliary signal lines 142 are interspersed in the active area 110a. Through the setting of the auxiliary signal line 142 , the common signal can not only be provided to the common electrode 120 through the main signal line 141 disposed around the periphery, but also the common signal can be provided through the auxiliary signal line 142 interspersed in the active area 110 a. Thereby, the magnitude of the common signal obtained by the plurality of common electrodes 120 on the entire active region 110a can be closer to an ideal value, which helps to improve the electrical properties of the display panel including the pixel array substrate 100 .

Please refer to FIG. 1 and FIG. 2 , in this embodiment, the auxiliary signal line 142 may overlap the data line DL. The auxiliary signal line 142 and the data line DL respectively belong to two different conductive layers, and at least one insulating layer (not shown) is disposed between the auxiliary signal line 142 and the data line DL. For example, in this embodiment, the scan line SL, the data line DL and the auxiliary signal line 142 may respectively belong to the first metal layer, the second metal layer and the third metal layer stacked on the substrate 110 in sequence, but this The invention is not limited thereto.

Referring to FIG. 1 , in this embodiment, the pixel array substrate 100 may optionally further include an auxiliary control line 152 electrically connected to at least one of the driving elements 130 and the main control line 151 . For example, in this embodiment, one end of the auxiliary control line 152 can be electrically connected to the main control line 151, and the other end of the auxiliary control line 152 can be electrically connected to two adjacent driving elements 130 left and right, but The present invention is not limited thereto.

It should be noted that, in the top view of the pixel array substrate 100 , the auxiliary control line 152 is located between two adjacent common electrode rows C. As shown in FIG. That is to say, the auxiliary control line 152 is interspersed in the active area 110a. Through the setting of the auxiliary control line 152, the gate opening signal can not only be provided to the plurality of switching elements SW located in the second peripheral area 110c of the substrate 110 through the main control line 151, but also the gate opening signal can be passed through the active area 110a. The auxiliary control line 152 is provided. Thereby, the magnitudes of the gate turn-on signals obtained by the plurality of switching elements SW on the entire second peripheral region 110c can be relatively consistent, which helps to improve the electrical properties of the display panel including the pixel array substrate 100 .

Referring to FIG. 1 and FIG. 3 , in this embodiment, the auxiliary control line 152 may overlap another data line DL. The auxiliary control line 152 and the data line DL respectively belong to two different conductive layers, and at least one insulating layer (not shown) is disposed between the auxiliary control line 152 and the data line DL. For example, in this embodiment, the scan line SL, the data line DL and the auxiliary control line 152 may respectively belong to the first metal layer, the second metal layer and the third metal layer stacked on the substrate 110 in sequence, but this The invention is not limited thereto.

Referring to FIG. 1 , in this embodiment, the plurality of auxiliary signal lines 142 and the plurality of auxiliary control lines 152 may be selectively arranged alternately in the second direction d2. However, the present invention is not limited thereto. In other embodiments, the order in which the auxiliary signal lines 142 and the auxiliary control lines 152 are inserted in the active area 110a can be designed in other ways according to actual requirements. In addition, the present invention does not limit the pixel array substrate 100 to include the auxiliary control line 152; To set the auxiliary signal line 142 .

It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the aforementioned embodiments, and the following embodiments will not be repeated.

FIG. 4 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. The pixel array substrate 100A in FIG. 4 is similar to the pixel array substrate 100 in FIG. 1 , and the differences between them are described as follows.

Referring to FIG. 4 , a plurality of common electrode rows R are arranged sequentially in the first direction d1 , and include a plurality of odd common electrode rows Ro and a plurality of even common electrode rows RE. The plurality of connection lines 160 includes a plurality of first connection lines 161 and a plurality of second connection lines 162, the plurality of first connection lines 161 are electrically connected to a plurality of odd-numbered common electrode columns Ro, and the plurality of second connection lines 162 are electrically connected to Connect to a plurality of even-numbered common electrode columns RE. The plurality of switch elements SW includes a plurality of first switch elements SW1 and a plurality of second switch elements SW2, and a plurality of second terminals SWb of the plurality of first switch elements SW1 are electrically connected to a plurality of first connection lines 161, and a plurality of The plurality of second ends SWb of the second switch element SW2 are electrically connected to the plurality of second connection lines 162 .

The main signal line 141 includes a first main signal line 141a and a second main signal line 141b, wherein a plurality of first terminals SWa of a plurality of first switch elements SW1 are electrically connected to the first main signal line 141a, and a plurality of second switch elements SW1 are electrically connected to the first main signal line 141a. The plurality of first ends SWa of the element SW2 are electrically connected to the second main signal line 141b. The auxiliary signal line 142 includes a first auxiliary signal line 142a and a second auxiliary signal line 142b, wherein the first auxiliary signal line 142a is electrically connected to at least one of the plurality of driving elements 130 and the first main signal line 141a, and the second auxiliary signal line 142a The signal line 142b is electrically connected to at least one of the driving elements 130 and the second main signal line 141b.

It should be noted that, in the top view of the pixel array substrate 100A, the first auxiliary signal line 142a is located between adjacent two of the multiple common electrode rows C, and the second auxiliary signal line 142b is located between the multiple common electrode rows C between the other adjacent two. The pixel array substrate 100A in FIG. 4 has similar effects and advantages to the pixel array substrate 100 in FIG. 1 , which will not be repeated here.

100, 100A: pixel array substrate

110: base

110a: active area

110b: The first peripheral area

110c: the second peripheral area

120: common electrode

130: drive element

141: Main signal line

141a: The first main signal line

141b: The second main signal line

142: Auxiliary signal line

142a: The first auxiliary signal line

142b: Second auxiliary signal line

151: Main control line

152: Auxiliary control line

160: connecting line

161: The first connection line

162: the second connection line

A, B: Partial

C: common electrode row

DL: data line

d1: the first direction

d2: second direction

PX: pixel structure

PE: pixel electrode

R: common electrode row

R _o : Odd-numbered common electrode columns

R _E : Even-numbered common electrode column

SL: scan line

SW: switching element

SW1: first switching element

SW2: second switching element

SWa, Ta: first end

SWb, Tb: the second terminal

SWc, Tc: control terminal

T: thin film transistor

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 3 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 4 is a schematic top view of a pixel array substrate according to another embodiment of the present invention.

100:Pixel array substrate

110: base

110a: active area

110b: The first peripheral area

110c: the second peripheral area

120: common electrode

130: drive element

141: Main signal line

142: Auxiliary signal line

151: Main control line

152: Auxiliary control line

160: connecting line

A, B: Partial

C: common electrode row

d1: the first direction

d2: second direction

R: common electrode column

SW: switching element

SWa: first end

SWb: second terminal

SWc: control terminal

Claims (6)

A pixel array substrate, comprising: a substrate having an active area, a first peripheral area and a second peripheral area, wherein the first peripheral area and the second peripheral area are arranged on opposite sides of the active area; A plurality of pixel structures are arranged on the active area of the substrate; a plurality of common electrodes are overlapped on the pixel structures, wherein the common electrodes are arranged into a plurality of common electrode columns and a plurality of common electrode rows, each A plurality of common electrodes in the common electrode row are arranged in a first direction, a plurality of common electrodes in each common electrode column are arranged in a second direction, and the first direction and the second direction are intersected; a plurality of Driving elements disposed on the first peripheral region of the substrate, wherein the driving elements include the first driving element to the nth driving element sequentially arranged in the first direction, and n is greater than or equal to 2 positive integer; a plurality of switching elements arranged on the second peripheral area of the substrate, wherein each of the switching elements has a first end, a second end and a control end; at least one main signal line is arranged on the On the second peripheral region of the substrate, wherein the plurality of first ends of the switching elements are electrically connected to the at least one main signal line, and the at least one main signal line is electrically connected to the first driving element and the nth driving element; a main control line, disposed on the second peripheral area of the substrate, wherein a plurality of control terminals of the switching elements are electrically connected to the main control line, and the main control line is electrically connected to the first driving element and the nth driving element; a plurality of connecting lines electrically connected to the driving elements, each of which is connected to the driving element electrically connected to the second end of one of the switching elements and one of the common electrodes; and at least one auxiliary signal line electrically connected to at least one of the driving elements and at least one main signal line , wherein in the top view of the pixel array substrate, the at least one auxiliary signal line is located between the common electrode rows. The pixel array substrate as described in claim 1, wherein the common electrode columns are arranged sequentially in the first direction, and include a plurality of odd-numbered common electrode columns and a plurality of even-numbered common electrode columns; the connecting lines include multiple A first connection line and a plurality of second connection lines, the first connection lines are electrically connected to the odd-numbered common electrode columns, and the second connection lines are electrically connected to the even-numbered common electrode columns; the switches The element includes a plurality of first switch elements and a plurality of second switch elements, the plurality of second ends of the first switch elements are electrically connected to the first connection lines, and the plurality of second ends of the second switch elements Terminals are electrically connected to the second connection lines; the at least one main signal line includes a first main signal line and a second main signal line, and a plurality of first ends of the first switching elements are electrically connected to the The first main signal line, the plurality of first ends of the second switching elements are electrically connected to the second main signal line; the at least one auxiliary signal line includes a first auxiliary signal line, and the first auxiliary signal line is electrically connected to the first auxiliary signal line. is permanently connected to at least one of the driving elements and the first main signal line, wherein in the plan view of the pixel array substrate, the first auxiliary signal line is located between adjacent two of the common electrode rows. The pixel array substrate as described in claim 2, wherein the at least one auxiliary signal line further includes a second auxiliary signal line, and the second auxiliary signal line is electrically connected to at least one of the driving elements and the second The main signal line; in the pixel array base In the top view of the board, the second auxiliary signal line is located between adjacent two of the common electrode rows. The pixel array substrate as described in Claim 1 further includes: at least one data line electrically connected to the pixel structures, wherein the at least one auxiliary signal line overlaps the at least one data line. The pixel array substrate as described in claim 1, further comprising: an auxiliary control line electrically connected to at least one of the driving elements and the main control line, wherein in the top view of the pixel array substrate, the The auxiliary control lines are located between adjacent two of the common electrode rows. The pixel array substrate as claimed in claim 5 further includes: at least one data line electrically connected to the pixel structures, wherein the auxiliary control line overlaps the at least one data line.

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