TW202320050A - Pixel array substrate - Google Patents
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本發明是有關於一種畫素陣列基板。The invention relates to a pixel array substrate.
隨著科技的發展,觸控顯示裝置因具有人機介面友善的優點,而被廣泛應用於日常生活中。其中,電容式觸控技術通過反應觸控物體(例如手指、觸控筆)造成的電容量變化來判斷觸控點的位置。觸控顯示面板可大致上區分為外貼式與內嵌式(in-cell)。內嵌式觸控顯示面板具有厚度較薄與重量較輕的優點,因此,廣受大眾喜愛。With the development of technology, touch display devices are widely used in daily life due to their advantages of a friendly human-machine interface. Among them, the capacitive touch technology judges the position of the touch point by reflecting the capacitance change caused by the touch object (eg finger, stylus). The touch display panel can be roughly divided into an external mount type and an in-cell type. The in-cell touch display panel has the advantages of thinner thickness and lighter weight, so it is widely favored by the public.
內嵌式觸控顯示面板是使用被劃分為多個區塊的共用電極做為觸控電極使用。為了在內嵌式觸控顯示面板的顯示時間區間內,提供共用訊號到主動區內的所有共用電極,一般而言,是利用設置於周邊區且與最外側的驅動元件電性連接的訊號線來提供之。然而,隨著內嵌式觸控顯示面板的尺寸增加,設置於周邊區的訊號線的長度也越來越長,阻容負載(resistance-capacitance load;RC load)大,導致位於各處的多個共用電極所接收到的多個共用訊號無法都具有理想值。The in-cell touch display panel uses common electrodes divided into multiple blocks as touch electrodes. In order to provide a common signal to all common electrodes in the active area during the display time interval of the in-cell touch display panel, generally speaking, a signal line arranged in the peripheral area and electrically connected to the outermost driving element is used. to provide it. However, as the size of the in-cell touch display panel increases, the length of the signal lines disposed in the peripheral area becomes longer and longer, and the resistance-capacitance load (RC load) is large, resulting in many The multiple common signals received by a common electrode cannot all have ideal values.
本發明提供一種畫素陣列基板,性能佳。The invention provides a pixel array substrate with good performance.
本發明的畫素陣列基板,包括基底、多個畫素結構、多個共用電極、多個驅動元件、多個開關元件、至少一主要訊號線、主要控制線、多條連接線及至少一輔助訊號線。基底具有主動區、第一周邊區及第二周邊區,其中第一周邊區及第二周邊區設置於主動區的相對兩側。多個畫素結構設置於基底的主動區上。多個共用電極重疊於多個畫素結構。多個共用電極排列成多個共用電極列及多個共用電極行,每一共用電極行的多個共用電極在第一方向上排列,每一共用電極列的多個共用電極在第二方向上排列,且第一方向與第二方向交錯。多個驅動元件設置於基底的第一周邊區上,其中多個驅動元件包括在第一方向上依序排列的第1驅動元件至第n個驅動元件,且n為大於或等於2的正整數。多個開關元件設置於基底的第二周邊區上,其中每一開關元件具有第一端、第二端及控制端。至少一主要訊號線設置於基底的第二周邊區上,其中多個開關元件的多個第一端電性連接至至少一主要訊號線,且至少一主要訊號線電性連接至第1個驅動元件及第n個驅動元件。主要控制線設置於基底的第二周邊區上,其中多個開關元件的多個控制端電性連接至主要控制線,且主要控制線電性連接至第1個驅動元件及第n個驅動元件。多條連接線電性連接至多個驅動元件,其中每一連接線電性連接至多個開關元件之一者的第二端及多個共用電極的一者。至少一輔助訊號線電性連接至多個驅動元件的至少一者及至少一主要訊號線。特別是,在畫素陣列基板的俯視圖中,至少一輔助訊號線位於多個共用電極行之間。The pixel array substrate of the present invention includes a substrate, a plurality of pixel structures, a plurality of common electrodes, a plurality of driving elements, a plurality of switching elements, at least one main signal line, a main control line, a plurality of connection lines and at least one auxiliary signal line. The base has an active area, a first peripheral area and a second peripheral area, wherein the first peripheral area and the second peripheral area are disposed on opposite sides of the active area. Multiple pixel structures are disposed on the active area of the base. Multiple common electrodes overlap multiple pixel structures. A plurality of common electrodes are arranged into a plurality of common electrode columns and a plurality of common electrode rows, a plurality of common electrodes of each common electrode row are arranged in a first direction, and a plurality of common electrodes of each common electrode row are arranged in a second direction arranged, and the first direction and the second direction are staggered. A plurality of driving elements are disposed on the first peripheral area of the substrate, wherein the plurality of driving elements include the first driving element to the nth driving element arranged in sequence in the first direction, and n is a positive integer greater than or equal to 2 . A plurality of switching elements are disposed on the second peripheral area of the base, and each switching element has a first terminal, a second terminal and a control terminal. At least one main signal line is disposed on the second peripheral area of the substrate, wherein the plurality of first ends of the plurality of switching elements are electrically connected to the at least one main signal line, and the at least one main signal line is electrically connected to the first driver element and the nth drive element. The main control line is disposed on the second peripheral area of the substrate, wherein the plurality of control ends of the plurality of switching elements are electrically connected to the main control line, and the main control line is electrically connected to the first driving element and the nth driving element . A plurality of connection lines are electrically connected to a plurality of driving elements, wherein each connection line is electrically connected to a second terminal of one of the plurality of switching elements and one of the plurality of common electrodes. At least one auxiliary signal line is electrically connected to at least one of the driving elements and at least one main signal line. Especially, in the top view of the pixel array substrate, at least one auxiliary signal line is located between the plurality of common electrode rows.
在本發明的一實施例中,上述的多個共用電極列在第一方向上依序排列,而包括多個奇數共用電極列及多個偶數共用電極列;多條連接線包括多條第一連接線及多條第二連接線,多條第一連接線電性連接至多個奇數共用電極列,多條第二連接線電性連接至多個偶數共用電極列;多個開關元件包括多個第一開關元件及多個第二開關元件,多個第一開關元件的多個第二端電性連接至多條第一連接線,多個第二開關元件的多個第二端電性連接至多條第二連接線;至少一主要訊號線包括第一主要訊號線及第二主要訊號線,多個第一開關元件的多個第一端電性連接至第一主要訊號線,多個第二開關元件的多個第一端電性連接至第二主要訊號線;至少一輔助訊號線包括第一輔助訊號線,第一輔助訊號線電性連接至多個驅動元件的至少一者及第一主要訊號線,其中在畫素陣列基板的俯視圖中,第一輔助訊號線位於多個共用電極行的相鄰兩者之間。In an embodiment of the present invention, the above-mentioned multiple common electrode columns are arranged sequentially in the first direction, and include multiple odd-numbered common electrode columns and multiple even-numbered common electrode columns; the multiple connecting lines include multiple first Connecting wires and a plurality of second connecting wires, the plurality of first connecting wires are electrically connected to a plurality of odd-numbered common electrode rows, and the plurality of second connecting wires are electrically connected to a plurality of even-numbered common electrode rows; the plurality of switching elements include a plurality of second A switch element and a plurality of second switch elements, the plurality of second ends of the plurality of first switch elements are electrically connected to the plurality of first connection lines, and the plurality of second ends of the plurality of second switch elements are electrically connected to the plurality of wires The second connection line; at least one main signal line includes a first main signal line and a second main signal line, a plurality of first ends of a plurality of first switching elements are electrically connected to the first main signal line, a plurality of second switches A plurality of first ends of the components are electrically connected to the second main signal line; at least one auxiliary signal line includes a first auxiliary signal line, and the first auxiliary signal line is electrically connected to at least one of the plurality of driving elements and the first main signal line lines, wherein in the top view of the pixel array substrate, the first auxiliary signal lines are located between adjacent two of the plurality of common electrode rows.
在本發明的一實施例中,上述的至少一輔助訊號線更包括第二輔助訊號線,第二輔助訊號線電性連接至多個驅動元件的至少一者及第二主要訊號線;在畫素陣列基板的俯視圖中,第二輔助訊號線位於多個共用電極行的相鄰兩者之間。In an embodiment of the present invention, the above-mentioned at least one auxiliary signal line further includes a second auxiliary signal line, and the second auxiliary signal line is electrically connected to at least one of the plurality of driving elements and the second main signal line; In the top view of the array substrate, the second auxiliary signal lines are located between adjacent two of the plurality of common electrode rows.
在本發明的一實施例中,上述的畫素陣列基板更包括至少一資料線,電性連接多個畫素結構,其中至少一輔助訊號線重疊於至少一資料線。In an embodiment of the present invention, the above-mentioned pixel array substrate further includes at least one data line electrically connected to a plurality of pixel structures, wherein at least one auxiliary signal line overlaps at least one data line.
在本發明的一實施例中,上述的畫素陣列基板更包括輔助控制線,電性連接至多個驅動元件的至少一者及主要控制線,其中在畫素陣列基板的俯視圖中,輔助控制線位於多個共用電極行的相鄰兩者之間。In an embodiment of the present invention, the above-mentioned pixel array substrate further includes an auxiliary control line electrically connected to at least one of the plurality of driving elements and the main control line, wherein in the top view of the pixel array substrate, the auxiliary control line It is located between adjacent two of the multiple common electrode rows.
在本發明的一實施例中,上述的畫素陣列基板更包括至少一資料線,電性連接多個畫素結構,其中輔助控制線重疊於至少一資料線。In an embodiment of the present invention, the above-mentioned pixel array substrate further includes at least one data line electrically connected to a plurality of pixel structures, wherein the auxiliary control line overlaps the at least one data line.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”可以是二元件間存在其它元件。It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about," "approximately," or "substantially" includes stated values and averages within acceptable deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the relative A specific amount of measurement-related error (ie, the limit of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and it is not necessary to use one standard deviation to apply to all properties .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.
圖1為本發明一實施例之畫素陣列基板的上視示意圖。FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention.
圖1示出基底110、共用電極120、驅動元件130、開關元件SW、主要訊號線141、輔助訊號線142、主要控制線151及輔助控制線152,而省略畫素陣列基板100的其它構件。1 shows a
圖2為本發明一實施例之畫素陣列基板的局部放大示意圖。圖2對應圖1的局部A。FIG. 2 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 corresponds to part A of FIG. 1 .
圖3為本發明一實施例之畫素陣列基板的局部放大示意圖。圖3對應圖1的局部B。FIG. 3 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 3 corresponds to part B of FIG. 1 .
請參照圖1,畫素陣列基板100包括基底110,具有主動區110a、第一周邊區110b及第二周邊區110c,其中第一周邊區110b及第二周邊區110c設置於主動區110a的相對兩側。舉例而言,在本實施例中,第二周邊區110c及第一周邊區110b可分別是設置在主動區110a之上下兩側的上邊框區及下邊框區,但本發明不以此為限。在本實施例中,基底110的材質可以是玻璃、石英、有機聚合物、或是不透光/反射材料(例如:晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料。1, the
請參照圖1及圖2,畫素陣列基板100還包括多個畫素結構PX,設置於基底110的主動區110a上。舉例而言,在本實施例中,每一畫素結構PX可包括薄膜電晶體T及畫素電極PE,其中薄膜電晶體T具有第一端Ta、第二端Tb及控制端Tc,而畫素電極PE電性連接至薄膜電晶體T的第二端Tb。在本實施例中,畫素陣列基板100還包括交錯設置的多條資料線DL及多條掃描線SL,其中資料線DL電性連接至畫素結構PX的薄膜電晶體T的第一端Ta,而掃描線SL電性連接至畫素結構PX的薄膜電晶體T的控制端Tc。Referring to FIG. 1 and FIG. 2 , the
請參照圖1及圖2,畫素陣列基板100還包括多個共用電極120,重疊於多個畫素結構PX。舉例而言,在本實施例中,每一共用電極120可重疊於多個畫素結構PX的畫素電極PE。在本實施例中,於顯示時間區間,共用電極120具有共用訊號,且共用電極120與畫素電極PE之間的電場用以驅動顯示介質(未繪示)。在本實施例中,於觸控時間區間,共用電極120是做為觸控感測電極使用,而具有觸控訊號。Referring to FIG. 1 and FIG. 2 , the
請參照圖1,多個共用電極120排列成多個共用電極列R及多個共用電極行C,每一共用電極行C的多個共用電極120在第一方向d1上排列,每一共用電極列R的多個共用電極120在第二方向d2上排列,且第一方向d1與第二方向d2交錯。舉例而言,在本實施例中,第一方向d1與第二方向d2可垂直,但本發明不以此為限。Please refer to FIG. 1, a plurality of
請參照圖1,畫素陣列基板100還包括多個驅動元件130,設置於基底110的第一周邊區110b上,其中多個驅動元件130包括在第一方向d1上依序排列的第1驅動元件130至第n個驅動元件130,且n為大於或等於2的正整數。舉例而言,在本實施例中,n=6。也就是說,在本實施例中,多個驅動元件130的數量為6個。然而,本發明不以此為限,在其它實施例中,多個驅動元件130的數量也可以是3個、4個、5個、7個或8個以上。此外,在本實施例中,驅動元件130例如是積體電路(integrated circuit;IC),但本發明不以此為限。Referring to FIG. 1, the
請參照圖1,畫素陣列基板100還包括多個開關元件SW,設置於基底110的第二周邊區110c上,其中每一開關元件SW具有第一端SWa、第二端SWb及控制端SWc。在本實施例中,開關元件SW例如是形成在基底110之第二周邊區110c上的薄膜電晶體,但本發明不以此為限。Please refer to FIG. 1, the
請參照圖1,畫素陣列基板100還包括主要訊號線141,設置於基底110的第二周邊區110c上,其中多個開關元件SW的多個第一端SWa電性連接至主要訊號線141,且主要訊號線141電性連接至第1個驅動元件130及第n個驅動元件130。舉例而言,在本實施例中,主要訊號線141的兩端是分別電性連接至位於基底110之最左側及最右側的兩個驅動元件130。Please refer to FIG. 1 , the
請參照圖1,畫素陣列基板100還包括主要控制線151,設置於基底110的第二周邊區110c上,其中多個開關元件SW的多個控制端SWc電性連接至主要控制線151,且主要控制線151電性連接至第1個驅動元件130及第n個驅動元件130。舉例而言,在本實施例中,主要控制線151的兩端是分別電性連接至位於基底110之最左側及最右側的兩個驅動元件130。Referring to FIG. 1, the
請參照圖1,畫素陣列基板100還包括多條連接線160,電性連接至多個驅動元件130,其中每一連接線160電性連接至多個開關元件SW之一者的第二端SWb及多個共用電極120的一者。Referring to FIG. 1, the
請參照圖1,值得注意的是,畫素陣列基板100還包括輔助訊號線142,電性連接至多個驅動元件130的至少一者及主要訊號線141。舉例而言,在本實施例中,輔助訊號線142的一端可電性連接至主要訊號線141,而輔助訊號線142的另一端可電性連接至左右相鄰的兩個驅動元件130。特別是,在畫素陣列基板100的俯視圖中,輔助訊號線142是位於相鄰的兩個共用電極行C之間。也就是說,輔助訊號線142是穿插在主動區110a中。透過輔助訊號線142的設置,共用訊號不但能透過設置於週邊的主要訊號線141提供至共用電極120,共用訊號還能透過穿插在主動區110a中的輔助訊號線142來提供。藉此,整個主動區110a上的多個共用電極120所獲得的共用訊號大小可較為接近理想值,而有助於提升包括畫素陣列基板100之顯示面板的電性。Referring to FIG. 1 , it is worth noting that the
請參照圖1及圖2,在本實施例中,輔助訊號線142可重疊於資料線DL。輔助訊號線142與資料線DL分別屬於不同的兩導電層,且輔助訊號線142與資料線DL之間設有至少一絕緣層(未繪示)。舉例而言,在本實施例中,掃描線SL、資料線DL及輔助訊號線142可分別屬於依序堆疊於基底110上的第一金屬層、第二金屬層及第三金屬層,但本發明不以此為限。Referring to FIG. 1 and FIG. 2 , in this embodiment, the
請參照圖1,在本實施例中,畫素陣列基板100還可選擇性地包括輔助控制線152,電性連接至多個驅動元件130的至少一者及主要控制線151。舉例而言,在本實施例中,輔助控制線152的一端可電性連接至主要控制線151,且輔助控制線152的另一端可電性連接至左右相鄰的兩個驅動元件130,但本發明不以此為限。Referring to FIG. 1 , in this embodiment, the
值得注意的是,在畫素陣列基板100的俯視圖中,輔助控制線152是位於相鄰的兩個共用電極行C之間。也就是說,輔助控制線152是穿插在主動區110a中。透過輔助控制線152的設置,閘極開啟訊號不僅能透過主要控制線151提供至位於基板110之第二周邊區110c的多個開關元件SW,閘極開啟訊號還能透過穿插在主動區110a中的輔助控制線152來提供。藉此,整個第二周邊區110c上的多個開關元件SW所獲得的閘極開啟訊號的大小可較為一致,而有助於提升包括畫素陣列基板100之顯示面板的電性。It should be noted that, in the top view of the
請參照圖1及圖3,在本實施例中,輔助控制線152可重疊於另一資料線DL。輔助控制線152與資料線DL分別屬於不同的兩導電層,且輔助控制線152與資料線DL之間設有至少一絕緣層(未繪示)。舉例而言,在本實施例中,掃描線SL、資料線DL及輔助控制線152可分別屬於依序堆疊於基底110上的第一金屬層、第二金屬層及第三金屬層,但本發明不以此為限。Referring to FIG. 1 and FIG. 3 , in this embodiment, the
請參照圖1,在本實施例中,多條輔助訊號線142及多條輔助控制線152可選擇性地在第二方向d2上交替排列。然而,本發明不限於此,在其它實施例中,輔助訊號線142及輔助控制線152穿插在主動區110a中的順序可視實際的需求做其它設計。此外,本發明也不限制畫素陣列基板100一定要包括輔助控制線152;在其它實施例中,也可不設置輔助控制線152,且可選擇性地將原本設有輔助控制線152的位置用以設置輔助訊號線142。Referring to FIG. 1 , in this embodiment, the plurality of
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重述。It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the aforementioned embodiments, and the following embodiments will not be repeated.
圖4為本發明另一實施例之畫素陣列基板的上視示意圖。圖4的畫素陣列基板100A與圖1的畫素陣列基板100類似,說明兩者的差異如下。FIG. 4 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. The
請參照圖4,多個共用電極列R在第一方向d1上依序排列,而包括多個奇數共用電極列Ro及多個偶數共用電極列RE。多條連接線160包括多條第一連接線161及多條第二連接線162,多條第一連接線161電性連接至多個奇數共用電極列Ro,而多條第二連接162線電性連接至多個偶數共用電極列RE。多個開關元件SW包括多個第一開關元件SW1及多個第二開關元件SW2,多個第一開關元件SW1的多個第二端SWb電性連接至多條第一連接線161,且多個第二開關元件SW2的多個第二端SWb電性連接至多條第二連接線162。Referring to FIG. 4 , a plurality of common electrode rows R are arranged sequentially in the first direction d1 , and include a plurality of odd common electrode rows Ro and a plurality of even common electrode rows RE. The plurality of
主要訊號線141包括第一主要訊號線141a及第二主要訊號線141b,其中多個第一開關元件SW1的多個第一端SWa電性連接至第一主要訊號線141a,多個第二開關元件SW2的多個第一端SWa電性連接至第二主要訊號線141b。輔助訊號線142包括第一輔助訊號線142a及第二輔助訊號線142b,其中第一輔助訊號線142a電性連接至多個驅動元件130的至少一者及第一主要訊號線141a,且第二輔助訊號線142b電性連接多個驅動元件130的至少一者及第二主要訊號線141b。The
值得注意的是,在畫素陣列基板100A的俯視圖中,第一輔助訊號線142a位於多個共用電極行C的相鄰兩者之間,且第二輔助訊號線142b位於多個共用電極行C的另外的相鄰兩者之間。圖4的畫素陣列基板100A與圖1的畫素陣列基板100具有類似的功效及優點,於此便不再重述。It should be noted that, in the top view of the
100、100A:畫素陣列基板
110:基底
110a:主動區
110b:第一周邊區
110c:第二周邊區
120:共用電極
130:驅動元件
141:主要訊號線
141a:第一主要訊號線
141b:第二主要訊號線
142:輔助訊號線
142a:第一輔助訊號線
142b:第二輔助訊號線
151:主要控制線
152:輔助控制線
160:連接線
161:第一連接線
162:第二連接線
A、B:局部
C:共用電極行
DL:資料線
d1:第一方向
d2:第二方向
PX:畫素結構
PE:畫素電極
R:共用電極列
R
o:奇數共用電極列
R
E:偶數共用電極列
SL:掃描線
SW:開關元件
SW1:第一開關元件
SW2:第二開關元件
SWa、Ta:第一端
SWb、Tb:第二端
SWc、Tc:控制端
T:薄膜電晶體
100, 100A: pixel array substrate 110:
圖1為本發明一實施例之畫素陣列基板的上視示意圖。 圖2為本發明一實施例之畫素陣列基板的局部放大示意圖。 圖3為本發明一實施例之畫素陣列基板的局部放大示意圖。 圖4為本發明另一實施例之畫素陣列基板的上視示意圖。 FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 3 is a partially enlarged schematic view of a pixel array substrate according to an embodiment of the present invention. FIG. 4 is a schematic top view of a pixel array substrate according to another embodiment of the present invention.
100:畫素陣列基板 100:Pixel array substrate
110:基底 110: base
110a:主動區 110a: active area
110b:第一周邊區 110b: The first peripheral area
110c:第二周邊區 110c: the second peripheral area
120:共用電極 120: common electrode
130:驅動元件 130: drive element
141:主要訊號線 141: Main signal line
142:輔助訊號線 142: Auxiliary signal line
151:主要控制線 151: Main control line
152:輔助控制線 152: Auxiliary control line
160:連接線 160: connecting line
A、B:局部 A, B: Partial
C:共用電極行 C: common electrode row
d1:第一方向 d1: the first direction
d2:第二方向 d2: second direction
R:共用電極列 R: common electrode row
SW:開關元件 SW: switching element
SWa:第一端 SWa: first end
SWb:第二端 SWb: second terminal
SWc:控制端 SWc: control terminal
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