CN215183964U - Pixel array substrate - Google Patents

Pixel array substrate Download PDF

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Publication number
CN215183964U
CN215183964U CN202121488355.1U CN202121488355U CN215183964U CN 215183964 U CN215183964 U CN 215183964U CN 202121488355 U CN202121488355 U CN 202121488355U CN 215183964 U CN215183964 U CN 215183964U
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Prior art keywords
pixel
array substrate
common electrode
pixel array
shielding pattern
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CN202121488355.1U
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Chinese (zh)
Inventor
李珉泽
郑圣谚
陈品妏
锺岳宏
徐雅玲
廖烝贤
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AU Optronics Corp
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AU Optronics Corp
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Priority claimed from TW110103827A external-priority patent/TWI757081B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A pixel array substrate comprises a plurality of pixel structures, a plurality of data lines, a plurality of gate lines and a plurality of first common electrodes. The data lines are arranged along a first direction and are electrically connected to the pixel structures. The gate lines are arranged along a second direction and are electrically connected to the pixel structures. Each first common electrode comprises a plurality of line segments arranged along a first direction, and two adjacent line segments are structurally separated to define a gap. In a top view of the pixel array substrate, a corresponding data line passes through the gap.

Description

Pixel array substrate
Technical Field
The utility model relates to a pixel array substrate.
Background
Generally, when the signal lines of the display panel are broken, the display panel is repaired to improve the yield. Specifically, the disconnected signal line and the repair line may be welded and/or the repair line may be cut to electrically connect the two portions of the disconnected signal line using the repair line.
The repair lines of the display panel can be divided into outer repair lines disposed in the peripheral region and inner repair lines disposed in the display region. The external repair line has a long length and a large load. When the external repair line is used to repair the signal line, the plurality of pixel structures electrically connected to the repaired signal line are prone to cause display image anomalies (e.g., bright lines and/or dark lines). Therefore, the external repair line is not suitable for a large-area and/or high-resolution display panel. Currently, the main stream of repair technology for large-area and/or high-resolution display panels is to use internal repair lines. However, the internal repair line is disposed in the display region, and the distance between the internal repair line and the signal line is short, which increases the load of the signal line, thereby reducing the charging efficiency of the pixel structure and being not favorable for the display quality.
SUMMERY OF THE UTILITY MODEL
The utility model provides a pixel array substrate, the performance is good.
The utility model discloses a pixel array substrate includes a plurality of pixel structures, many data lines, many gate lines and a plurality of first common electrode. Each pixel structure comprises a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The data lines are arranged along a first direction and are electrically connected to the thin film transistors of the pixel structures. The gate lines are arranged along a second direction and are electrically connected to the thin film transistors of the pixel structures, wherein the first direction and the second direction are staggered. Each first common electrode comprises a plurality of line segments arranged along a first direction, and two adjacent line segments are structurally separated to define a gap. In a top view of the pixel array substrate, a corresponding data line passes through the gap.
Particularly, the utility model provides a pixel array substrate, include:
a plurality of pixel structures, wherein each pixel structure comprises a thin film transistor and a pixel electrode electrically connected to the thin film transistor;
a plurality of data lines arranged along a first direction and electrically connected to the plurality of thin film transistors of the pixel structures;
a plurality of gate lines arranged along a second direction and electrically connected to the thin film transistors of the pixel structures, wherein the first direction and the second direction are staggered; and
a plurality of first common electrodes, wherein each first common electrode comprises a plurality of line segments arranged along the first direction; the adjacent two of the line segments are separated on the structure so as to define a gap; in a top view of the pixel array substrate, a corresponding data line passes through the gap.
Preferably, the pixel array substrate further includes:
a plurality of second common electrodes, wherein the pixel structures are arranged in a plurality of pixel rows, the pixel structures of each pixel row are arranged along the first direction, and each second common electrode is partially overlapped with the pixel electrodes of the pixel structures of a corresponding pixel row;
in a top view of the pixel array substrate, each of the first common electrodes is disposed between a corresponding gate line and a corresponding and second common electrode.
Preferably, each pixel structure further comprises a connection pattern electrically connecting the thin film transistor and the pixel electrode; the line segments of each first common electrode comprise: the pixel structure comprises a plurality of first line segments and a plurality of second line segments, wherein each first line segment is arranged with at least one data line in a staggered mode, and each second line segment is arranged with the connecting pattern of a corresponding pixel structure in a staggered mode and is not overlapped with the data lines.
Preferably, the first line segments and the second line segments of the first common electrodes are alternately arranged in the first direction and the second direction.
Preferably, the pixel array substrate further includes:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
in a top view of the pixel array substrate, a line segment of a first common electrode and another data line have a first intersection, and the first intersection overlaps an opening of the transparent shielding pattern.
Preferably, the pixel array substrate further includes:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
the line segment of the first common electrode and a third common electrode have a second intersection, and the second intersection is overlapped with the opening of the transparent shielding pattern.
Preferably, the pixel array substrate further includes:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
wherein, a line segment of a first common electrode and another data line have a first welding position; in a top view of the pixel array substrate, the first welding portion overlaps an opening of the transparent shielding pattern.
Preferably, the pixel array substrate further includes:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
the line segment of the first common electrode and a third common electrode have a second welding point, and the second welding point is overlapped with the opening of the transparent shielding pattern.
Preferably, the third common electrode has a first disconnection point; in a top view of the pixel array substrate, the first disconnection portion overlaps the opening of the transparent shielding pattern.
Preferably, the opening of the transparent shielding pattern has a recess portion overlapping the first break.
Preferably, the pixel array substrate further includes:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
in a top view of the pixel array substrate, a line segment of a first common electrode and a transfer line have a third intersection, and the third intersection overlaps an opening of the transparent shielding pattern.
Preferably, the pixel array substrate further includes:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
in a top view of the pixel array substrate, the line segment of the first common electrode and a third common electrode have a fourth intersection, and the fourth intersection overlaps the opening of the transparent shielding pattern.
Preferably, the pixel array substrate further includes:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
wherein, a line segment of a first common electrode and a transfer line have a third welding part; in a top view of the pixel array substrate, the third welding portion overlaps an opening of the transparent shielding pattern.
Preferably, the pixel array substrate further includes:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
the line segment of the first common electrode and a third common electrode have a fourth welding point, and the fourth welding point is overlapped with the opening of the transparent shielding pattern.
Preferably, the third common electrode has a second disconnection point; in a top view of the pixel array substrate, the second break overlaps the opening of the transparent shielding pattern.
Preferably, the opening of the transparent shielding pattern has a recess portion overlapping the second break.
Drawings
Fig. 1 is a schematic top view of a pixel array substrate 10 according to an embodiment of the present invention.
Fig. 2 is a schematic top view of a region R of the pixel array substrate 10 according to an embodiment of the present invention.
Fig. 3 is an enlarged schematic view of a part r of the pixel array substrate 10 according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a pixel array substrate 10 according to an embodiment of the invention.
Fig. 5 is a schematic top view of a pixel array substrate 10' according to an embodiment of the present invention.
Description of reference numerals:
10. 10': pixel array substrate
110: substrate
120: a first metal layer
122: a first common electrode
122a, 122b-1, 122 b-2: line segment
122 g: gap
124: a second common electrode
130: gate insulating layer
140: second metal layer
142: connection pattern
144: third common electrode
144a, 144b, 144c, 144 d: at one place
144m, and a weight ratio of: main part
150: first passivation layer
160: color filter pattern
170: second passivation layer
180: a first transparent conductive layer
182: transparent shielding pattern
182 a: opening of the container
182a-1, 182 a-2: concave part
190: planarization layer
130a, 192: contact window
200: second transparent conductive layer
202: pixel electrode
Cspx: line of pixels
C1: first break of
C2: second break point
C3: third break away
C4: fourth point of disconnection
C5: fifth break point
C6: sixth breaking point
C7: seventh breaking point
C8: eighth break point
DL: data line
DLo: at the point of disconnection
DL-1: the first part
DL-2: the second part
DM 1: first diamond lattice pattern
DM 2: second diamond lattice pattern
GL: gate line
gl: adapter cable
gla: main part
And glo: at the point of disconnection
gl-1: the first part
gl-2: the second part
R: region(s)
r: local part
Rspx: pixel column
SDL: data signal
Sgl: gate drive signal
SPX: pixel structure
T: thin film transistor
Ta: source electrode
Tb: drain electrode
Tc: grid electrode
Td: semiconductor pattern
W1: first welding joint
W2: second welding joint
W3: third weld
W4: fourth weld
W5: fifth weld joint
W6: sixth weld
W7: seventh weld joint
W8: eighth fusion joint
X1: first intersection
X2: second intersection
X3: third intersection
X4: fourth intersection
x: a first direction
y: second direction
I-I': cutting line
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" or "coupled" may mean that there are additional elements between the elements.
As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately" or "substantially" may be selected based on optical properties, etch properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic top view of a pixel array substrate 10 according to an embodiment of the present invention.
Fig. 2 is a schematic top view of a region R of the pixel array substrate 10 according to an embodiment of the present invention. Fig. 2 corresponds to region R of fig. 1.
Fig. 1 schematically illustrates the base 110, the gate lines GL and the transfer lines GL, and other components of the pixel array substrate 10 of fig. 2 are omitted.
Fig. 3 is an enlarged schematic view of a part r of the pixel array substrate 10 according to an embodiment of the present invention. Fig. 3 corresponds to the section r of fig. 2.
Fig. 4 is a schematic cross-sectional view of a pixel array substrate 10 according to an embodiment of the invention. Fig. 4 corresponds to the section line I-I' of fig. 3.
Referring to fig. 1, 2, 3 and 4, the pixel array substrate 10 includes a substrate 110. The base 110 is mainly used for carrying a plurality of components of the pixel array substrate 10. For example, in the present embodiment, the material of the substrate 110 may be glass. However, the invention is not limited thereto, and according to other embodiments, the material of the substrate 110 may be quartz, organic polymer, opaque/reflective material (e.g., wafer, ceramic, etc.), or other applicable materials.
Referring to fig. 1, 2 and 3, the pixel array substrate 10 includes a plurality of data lines DL and a plurality of gate lines GL. A plurality of data lines DL and a plurality of gate lines GL are disposed on the substrate 110. The plurality of data lines DL are arranged along a first direction x, and the plurality of gate lines GL are arranged along a second direction y, wherein the first direction x and the second direction y are staggered. For example, in the present embodiment, the first direction x and the second direction y may be perpendicular, but the present invention is not limited thereto.
Referring to fig. 3 and 4, the data line DL and the gate line GL belong to different film layers. For example, in the present embodiment, the gate line GL may selectively belong to the first metal layer 120, and the data line DL may selectively belong to the second metal layer 140, but the invention is not limited thereto.
In view of conductivity, in the present embodiment, a metal material is used for the data line DL and the gate line GL. However, the present invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the data lines DL and the gate lines GL, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.
Referring to fig. 2 and 3, the pixel array substrate 10 includes a plurality of pixel structures SPX disposed on a substrate 110. Each pixel structure SPX includes a thin film transistor T and a pixel electrode 202 electrically connected to the thin film transistor T. The data lines DL are electrically connected to the thin film transistors T of the pixel structures SPX. The gate lines GL are electrically connected to the thin film transistors T of the pixel structures SPX.
Referring to fig. 3 and 4, in the present embodiment, each thin film transistor T has a source electrode Ta, a drain electrode Tb, a gate electrode Tc and a semiconductor pattern Td, a gate insulating layer 130 is interposed between the gate electrode Tc and the semiconductor pattern Td, the source electrode Ta and the drain electrode Tb are respectively electrically connected to two different regions of the semiconductor pattern Td, the source electrode Ta is electrically connected to a corresponding data line DL, and the gate electrode Tc is electrically connected to a corresponding gate line GL. For example, in the present embodiment, the gate Tc may selectively belong to the first metal layer 120, and the source Ta and the drain Tb may selectively belong to the second metal layer 140, but the invention is not limited thereto.
The drain Tb of each tft T is electrically connected to a corresponding pixel electrode 202. For example, in the present embodiment, each pixel structure SPX further includes a connection pattern 142 disposed on the gate insulating layer 130 and electrically connected to the drain electrode Tb of the thin film transistor T; the pixel array substrate 10 may further include a first passivation layer 150 disposed on the second metal layer 140, a color filter pattern 160 disposed on the first passivation layer 150, a second passivation layer 170 disposed on the color filter pattern 160, and a planarization layer 190 disposed on the second passivation layer 170; the pixel electrode 202 may be disposed on the planarization layer 190 and electrically connected to the connection pattern 142 through the contact window 192 of the planarization layer 190, wherein the connection pattern 142 electrically connects the pixel electrode 202 and the drain Tb of the thin film transistor T.
In the present embodiment, the pixel electrode 202 may belong to the second transparent conductive layer 200. The material of the second transparent conductive layer 200 may include metal oxides, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the foregoing, but the invention is not limited thereto.
Referring to fig. 2, the pixel array substrate 10 further includes a plurality of first common electrodes 122. Each first common electrode 122 includes a plurality of line segments 122a, 122b arranged along the first direction x; adjacent ones of the plurality of line segments 122a, 122b are structurally separated to define a gap 122 g; in the top view of the pixel array substrate 10, a corresponding data line DL passes through the gap 122 g.
In other words, each first common electrode 122 includes a plurality of line segments 122a, 122b disconnected from each other; in a top view of the pixel array substrate 10, each data line DL of the pixel array substrate 10 at least passes through the break (i.e., the gap 122g) of at least one first common electrode 122 without overlapping each first common electrode 122. Therefore, the parasitic capacitance between the data line DL and the first common electrode 122 is small, so that the load of the data line DL is reduced, and the charging efficiency of the pixel structure SPX is improved, and the performance of the pixel array substrate 10 is improved.
In the present embodiment, the line segments 122a and 122b of each first common electrode 122 include a plurality of first line segments 122a and a plurality of second line segments 122b, each first line segment 122a is disposed in a staggered manner with respect to at least one data line DL, and each second line segment 122b is disposed in a staggered manner with respect to the connection pattern 142 of a corresponding pixel structure SPX and is not overlapped with the data line DL.
Under normal conditions (or, under the condition that the first common electrode 122 is not used for repairing the pixel array substrate 10), the first line segments 122a and the second line segments 122b of each first common electrode 122 are respectively electrically connected to a corresponding second common electrode 124; the plurality of first line segments 122a of the first common electrode 122, the plurality of second line segments 122b of the first common electrode 122 and the second common electrode 124 have the same reference potential; however, the present invention is not limited thereto.
For example, in the present embodiment, each first line segment 122a may be disposed to intersect with three data lines DL, and two second line segments 122b-1 and 122b-2, which intersect with two connection patterns 142 respectively, may be disposed between two left and right adjacent first line segments 122 a. However, the present invention is not limited thereto, and the number of the data lines DL interlaced with the same first segment 122a and/or the number of the second segments 122b located between two adjacent first segments 122a may be changed according to actual requirements.
It should be noted that, in the present embodiment, the second line segment 122b is disposed such that the parasitic capacitances between the plurality of pixel structures SPX respectively corresponding to the first line segment 122a and the second line segment 122b and the first common electrode 122 are relatively close. In this way, the pixel structures SPX respectively corresponding to the first line segment 122a and the second line segment 122b can have similar optical performance, so as to improve the overall display quality of the display panel (not shown) having the pixel array substrate 10.
Referring to fig. 2, in the present embodiment, a plurality of first line segments 122a and a plurality of second line segments 122b-1 of a plurality of first common electrodes 122 respectively corresponding to a plurality of pixel rows Rspx may be alternately arranged in the first direction x and the second direction y. In other words, the connection lines of the pixel structures SPX respectively corresponding to the first line segments 122a may substantially form the first rhomboid DM1, and the connection lines of the pixel structures SPX respectively corresponding to the second line segments 122b-1 may substantially form the second rhomboid DM 2. Therefore, even if the optical performances (e.g., brightness) of the pixel structures SPX respectively corresponding to the first line segments 122a and the second line segments 122b are slightly different, the overall display quality of the display panel having the pixel array substrate 10 is not easily affected excessively.
For example, in the present embodiment, the first common electrode 122 may selectively belong to the first metal layer 120, but the invention is not limited thereto. In view of conductivity, in the present embodiment, a metal material is used for the first common electrode 122. However, the present invention is not limited thereto, and according to other embodiments, the first common electrode 122 may also use other conductive materials, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.
Referring to fig. 2, in the present embodiment, the pixel array substrate 10 further includes a plurality of second common electrodes 124; the plurality of pixel structures SPX are arranged in a plurality of pixel columns Rspx, and the plurality of pixel structures SPX of each pixel column Rspx are arranged along the first direction x; each of the second common electrodes 124 partially overlaps with the pixel electrodes 202 of the pixel structures SPX of a corresponding one of the pixel columns Rspx. Each of the second common electrodes 124 and the plurality of pixel electrodes 202 form a storage capacitor of the plurality of pixel structures SPX. In a top view of the pixel array substrate 10, each of the first common electrodes 122 may be disposed between a corresponding one of the gate lines GL and a corresponding one of the second common electrodes 124.
For example, in the present embodiment, the second common electrode 124 may selectively belong to the first metal layer 120, but the invention is not limited thereto. In view of conductivity, in the present embodiment, a metal material is used for the second common electrode 124. However, the present invention is not limited thereto, and according to other embodiments, the second common electrode 124 may also use other conductive materials, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.
Referring to fig. 1 and fig. 2, in the present embodiment, the pixel array substrate 10 further includes a plurality of patch cords gl. The plurality of patch cords gl are disposed on the substrate 110 and arranged in the first direction x. The plurality of patch lines GL arranged in the first direction x are electrically connected to the plurality of gate lines GL arranged in the second direction y, respectively. Referring to fig. 2, in the present embodiment, the plurality of pixel structures SPX are arranged in a plurality of pixel rows Cspx, and the plurality of pixel structures SPX of each pixel row Cspx are arranged along the second direction y; in the top view of the pixel array substrate 10, each of the plurality of transfer lines gl is disposed between two adjacent pixel rows Cspx.
Referring to fig. 1, fig. 2 and fig. 3, for example, in the present embodiment, the plurality of gate lines GL may selectively belong to the first metal layer 120, the main portion gla of the plurality of patch lines GL may selectively belong to the second metal layer 140, the gate insulating layer 130 (shown in fig. 4) is disposed between the first metal layer 120 and the second metal layer 140, the gate insulating layer 130 has a plurality of contact windows 130a (shown in fig. 1), and the main portion gla of the plurality of patch lines GL may be electrically connected to the plurality of gate lines GL through the plurality of contact windows 130a of the gate insulating layer 130, but the present invention is not limited thereto.
Referring to fig. 2, fig. 3 and fig. 4, in the present embodiment, the pixel array substrate 10 may further optionally include a transparent shielding pattern 182. The transparent shielding pattern 182 is disposed between at least one of the layers to which the switching line gl belongs and the layer to which the pixel electrode 202 belongs to shield the interference of the gate driving signal of the switching line gl to the potential of the pixel electrode 202. For example, in the present embodiment, the first transparent conductive layer 180 of the transparent shielding pattern 182 may be disposed between the second metal layer 140 of the main portion gla of the patch cord gl and the second transparent conductive layer 200 of the pixel electrode 202.
Referring to fig. 4, in the embodiment, specifically, the transparent shielding pattern 182 may be selectively disposed on the second passivation layer 170 and between the planarization layer 190 and the second passivation layer 170, but the invention is not limited thereto. According to other embodiments, the transparent shielding pattern 182 may be disposed at other positions between the patch line gl and the pixel electrode 202; alternatively, the provision of the transparent shield pattern 182 may also be omitted.
Referring to fig. 2, in the present embodiment, in the top view of the pixel array substrate 10, the line segment 122a of the first common electrode 122 and the data line DL have a first intersection X1, and the first intersection X1 may overlap the opening 182a of the transparent shielding pattern 182. In other words, the entities of the transparent shielding pattern 182 are spaced apart at the first intersection X1 of the first common electrode 122 and the data line DL and do not overlap with the first intersection X1.
Referring to fig. 2, in the present embodiment, the pixel array substrate 10 further includes a plurality of third common electrodes 144 arranged along the first direction x; in the top view of the pixel array substrate 10, each third common electrode 144 is disposed between two adjacent pixel rows Cspx.
For example, in the present embodiment, the third common electrode 144 has a main portion 144m spanning the plurality of gate lines GL, and the main portion 144m of the third common electrode 144 may belong to the second metal layer 140, but the invention is not limited thereto. In view of conductivity, in the present embodiment, a metal material is used for the third common electrode 144. However, the present invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the third common electrode 144, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.
In the present embodiment, the line segment 122a of the first common electrode 122 and the third common electrode 144 have a second intersection X2, and the second intersection X2 overlaps the opening 182a of the transparent shielding pattern 182. In other words, the entities of the transparent shielding pattern 182 are spaced apart at the second intersections X2 of the first and third common electrodes 122 and 144 and do not overlap with the second intersections X2.
In the embodiment, in the top view of the pixel array substrate 10, a segment 122a of the first common electrode 122 and a transfer line gl have a third intersection X3, and the third intersection X3 overlaps the opening 182a of the transparent shielding pattern 182. In other words, the entity of the transparent shielding pattern 182 is spaced apart from the third intersection X3 of the first common electrode 122 and the patch cord gl and does not overlap with the third intersection X3.
In the embodiment, in the top view of the pixel array substrate 10, the line segment 122a of the first common electrode 122 and the other third common electrode 144 have a fourth intersection X4, and the fourth intersection X4 overlaps the opening 182a of the transparent shielding pattern 182. In other words, the entities of the transparent shielding pattern 182 are spaced apart from the fourth intersection X4 of the other third common electrode 144 at the line segment 122a of the first common electrode 122 and do not overlap with the fourth intersection X4.
It is noted that when the signal line (e.g., the data line DL and/or the transfer line gl) is disconnected, the first common electrode 122 disposed horizontally and the third common electrode 144 disposed vertically can be used for repairing, as illustrated in fig. 5.
Fig. 5 is a schematic top view of a pixel array substrate 10' according to an embodiment of the present invention. The pixel array substrate 10' of fig. 5 is similar to the pixel array substrate 10 of fig. 2, and therefore the same or similar elements are denoted by the same or similar reference numerals, and the differences between the two will be described below, and the same or similar elements will be referred to the above description, and will not be repeated here. In addition, fig. 5 omits the illustration of the pixel electrode 202 for clarity of illustration.
The pixel array substrate 10 of fig. 2 is a normal (or, non-repaired) pixel array substrate, and the pixel array substrate 10' of fig. 5 is a repaired pixel array substrate.
Referring to fig. 5, in the present embodiment, a data line DL has a break DLo, and the break DLo divides the data line DL into a first portion DL-1 and a second portion DL-2, wherein the first portion DL-1 of the data line DL is located above the break DLo, and the second portion DL-2 of the data line DL is located below the break DLo.
In order to repair the broken data line DL, in the present embodiment, the first portion DL-1 of the data line DL and a segment 122a of the first common electrode 122 interleaved therewith may be welded, such that the segment 122a of the first common electrode 122 and the first portion DL-1 of the data line DL have the first welding point W1 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the first welding point W1 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In the present embodiment, the segment 122a of the first common electrode 122 crossing the first portion DL-1 of the data line DL and a portion 144a of a third common electrode 144 may be welded together, so that the segment 122a of the first common electrode 122 and the third common electrode 144 have a second welding point W2 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the second welding point W2 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In the present embodiment, another portion 144b of the third common electrode 144 and a line segment 122a of another first common electrode 122 interlaced with the another portion 144b of the third common electrode 144 may be further welded, so that the line segment 122a of another first common electrode 122 and the another portion 144b of the third common electrode 144 have a fifth welding point W5 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the fifth welding point W5 may overlap another opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In the present embodiment, the second portion DL-2 of the data line DL and a segment 122a of another first common electrode 122 interleaved therewith may be further fusion-bonded, so that the segment 122a of another first common electrode 122 and the second portion DL-2 of the data line DL have a sixth fusion-bonded portion W6 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the sixth welding point W6 may overlap another opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In this embodiment, a part of the third common electrode 144 having the second fusion point W2 and the fifth fusion point W5 may be disconnected from the other part of the third common electrode 144. Specifically, in the present embodiment, the third common electrode 144 may have a first breaking point C1 located above the second welding point W2 and a third breaking point C3 located below the fifth welding point W5. In the present embodiment, the opening 182a of the transparent shielding pattern 182 may have a recess 182a-1 overlapping the first cut-off C1, but the invention is not limited thereto.
In addition, in the present embodiment, a line segment 122a having the first welding point W1 and the second welding point W2 and the adjacent second common electrode 124 may have a fourth disconnection C4, and another line segment 122a having the fifth welding point W5 and the sixth welding point W6 and the adjacent second common electrode 124 may have a fifth disconnection C5.
After the first fusion point W1, the second fusion point W2, the fifth fusion point W6, the sixth fusion point W6, the first break point C1, the third break point C3, the fourth break point C4 and the fifth break point C5 are formed, the data signal S of the first portion DL-1 of the data line DL is formedDLThe first welding point W1, the line segment 122a of one first common electrode 122 crossing the first portion DL-1 of the data line DL, the second welding point W2, the portion of the third common electrode 144 cut by the first break C1 and the third break C3, the fifth welding point W5, the line segment 122a of the other first common electrode 122 crossing the second portion DL-2 of the data line DL, and the sixth welding point W6 are transferred to the second portion DL-2 of the data line DL, so that the pixel array substrate 10' can operate normally.
Referring to fig. 5, in the present embodiment, a transfer line gl has a break portion glo, and the break portion glo divides the transfer line gl into a first portion gl-1 and a second portion gl-2, wherein the first portion gl-1 of the transfer line gl is located above the break portion glo, and the second portion gl-2 of the transfer line gl is located below the break portion glo.
In the present embodiment, the first portion gl-1 of the transfer line gl and a segment 122a of a first common electrode 122 interleaved therewith can be fusion-bonded, such that the segment 122a of the first common electrode 122 and the first portion gl-1 of the transfer line gl have the third fusion W3 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the third welding point W3 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In the present embodiment, the line segment 122a of the first common electrode 122 and one point 144c of another third common electrode 144, which are interlaced with the first portion gl-1 of the patch cord gl, can be further welded, so that the line segment 122a of the first common electrode 122 and the third common electrode 144 have a fourth welding point W4 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the fourth welding point W4 may overlap the opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In the present embodiment, the other portion 144d of the other third common electrode 144 and the line segment 122a of the other first common electrode 122 interlaced with the other portion 144d of the other third common electrode 144 can be welded together, so that the line segment 122a of the other first common electrode 122 and the other portion 144d of the third common electrode 144 have a seventh welding point W7 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the seventh welding point W7 may overlap another opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In the present embodiment, the second portion gl-2 of the patch cord gl and the line segment 122a of the other first common electrode 122 interlaced therewith can be further welded, so that the line segment 122a of the other first common electrode 122 and the second portion gl-2 of the patch cord gl have an eighth welding point W8 and are electrically connected to each other. In the embodiment, in the top view of the pixel array substrate 10', the eighth fusion point W8 may overlap another opening 182a of the transparent shielding pattern 182, but the invention is not limited thereto.
In this embodiment, a part of the third common electrode 144 having the fourth and seventh welding points W4 and W7 may be disconnected from the other part of the third common electrode 144. Specifically, the third common electrode 144 may have a second cut-off C2 located above the fourth welding point W4 and a sixth cut-off C6 located below the seventh welding point W7. In the present embodiment, the opening 182a of the transparent shielding pattern 182 may have a recess 182a-2 overlapping the second cut-off C2, but the invention is not limited thereto.
In addition, in the present embodiment, the first line segment 122a of the first common electrode 122 having the third welding point W3 and the fourth welding point W4 and the adjacent second common electrode 124 may have a seventh disconnection C7, and the first line segment 122a of the first common electrode 122 having the seventh welding point W7 and the eighth welding point W8 and the adjacent second common electrode 124 may have an eighth disconnection C8.
After the third welding point W3, the fourth welding point W4, the seventh welding point W7, the eighth welding point W8, the second breaking point C2, the sixth breaking point C6, the seventh breaking point C7 and the eighth breaking point C8 are formed, the gate driving signal S of the first portion gl-1 of the line gl is transferredglThe line segment 122a of the first common electrode 122 crossing the first portion gl-1 of the patch line gl, the fourth welding point W4, the portion of the third common electrode 144 cut by the second break C2 and the sixth break C6, the seventh welding point W7, the line segment 122a of the other first common electrode 122 crossing the second portion gl-2 of the patch line gl, and the eighth welding point W8 are transmitted to the second portion gl-2 of the patch line gl through the third welding point W3, so that the pixel array substrate 10' can operate normally.

Claims (16)

1. A pixel array substrate, comprising:
a plurality of pixel structures, wherein each pixel structure comprises a thin film transistor and a pixel electrode electrically connected to the thin film transistor;
a plurality of data lines arranged along a first direction and electrically connected to the plurality of thin film transistors of the pixel structures;
a plurality of gate lines arranged along a second direction and electrically connected to the thin film transistors of the pixel structures, wherein the first direction and the second direction are staggered; and
a plurality of first common electrodes, wherein each first common electrode comprises a plurality of line segments arranged along the first direction; the adjacent two of the line segments are separated on the structure so as to define a gap; in a top view of the pixel array substrate, a corresponding data line passes through the gap.
2. The pixel array substrate of claim 1, further comprising:
a plurality of second common electrodes, wherein the pixel structures are arranged in a plurality of pixel rows, the pixel structures of each pixel row are arranged along the first direction, and each second common electrode is partially overlapped with the pixel electrodes of the pixel structures of a corresponding pixel row;
in a top view of the pixel array substrate, each of the first common electrodes is disposed between a corresponding gate line and a corresponding and second common electrode.
3. The pixel array substrate of claim 1, wherein each of the pixel structures further comprises a connection pattern electrically connecting the thin film transistor and the pixel electrode; the line segments of each first common electrode comprise: the pixel structure comprises a plurality of first line segments and a plurality of second line segments, wherein each first line segment is arranged with at least one data line in a staggered mode, and each second line segment is arranged with the connecting pattern of a corresponding pixel structure in a staggered mode and is not overlapped with the data lines.
4. The pixel array substrate of claim 3, wherein the first line segments and the second line segments of the first common electrodes are alternately arranged in the first direction and the second direction.
5. The pixel array substrate of claim 1, further comprising:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
in a top view of the pixel array substrate, a line segment of a first common electrode and another data line have a first intersection, and the first intersection overlaps an opening of the transparent shielding pattern.
6. The pixel array substrate of claim 5, further comprising:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
the line segment of the first common electrode and a third common electrode have a second intersection, and the second intersection is overlapped with the opening of the transparent shielding pattern.
7. The pixel array substrate of claim 1, further comprising:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
wherein, a line segment of a first common electrode and another data line have a first welding position; in a top view of the pixel array substrate, the first welding portion overlaps an opening of the transparent shielding pattern.
8. The pixel array substrate of claim 7, further comprising:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
the line segment of the first common electrode and a third common electrode have a second welding point, and the second welding point is overlapped with the opening of the transparent shielding pattern.
9. The pixel array substrate of claim 8, wherein the third common electrode has a first break; in a top view of the pixel array substrate, the first disconnection portion overlaps the opening of the transparent shielding pattern.
10. The pixel array substrate of claim 9, wherein the opening of the transparent shielding pattern has a recess overlapping the first break.
11. The pixel array substrate of claim 1, further comprising:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
in a top view of the pixel array substrate, a line segment of a first common electrode and a transfer line have a third intersection, and the third intersection overlaps an opening of the transparent shielding pattern.
12. The pixel array substrate of claim 11, further comprising:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
in a top view of the pixel array substrate, the line segment of the first common electrode and a third common electrode have a fourth intersection, and the fourth intersection overlaps the opening of the transparent shielding pattern.
13. The pixel array substrate of claim 1, further comprising:
a plurality of transfer lines arranged along the first direction and electrically connected to the gate lines; and
a transparent shielding pattern arranged between at least one film layer to which the transfer lines belong and one film layer to which a plurality of pixel electrodes of the pixel structures belong;
wherein, a line segment of a first common electrode and a transfer line have a third welding part; in a top view of the pixel array substrate, the third welding portion overlaps an opening of the transparent shielding pattern.
14. The pixel array substrate of claim 13, further comprising:
a plurality of third common electrodes arranged along the first direction, wherein the pixel structures are arranged into a plurality of pixel rows, and the pixel structures of each pixel row are arranged along the second direction; in a top view of the pixel array substrate, each third common electrode is arranged between two adjacent pixel rows;
the line segment of the first common electrode and a third common electrode have a fourth welding point, and the fourth welding point is overlapped with the opening of the transparent shielding pattern.
15. The pixel array substrate of claim 14, wherein the third common electrode has a second break; in a top view of the pixel array substrate, the second break overlaps the opening of the transparent shielding pattern.
16. The pixel array substrate of claim 15, wherein the opening of the transparent shielding pattern has a recess overlapping the second break.
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