TWI756416B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI756416B
TWI756416B TW107114489A TW107114489A TWI756416B TW I756416 B TWI756416 B TW I756416B TW 107114489 A TW107114489 A TW 107114489A TW 107114489 A TW107114489 A TW 107114489A TW I756416 B TWI756416 B TW I756416B
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Taiwan
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dielectric layer
layer
forming
gate
recess
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TW107114489A
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TW201839822A (zh
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唐邦泰
黃泰鈞
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例揭露半導體裝置與其形成方法。方法包括形成閘極堆疊於半導體結構上。使閘極堆疊凹陷以形成第一凹陷。沿著第一凹陷的底部與側壁形成第一介電層，且第一介電層具有第一蝕刻速率。形成第二介電層於第一介電層上，第二介電層具有第二蝕刻速率，且第一蝕刻速率大於第二蝕刻速率。形成第三介電層於第二介電層上。改變第三介電層的一部份之蝕刻速率。使第一介電層、第二介電層、與第三介電層凹陷，以形成第二凹陷。形成蓋層於第二凹陷中。

Description

半導體裝置與其形成方法
本發明實施例關於半導體裝置的形成方法，更特別關於形成接點以用於多閘極場效電晶體裝置的方法。
金氧半場效電晶體廣泛應用於積體電路。為增加積體電路中金氧半場效電晶體的密度，需大幅減少金氧半場效電晶體的物理尺寸如閘極長度。金氧半場效電晶體的閘極長度短，可能導致不想要的短通道效應，比如關閉狀態的漏電流過高與汲極誘發的通道能障降低過多。
為抑制短閘極長度的電晶體其短通道效效，可採用多閘極場效電晶體結構。多閘極場效電晶體與平片裝置結構相較，其閘極對通道電位具有較佳的靜電控制。多閘極場效電晶體的例子包含雙閘極電晶體或三閘極電晶體。雙閘極電晶體又稱作雙閘極鰭狀場效電晶體。三閘極電晶體可稱作三閘極鰭狀場效電晶體，或簡稱為鰭狀場效電晶體。雙閘極或三閘極的裝置採用的通道類似鰭狀物。開啟狀態或飽合驅動電流在鰭狀物中流通，以達單位腳距(footprint)或佈局區域的高電流密度。
其他多閘極場效電晶體包含Π閘極、Ω閘極、圍繞閘極、或全包覆式閘極結構，其可進一步改善閘極的靜電控制。為繞閘極電晶體的通道與奈米線類似，而奈米線的方向可 水平或垂直。對水平奈米線電晶體而言，可垂直堆疊多個水平方向的奈米線通道。
本發明一實施例提供之半導體裝置的形成方法，包括：形成閘極堆疊於半導體結構上；使閘極堆疊凹陷以形成第一凹陷；沿著第一凹陷的底部與側壁形成第一介電層，且第一介電層具有第一蝕刻速率；形成第二介電層於第一介電層上，第二介電層具有第二蝕刻速率，且第一蝕刻速率大於第二蝕刻速率；形成第三介電層於第二介電層上；改變第三介電層的一部份之蝕刻速率；使第一介電層、第二介電層、與第三介電層凹陷，以形成第二凹陷；以及形成蓋層於第二凹陷中。
B、C:剖線
Hfin:高度
T1、T2、T3:厚度
Ttotal:總厚度
102:基板
104:鰭狀物
106:淺溝槽隔離區
108:溝槽
110:襯墊層
112:虛置閘極介電層
114:虛置閘極
116:虛置閘極堆疊
117:虛置閘極遮罩
118:側壁間隔物
120:第一源極/汲極區
122:第二源極/汲極區
124:通道區
230:襯墊介電膜
332:層間介電層
502:閘極介電層
504:閘極
602:閘極遮罩
604、912:蓋層
606:區域
702:開口
802:接點
902、908:凹陷
904:多層膜
9041:第一膜
9042:第二膜
9043:第三膜
906:縫隙
910:氮摻雜
912d:摻雜硼的部份
1000:方法
1001、1003、1005、1007、1009、1011、1013、1015:步驟
第1A-8A、1B-8B、1C-8C、9A-9I圖係一些實施例中，半導體裝置於製程中的中間製程階段的多種圖式。
第10圖係一些實施例中，形成裝置的方法其流程圖。
下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一結構於第二結構上的敘述包含兩者直接接觸，或兩者之間隔有其他額外結構而非直接接觸。此外，本發明實施例之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
下述實施例關於形成接點以用於多閘極場效電晶體裝置的方法，包含形成自對準接點的方法。此處所述的實施例通常可用於雙閘極或三閘極的鰭狀場效電晶體、圍繞閘極或全包覆式閘極電晶體、及/或奈米線電晶體。
為說明目的，圖式與下述內容為單一鰭狀物與三個閘極。然而值得注意的是，其他實施例可採用更多鰭狀物，並可採用更多或更少閘極。此外，可採用其他結構。舉例來說，相鄰鰭狀物的磊晶區可合併形成單一的較大源極/汲極區。
第1A至8C圖係一些實施例中，形成鰭狀場效電晶體與個別接點的中間階段其透視圖與剖視圖。下述內容包含實施例的變化。在多種圖式與例示性的實施例中，類似標號將用於標示類似元件。在第1A至8C圖中，末尾為「A」的圖式(如第1A圖、第2A圖、等等)為透視圖，末尾為「B」的圖式(如第1B圖、第2B圖、等等)為沿著末尾為「A」的個別圖式中剖線B的剖視圖，而末尾為「C」的圖式(如第1C圖、第2C圖、等等)為沿著末尾為「A」的個別圖式中剖線C的剖視圖。
如第1A至1C圖所示，基板102具有一或多個鰭狀物，比如圖式中的鰭狀物104。應理解單一鰭狀物僅用以說明， 而其他實施例可包含任何數目的鰭狀物。基板102可為半導體基板如基體半導體、絕緣層上半導體基板、或類似物，其可摻雜p型或n型摻質或未摻雜。基板102可為晶圓如矽晶圓。一般而言，絕緣層上矽基板包含半導體材料層形成於絕緣層上。舉例來說，絕緣層可為埋置氧化物層、氧化矽層、或類似物。絕緣層可形成於基板上，而基板通常為矽基板或玻璃基板。此外亦可採用其他基板如多層基板或組成漸變基板。在一些實施例中，基板102的半導體材料可包含矽、鍺、半導體化合物(如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、半導體合金(如矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、或上述之組合。
基板102可包含多種摻雜區，端視設計需求(如p型基板或n型基板)而定。在一些實施例中，摻雜區可摻雜p型或n型摻質。舉例來說，摻雜區可摻雜p型摻質如硼或二氟化硼、n型摻質如磷或砷、及/或上述之組合。摻雜區可設置為用於n型鰭狀場效電晶體，或另外設置為用於p型鰭狀場效電晶體。
基板102亦可包含積體電路裝置(未圖示)。本技術領域中具有通常知識者應理解，多種積體電路裝置如電晶體、二極體、電容、電阻、類似物、或上述之組合可形成於基板102之中及/或之上，以符合鰭狀場效電晶體裝置其設計的結構與功能需求。積體電路裝置的形成方法可採用任何合適方法。
舉例來說，鰭狀物104的形成方法可採用圖案化製程以形成溝槽108，而鰭狀物104形成於相鄰的溝槽108之間。在一些實施例中，採用光微影技術圖案化遮罩層(未圖示)。一 般而言，沉積光阻材料(未圖示)於遮罩層上。以通過圖案化光罩的能量照射(曝光)光阻材料，以誘發光阻材料其曝光至能量的部份中產生反應。顯影光阻材料，以移除光阻材料的部份。保留的光阻材料可保護下方的材料免於後續製程步驟(如蝕刻)影響。如之後的詳述內容，鰭狀物104可用於形成多閘極場效電晶體。在一例中，通道側壁表面的結晶方向可為(110)，而通道上表面的結晶方向可為(001)。通道側壁可為其他結晶方向，比如(551)。通道側壁與通道上表面可具有其他結晶方向。
在一些實施例中，鰭狀物104可由任何合適方法形成。舉例來說，鰭狀物104的形成方法可採用一或多道光微影製程，比如雙重圖案化製程或多重圖案化製程。一般而言，雙重或多重圖案化製程結合光微影與自對準製程，其形成的圖案間距可小於單一直接圖案化製程所形成的圖案間距。舉例來說，一實施例形成犧牲層於基板102上，並以光微影製程圖案化犧牲層。接著採用自對準製程，沿著圖案化的犧牲層的側邊形成間隔物。接著移除犧牲層並保留間隔物(或芯)，且可再採用間隔物(或芯)圖案化基板102以形成鰭狀物104。
沿著溝槽108中的鰭狀物104其側壁形成隔離區(如淺溝槽隔離區106)。在形成淺溝槽隔離區106之前，形成一或多個襯墊層(統稱為襯墊層110)於基板102及鰭狀物104的側壁上。在一些實施例中，襯墊層110為單層結構，且其厚度介於約10Å至約50Å之間。在其他實施例中，襯墊層110為雙層結構，其具有第一襯墊子層與第二襯墊子層。在一些實施例中，第一襯墊子層包含氧化矽，且其厚度介於約5Å至約20Å之間； 而第二襯墊子層包含氮化矽，且其厚度介於約5Å至約30Å之間。襯墊層110的沉積方法可為一或多道製程如物理氣相沉積、化學氣相沉積、或原子層沉積，但亦可採用任何可接受的製程。在一些實施例中，溝槽108自鰭狀物104的頂部向下的深度介於約500Å至約3000Å之間。此外可採用其他材料、其他尺寸、及/或其他製程。
淺溝槽隔離區106之組成可為合適的介電材料，比如氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃、低介電常數的介電物如摻雜碳的氧化物、極低介電常數的介電物如多孔且摻雜碳的氧化矽、聚合物如聚醯亞胺、上述之組合、或類似物。在一些實施例中，淺溝槽隔離區106的形成製程可為化學氣相沉積、可流動的化學氣相沉積、或旋轉塗佈玻璃製程，但亦可採用任何可接受的製程。接著可移除沿伸至鰭狀物104的上表面之淺溝槽隔離區106的部份，並可移除鰭狀物104之上表面上的襯墊層110的部份，且移除方法可採用蝕刻製程、化學機械研磨、或類似方法。
在一些實施例中，使淺溝槽隔離區106與襯墊層110凹陷以露出鰭狀物104的側壁，如第1A至1C圖所示。在一些實施例中，使淺溝槽隔離區106與襯墊層110凹陷的方法可採用一或多個選擇性蝕刻製程，其以鰭狀物104作為蝕刻遮罩。舉例來說，可採用單一蝕刻製程使淺溝槽隔離區106與襯墊層110凹陷。在其他實施例中，可採用多重蝕刻製程使淺溝槽隔離區106與襯墊層110凹陷。舉例來說，可採用第一蝕刻製程以及襯墊層110作為蝕刻遮罩使淺溝槽隔離區106凹陷，接著採用 第二蝕刻製程使襯墊層110凹陷。在淺溝槽隔離區106包含氧化矽的實施例中，蝕刻製程可為乾蝕刻、化學蝕刻、或濕蝕刻等製程。舉例來說，化學蝕刻可採用含氟化學劑如稀氫氟酸。在使淺溝槽隔離區106與襯墊層110凹陷之後，鰭狀物104其高於淺溝槽隔離區106的高度Hfin可大於或等於30nm，比如大於或等於50nm。應理解的是，後續製程可調整鰭狀物高度。
如第1A至1C圖所示的一些實施例，形成虛置閘極介電層112與虛置閘極114於露出的鰭狀物104上。虛置閘極介電層112與虛置閘極114之後可用於定義及形成源極/汲極區。在一些實施例中，虛置閘極介電層112與虛置閘極114的形成方法為沉積虛置閘極介電層(未圖示)於露出的鰭狀物104上，沉積虛置閘極層(未圖示)於虛置閘極介電層上，並圖案化虛置閘極介電層與虛置閘極層。虛置閘極介電層的形成方法可為熱氧化、原子層沉積、化學氣相沉積、濺鍍、或本技術領域中已知用於形成虛置閘極介電層的任何其他方法。在一些實施例中，虛置閘極介電層的組成可與淺溝槽隔離區106的材料相同。在其他實施例中，虛置閘極介電層112的組成可為一或多層的合適介電材料，比如氧化矽、氮化矽、氮碳化矽、氮氧化矽、氮氫化矽、低介電常數介電物(如摻雜碳的氧化物)、極低介電常數的介電物(如多孔且摻雜碳的氧化矽)、聚合物如聚醯亞胺、類似物、或上述之組合。在一些實施例中，虛置閘極介電層112包含的介電材料具有高介電常數(比如大於3.9)。高介電常數的材料可包含金屬氧化物如氧化鉿、氧化鉿鋯、氧化鉿矽、氧化鉿鈦、氧化鉿鋁、類似物、上述之組合、或上述之多層結構。
接著形成虛置閘極層於虛置閘極介電層上。在一些實施例中，虛置閘極層為導電材料，其可為非晶矽、多晶矽、非晶鍺、多晶鍺、非晶矽鍺、多晶矽鍺、金屬氮化物、金屬矽化物、金屬氧化物、或金屬。在一實施例中，虛置閘極層的沉積方法可為物理氣相沉積、化學氣相沉積、濺鍍沉積、或本技術領域中已知用於沉積導電材料的其他技術。此外可採用其他材料(導電或非導電)。虛置閘極層通常具有不平坦的上表面，且在沉積虛置閘極層後可平坦化虛置閘極層。
硬遮罩如虛置閘極遮罩117可形成於虛置閘極層上以利圖案化。虛置閘極遮罩117包含一或多個遮罩層，且可用於圖案化虛置閘極介電層與虛置閘極層以形成虛置閘極介電層112與虛置閘極114，如第1A至1C圖所示。虛置閘極遮罩117可包含一或多層。在一些實施例中，虛置閘極遮罩117之組成可為氧化矽、氮碳化矽、氮氧化矽、氮化矽、氧化鋁、氮氫化矽、或其他合適材料。
在一些實施例中，虛置閘極遮罩117包含第一硬遮罩層與第二硬遮罩層。第一硬遮罩層可為氧化物層(如氧化矽)，而第二硬遮罩層可為氮化物(如氮化矽)。第一硬遮罩層與第二硬遮罩層的沉積製程可為原子層沉積、化學氣相沉積、物理氣相沉積、或旋轉塗佈玻璃製程，但亦可採用任何可接受的製程。第一硬遮罩層的厚度可介於約10Å至約250Å之間，而第二硬遮罩層的厚度可介於約150Å至約850Å之間。虛置閘極114與虛置閘極介電層112一起形成虛置閘極堆疊116。虛置閘極介電層112的厚度可介於約30Å至約50Å之間。虛置閘極114的厚 度可介於約40nm至約60nm之間。
在一些實施例中，側壁間隔物118沿著虛置閘極堆疊116的側壁形成。側壁間隔物118的形成方法可為沉積間隔物層(未圖示)於虛置閘極堆疊116、鰭狀物104、與淺溝槽隔離區106上，接著圖案化間隔物層。在一些實施例中，間隔物層的組成為氮化矽，且可為單層結構。在其他實施例中，間隔物層可為多層的複合結構。舉例來說，間隔物層可包含氧化矽層，以及氧化矽層上的氮化矽層。此外亦可採用其他材料如氧化矽、氮碳化矽、氮氧化矽、氮化矽、氮氫化矽、氮碳氧化矽、其他低介電常數的材料、或上述之組合。在一些實施例中，間隔物層的厚度可介於約20Å至約30Å之間。
可圖案化間隔物層以形成側壁間隔物118，且圖案化方法可採用非等向蝕刻製程，以移除裝置的水平部份上與沿著虛置閘極堆疊116其側壁的間隔物層。由於裝置的水平部份上與沿著鰭狀物104的側壁之間隔物層厚度不同，將沿著虛置閘極堆疊116的側壁保留間隔物層，並露出源極/汲極區中的鰭狀物104，如第1A與1C圖所示。
值得注意的是，圖式中的三個閘極僅用於說明目的。在一些實施例中，中間的閘極可為主動閘極，而兩側的閘極可為用於圖案化目的之虛置(非主動)閘極。在其他實施例中，所有的閘極均可為主動閘極。
如第1A至1C圖所示的一些實施例，第一源極/汲極區120與第二源極/汲極區122沿著虛置閘極堆疊116其兩側，形成於鰭狀物104的露出部份上。在一些實施例中，可使鰭狀物 104凹陷，並磊晶形成第一源極/汲極區120與第二源極/汲極區122於凹陷的鰭狀物104其露出的部份上。綜上所述，第一源極/汲極區120與第二源極/汲極區122亦可分別稱作第一磊晶源極/汲極區與第二磊晶源極/汲極區。在源極/汲極區中採用磊晶成長的材料，可讓第一源極/汲極區120施加應力至通道區124。用於第一源極/汲極區120與第二源極/汲極區122的材料可不同，以分別用於n型鰭狀場效電晶體與p型鰭狀場效電晶體。用於n型鰭狀場效電晶體的材料可施加拉伸應力至通道區124，而用於p型鰭狀場效電晶體的另一材料可施加壓縮應力至通道區124。舉例來說，一些實施例中的通道區124其組成為矽時，磷化矽或碳化矽可用於形成n型鰭狀場效電晶體的源極/汲極區，而矽鍺或鍺可用於形成p型鰭狀場效電晶體的源極/汲極區。此外亦可採用其他材料。
在n型裝置與p型裝置採用不同材料的實施例中，需要在形成磊晶材料於一裝置(如p型裝置)上時，遮罩另一裝置(如n型裝置)。之後再重複類似製程於另一裝置。經由佈植合適摻質的佈植製程，或在成長材料時原位摻雜材料，可摻雜第一源極/汲極區120與第二源極/汲極區122。舉例來說，對p型通道的多閘極場效電晶體而言，當通道為矽或矽鍺(Si1-xGex)時，摻雜的磊晶膜可為摻雜硼的矽鍺(Si1-yGey)，其中y大於或等於x以誘發縱向的壓縮應力於通道中，以增進電洞移動率。對n型通道的多閘極場效電晶體而言，當通道為矽時，摻雜的磊晶膜可為摻雜磷的矽(Si：P)或摻雜磷的碳矽(Si1-zCz：P)。當通道為半導體化合物如砷化銦鎵(InmGa1-mAs)時，摻雜的磊晶膜可為 InnGa1-nAs，其中n小於或等於m。
如第2A至2C圖所示，沉積襯墊介電膜230於第一源極/汲極區120、第二源極/汲極區122、側壁間隔物118、與虛置閘極堆疊116的頂部上。在一些實施例中，襯墊介電膜230包含氧化矽、氮碳化矽、氮氧化矽、氮化矽、或氮氫化矽，但可採用其他合適的介電材料。襯墊介電膜230亦可包含多個層狀物，其包含上述材料的組合。襯墊介電膜230的沉積方法可為一或多道製程，比如物理氣相沉積、化學氣相沉積、或原子層沉積，但亦可採用任何可接受的製程。此外可採用其他材料及/或製程。在一些實施例中，襯墊介電膜230的厚度小於或等於約5nm，比如小於或等於約3nm。此外可採用其他厚度。
如第3A至3C圖所示的一些實施例，形成層間介電層332於襯墊介電膜230上。在一實施例中，層間介電層332為可流動的化學氣相沉積形成的可流動膜。在一些實施例中，層間介電層332之組成為介電材料如磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物，且其沉積方法可為任何合適方法如化學氣相沉積、電漿增強化學氣相沉積、旋轉塗佈玻璃製程、上述之組合、或類似方法。在一些實施例中，襯墊介電膜230在圖案化層間介電層332以形成開口(用於後續形成的接點)時，可作為停止層。綜上所述，用於襯墊介電膜230的材料其蝕刻速率，應低於層間介電層332的材料其蝕刻速率。接著可採用蝕刻製程、化學機械研磨、或類似方法，移除延伸至鰭狀物104之頂部上的襯墊介電膜230與層間介電層332的部份。在一些實施例中，這些製程可部份地 或完全地移除虛置閘極遮罩117。
如第4A至4C圖所示的一些實施例，移除虛置閘極114與虛置閘極介電層112。移除製程可包含一或多道蝕刻製程。舉例來說，當虛置閘極114包含多晶矽而虛置閘極介電層112包含氧化矽時，移除製程可包含選擇性蝕刻，其採用乾蝕刻或濕蝕刻。在採用乾蝕刻的例子中，製程氣體可包含四氟化碳、氟仿、三氟化氮、六氟化硫、溴、溴化氫、氯、或上述之組合。視情況可採用稀釋氣體如氮、氧、或氬。在採用濕蝕刻的例子中，化學劑可包含氫氧化銨：雙氧水：水、氫氧化胺、氫氧化鉀、硝酸：氟化銨：水、及/或類似物。虛置閘極介電層112的移除方法可採用濕蝕刻製程，比如稀氫氟酸。此外可採用其他製程與材料。
如第5A至5C圖所示的一些實施例，形成閘極介電層502於鰭狀物104的通道區124上。在一實施例中，閘極介電層502包含一或多層的高介電常數介電層(其介電常數大於3.9)。舉例來說，一或多個閘極介電層可包含一或多層鉿、鋁、鋯、或上述之組合的金屬氧化物或矽酸鹽。其他合適材料包含鑭、鎂、鋇、鈦、鉛、或鋯的金屬氧化物、合金的氧化物、或上述之組合。例示性材料包含氧化鎂、氧化鋇鈦、氧化鋇鍶鈦、氧化鉛鈦、氧化鉛鋯鈦、氮碳化矽、氮氧化矽、氮化矽、氧化鋁、氧化鑭、氧化鉭、氧化釔、氧化鉿、氧化鋯、氮氧化鉿矽、氧化釔鍺、氧化釔矽、氧化鑭鋁、或類似物。閘極介電層502的形成方法包含分子束沉積、原子層沉積、物理氣相沉積、或類似方法。在一實施例中，閘極介電層502的厚度可介於約3Å 至約30Å之間。
在一些實施例中，在形成閘極介電層502之前，可形成界面層(未圖示)於通道區上，再形成閘極介電層502於界面層上。就面層有助於緩衝後續形成的高介電常數的介電層以及下方的半導體材料。在一些實施例中，界面層為化學氧化矽，其形成方法可為化學反應。舉例來說，化學氧化物的形成方法可採用水與臭氧、氫氧化銨與雙氧水與水、或其他方法。其他實施例可採用不同材料或製程以用於界面層。在一實施例中，界面層的厚度可介於約30Å至約50Å之間。
如第5A至5C圖所示，形成閘極504於閘極介電層502上。閘極504可包含金屬如鎢、銅、鈦、銀、鋁、鈦鋁、氮化鈦鋁、碳化鉭、氮碳化鉭、氮化鉭矽、錳、鈷、鈀、鎳、錸、銥、釕、鉑、鋯、或上述之組合。在一些實施例中，閘極504可包含金屬如氮化鈦、氮化鎢、氮化鉭、或釕。此外，可採用金屬合金如鈦鋁、釕鉭、釕鋯、鉑鈦、鈷鎳、或鎳鉭，及/或金屬氮化物如氮化鎢、氮化鈦、氮化鉬、氮化鉭、或氮化鉭矽。在一些實施例中，閘極504的厚度可介於約5nm至約100nm之間。閘極504的形成方法可採用合適製程如原子層沉積、化學氣相沉積、物理氣相沉積、電鍍、或上述之組合。可進行平坦化製程如化學機械研磨，以移除多餘材料。
如第6A至6C圖所示的一些實施例，使閘極504與閘極介電層502凹陷，並形成閘極遮罩602與蓋層604於閘極504與閘極介電層502的保留部份上。在一些實施例中，使閘極504凹陷的方法採用氯與氧與三氯化硼的乾蝕刻製程。
在使閘極504與閘極介電層502凹陷之後，可形成閘極遮罩602於凹陷中，以在後續製程中保護閘極504與閘極介電層502。在一些實施例中，閘極遮罩602可包含氧化矽、氮碳化矽、氮氧化矽、氮化矽、氧化鋁、氧化鑭、氮氫化矽、上述之組合、或類似物，但亦可採用其他合適的介電膜。舉例來說，閘極遮罩602的形成方法可採用原子層沉積、化學氣相沉積、物理氣相沉積、旋轉塗佈、或類似方法。此外可採用其他合適製程。蓋層604可包含非晶矽、碳氧化矽、碳化矽、氮化矽、上述之組合、或類似物。舉例來說，蓋層604的形成方法可採用原子層沉積、化學氣相沉積、物理氣相沉積、或類似方法。在一實施例中，閘極遮罩602的厚度可介於約30nm至約60nm之間。在一實施例中，蓋層604的厚度可介於約10nm至約30nm之間。
可進行平坦化製程如化學機械研磨，以移除超出凹陷的多餘材料。此外，平坦化製程露出層間介電層332的上表面。用於形成閘極遮罩602與蓋層604的製程流程，其細節將進一步搭配第9A至9I圖說明如下。
第7A至7C圖所示的一些實施例，進一步形成開口702於層間介電層332中。如下詳述，接點形成於開口702中。在一些實施例中，可採用合適的光微影與蝕刻製程圖案化層間介電層332，以形成開口702。開口702露出第一源極/汲極區120與第二源極/汲極區122。
如第8A至8C圖所示的一些實施例，形成接點802於開口702(見第7A至7C圖)中。接點802可包含單層或多層結 構。舉例來說，一些實施例的接點802包含襯墊層如擴散阻障層、黏著層、或類似物，且接點填充物形成於開口702中的接點襯墊層上。接點襯墊層可包含鈦、氮化鈦、鉭、氮化鉭、或類似物，其形成方法可為原子層沉積、化學氣相沉積、物理氣相沉積、或類似方法。接點填充物的形成方法可為沉積導電材料如一或多層的鎳、鉭、氮化鉭、鎢、鈷、鈦、氮化鈦、鋁、銅、金、上述之合金、上述之組合、或類似物。可進行平坦化製程如化學機械研磨，以自層間介電層332的上表面移除多餘材料。
此外可進行其他製程。舉例來說，一些實施例可形成金屬矽化物於第一源極/汲極區120與第二源極/汲極區122上。在一些實施例中，在第7A至7C所述之製程形成開口702之後形成金屬矽化物。金屬矽化物的形成製程，可形成金屬矽化物於摻雜的源極/汲極區之頂部上，以降低摻雜的源極/汲極區與之後形成的接點金屬之間的接點電阻。在一實施例中，金屬矽化物的形成製程包括沉積金屬膜於源極/汲極區的頂部上，進行熱處理以形成金屬矽化物於源極/汲極區與金屬膜之間的界面，並進行蝕刻製程以移除多餘的未反應金屬。金屬矽化物可包含鈦矽化物、鎳矽化物、鈷矽化物、鎳鈷矽化物、鉭矽化物、上述之組合、或類似物。
第9A至9I圖係一些實施例中，閘極遮罩602與蓋層604的製程其中間階段的多種圖式。第9A至9I圖係第6C圖所示的區域606其放大剖視圖。如第9A圖所示的區域606，係使閘極504與閘極介電層502凹陷後，形成凹陷902的結構。
如第9B圖所示，形成多層膜904於凹陷902(見第9A圖)中。在一些實施例中，多層膜904包含第一膜9041、第一膜9041上的第二膜9042、與第二膜上的第三膜9043。在一些實施例中，第一膜9041的厚度T1介於約10nm至約13nm之間。在一些實施例中，第一膜9041的厚度T1可為多層膜904的總厚度Ttotal之約40%。在一些實施例中，第二膜9042的厚度T2介於約10nm至約13nm之間。在一些實施例中，，第二膜9042的厚度T2可為多層膜904的總厚度Ttotal之約40%。在一些實施例中，第三膜9043的厚度T3介於約3nm至約5nm之間。在一些實施例中，第三膜9043的厚度T3可為多層膜904的總厚度Ttotal之約20%。在一些實施例中，多層膜904可包含氧化矽、氮碳化矽、氮氧化矽、氮化矽、氧化鋁、氧化鑭、氮氫化矽、上述之組合、或類似物。舉例來說，多層膜904的形成方法可採用原子層沉積、化學氣相沉積、物理氣相沉積、旋轉塗佈、上述之組合、或類似方法。在一些實施例中，多層膜904順應性地沉積於凹陷中。在沉積製程後，多層膜904包含縫隙906，其中多層膜904沉積於凹陷902的側壁與底部上的層狀物，將在凹陷902的內部中接觸。如下詳述，多層膜904經凹陷後形成閘極遮罩602於凹陷902中。
在一些實施例中，當第一膜9041包含氮化矽時，順應性沉積第一膜9041的方法可採用原子層沉積，其前驅物氣體混合物包含氨與二氯矽烷。在沉積時亦可採用稀釋氣體如氫或氬。在一些實施例中，沉積製程可歷時約4000秒至約6000秒之間，其溫度可介於約450℃至約550℃之間，且其壓力可介於約1.5Torr至約3Torr之間。在一些實施例中，可改變前驅物氣體 的相對用量以調整第一膜9041的性質(如蝕刻速率)。在一些實施例中，藉由改變前驅物氣體的相對用量，可調整第一膜9041中的氯含量。在一些實施例中，增加第一膜9041中的氯含量，可增加第一膜9041的蝕刻速率。
在形成第一膜9041之後，沉積第二膜9042於第一膜9041上。在一些實施例中，當第二膜9042包含氮化矽時，順應性沉積第二膜9042的方法可採用原子層沉積，其前驅物氣體混合物包含氨與二氯矽烷。在沉積時亦可採用稀釋氣體如氫或氬。在一些實施例中，沉積製程可歷時約3000秒至約5000秒之間，其溫度可介於約450℃至約550℃之間，且其壓力可介於約1.5Torr至約3Torr之間。在一些實施例中，可改變前驅物氣體的相對用量以調整第二膜9042的性質(如蝕刻速率)。在一些實施例中，改變第二膜9042中的氯含量，可調整第二膜9042的蝕刻速率。在一些實施例中，可改變沉積時的前驅物氣體的相對用量以改變氯含量。在一些實施例中，第二膜9042的氯含量可介於約2wt%至約5wt%之間。在一些實施例中，第二膜9042的氯含量小於第一膜9041的氯含量。如此一來，對後續採用的蝕刻製程而言，第一膜9041的蝕刻速率可大於第二膜9042的蝕刻速率。綜上所述，第一膜9041亦可稱作軟膜，而第二膜9042亦可稱作硬膜。
在形成第二膜9042之後，沉積第三膜9043於第二膜9042上。在一些實施例中，當第三膜9043包含氮化矽時，順應性沉積第三膜9043的方法可採用原子層沉積，其前驅物氣體混合物包含氨與二氯矽烷。在沉積時亦可採用稀釋氣體如氫或 氬。在一些實施例中，沉積製程可歷時約2000秒至約3000秒之間，其溫度可介於約450℃至約550℃之間，且其壓力可介於約1.5Torr至約3Torr之間。
在沉積步驟之後，一些實施例將第三膜9043置入含二氯矽烷與氫氣的氣體混合物的環境中進行硬化。在硬化步驟中亦可採用稀釋氣體如氬。在一些實施例中，硬化步驟可歷時約200秒至約400秒之間，且其溫度可介於約450℃至約550℃之間。硬化步驟可改變第三膜9043的特性(如蝕刻速率)。在一些實施例中，硬化步驟可增加靠近縫隙906的第三膜9043其矽含量。藉由增加靠近縫隙906的第三膜9043其矽含量，對後續採用的蝕刻製程而言，可進低靠近縫隙906的第三膜9043其蝕刻速率。在一些實施例中，第三膜9043的矽含量可介於約40wt%至約50wt%之間。如下詳述，由於上述多層膜904具有不同蝕刻速率的層狀物，在蝕刻多層膜904之後的閘極遮罩602可具有實質上平坦的表面。
在其他實施例中，多層膜904的形成方法包括形成第一膜9041後硬化，並可省略第二膜9042與第三膜9043的形成步驟。在其他實施例中，多層膜904的形成方法可包括形成第一膜9041與第二膜9042後硬化，並可省略第三膜9043的形成步驟。在其他實施例中，多層膜904的形成方法可包含形成第一膜9041與第二膜9042，並可省略第三膜9043的形成步驟與硬化步驟。
如第9C圖所示，移除超出凹陷(見第9A圖)的多層膜904其多餘部份。在一些實施例中，層間介電層332的上表面 上的多層膜904其多餘部份的移除方法，可採用蝕刻製程、化學機械研磨、或類似方法。
如第9D圖所示，使多層膜904凹陷以形成閘極遮罩602與凹陷908。在一些實施例中，凹陷步驟可包含採用乾蝕刻或濕蝕刻選擇性地蝕刻多層膜904。在一些實施例中，當多層膜904包含氮化矽並採用乾蝕刻時，製程氣體可包含氟甲烷、氧、氬、或上述之組合。此外亦可採用其他製程。在一些實施例中，當多層膜904包含氮化矽時，對採用含氟甲烷、氧、氬、或上述之組合的製程氣體的蝕刻製程而言，第一膜9041的蝕刻速率高於第二膜9042的蝕刻速率。在一些實施例中，多層膜904包含氮化矽時，對採用含氟甲烷、氧、氬、或上述之組合的製程氣體的蝕刻製程而言，靠近縫隙906的第三膜9043的蝕刻速率降低。在凹陷步驟後，由於第一膜9041的蝕刻速率高於第二膜9042的蝕刻速率，凹陷908的側壁實質上可不殘留第一膜9041的材料，其於形成蓋層604(見第6A至6C圖)時可改善凹陷填充製程。此外，藉由降低靠近縫隙906的第三膜9043其蝕刻速率，可減少或避免不想要的縫隙開口。在一些實施例中，閘極遮罩602具有實質上齊平的上表面，因此凹陷908實質上為矩形。
如第9E圖所示，對凹陷908露出的側壁間隔物118進行氮摻雜910。在一些實施例中，氮摻雜910改變側壁間隔物118的性質如蝕刻速率。在一些實施例中，氮摻雜910降低側壁間隔物118其摻雜部份的蝕刻速率。在一些實施例中，側壁間隔物118其摻雜部份的氮含量可介於約10wt%至約20wt%之間。
如第9F圖所示，形成蓋層912於凹陷908中。在一 些實施例中，蓋層912可包含矽、碳化矽、旋轉塗佈碳、或類似物，且其形成方法可採用原子層沉積、化學氣相沉積、旋轉塗佈、或類似方法。在一些實施例中，進行硼摻雜於蓋層912的橫向部份以轉變其性質(如蝕刻速率)。在一些實施例中，蓋層912其摻雜硼的部份912d之蝕刻速率，低於蓋層912其未摻雜部份之蝕刻速率。在一些實施例中，蓋層912其摻雜硼的部份912d之硼含量可介於約10wt%至約20wt%之間。
如第9G圖所示，選擇性移除蓋層912的未摻雜部份。在一些實施例中，當蓋層912包含矽時，可採用氫氧化銨的濕蝕刻製程移除蓋層912的未摻雜部份。在選擇性移除之後，蓋層912其摻雜硼的部份912d保留於凹陷908中以及層間介電層332的上表面上。
如第9H圖所示，選擇性移除沿著凹陷908其側壁的側壁間隔物118。在一些實施例中，當側壁間隔物118包含氮化矽時，可採用磷酸的蝕刻製程移除側壁間隔物118。在一些實施例中，在選擇性移除之後，凹陷908中可露出襯墊介電膜230的部份。
如第9I圖所示，形成蓋層604於凹陷908中。蓋層604可包含非晶矽或類似物。舉例來說，蓋層604的形成方法可採用原子層沉積、化學氣相沉積、物理氣相沉積、或類似方法。可進行平坦化製程如化學機械研磨，以移除超出凹陷908的多餘材料。此外，平坦化製程自層間介電層332的上表面移除摻蓋層912其摻雜硼的部份912d，並露出層間介電層332的上表面。
第10圖係一些實施例中，形成裝置的方法1000其流程圖。方法1000的步驟1001形成閘極堆疊(如第5A至5C圖所示的閘極介電層502與閘極504)於半導體結構上，比如搭配第5A至5C圖說明的前述內容。在步驟1003中，使閘極堆疊凹陷以形成第一凹陷(如第9A圖所示的凹陷902)，比如搭配第9A圖說明的前述內容。在步驟1005中，沿著第一凹陷的底部與側壁形成第一介電層(如第9B圖所示的第一膜9041)，比如搭配第9B圖說明的前述內容。在步驟1007中，形成第二介電層(如第9B圖所示的第二膜9042)於第一介電層上，比如搭配第9B圖說明的前述內容。在步驟1009中，形成第三介電層(如第9B圖所示的第三膜9043)於第二介電層上，比如搭配第9B圖說明的前述內容。在步驟1011中，硬化第三介電層，比如搭配第9B圖說明的前述內容。在步驟1013中，使第一介電層、第二介電層、與第三介電層凹陷以形成第二凹陷(如第9D圖所示的凹陷908)，比如搭配第9C與9D圖說明的前述內容。在步驟1015中，形成蓋層(如第9I圖所示的蓋層604)於第二凹陷中，比如搭配第9E至9I圖說明的前述內容。在其他實施例中，可省略步驟1007、1009、及/或1011。
此處所述的多種實施例可在進行回蝕刻製程以形成閘極遮罩602時，避免縫隙開口、減少殘留物於側壁上、並改善凹陷輪廓。多種實施例在形成蓋層604時，可減少製程步驟並改善製程容忍度。
依據一實施例，半導體裝置的形成方法包括：形成閘極堆疊於半導體結構上；使閘極堆疊凹陷以形成第一凹 陷；沿著第一凹陷的底部與側壁形成第一介電層，且第一介電層具有第一蝕刻速率；形成第二介電層於第一介電層上，第二介電層具有第二蝕刻速率，且第一蝕刻速率大於第二蝕刻速率；形成第三介電層於第二介電層上；改變第三介電層的一部份之蝕刻速率；使第一介電層、第二介電層、與第三介電層凹陷，以形成第二凹陷；以及形成蓋層於第二凹陷中。在一實施例中，上述方法更包括沿著閘極堆疊的側壁形成間隔物。在一實施例中，使第一介電層、第二介電層、與第三介電層凹陷的步驟更包括露出間隔物的一部份。在一實施例中，上述方法更包括移除間隔物其露出的一部份。在一實施例中，改變第三介電層的一部份之蝕刻速率的步驟，包括硬化第三介電層的一部份，以降低第三介電層的一部份之蝕刻速率。在一實施例中，硬化步驟在含有二氯矽烷與氫的氣體混合物之環境下進行。在一實施例中，第二介電層的氯含量低於第一介電層的氯含量。
依據另一實施例，半導體裝置的形成方法包括：形成閘極堆疊於半導體結構上；形成間隔物於閘極堆疊的側壁上；蝕刻閘極堆疊以形成第一凹陷；順應性地沉積第一介電層於第一凹陷中，且第一介電層具有第一蝕刻速率；順應性地沉積第二介電層於第一介電層上，第二介電層具有第二蝕刻速率，且第一蝕刻速率大於第二蝕刻速率；順應性地沉積第三介電層於第二介電層上，且第三介電層具有第三蝕刻速率；硬化第三介電層，且第三介電層的硬化部份其蝕刻速率小於第三蝕刻速率；以及蝕刻第一介電層、第二介電層、與第三介電層，以形成第二凹陷，第二凹陷露出間隔物的一部份，且第一介電 層、第二介電層、與第三介電層的保留部份形成閘極遮罩。在一實施例中，上述方法在形成閘極遮罩之後，更包括蝕刻間隔物以移除間隔物的一部份。在一實施例中，上述方法在蝕刻間隔物之後，更包括形成蓋層於閘極遮罩與間隔物的剩餘部份上。在一實施例中，蓋層的寬度大於閘極遮罩的寬度。在一實施例中，硬化步驟在含有二氯矽烷與氫的氣體混合物之環境下進行。在一實施例中，硬化步驟增加第三介電層的硬化部份之矽含量。在一實施例中，第二介電層的氯含量低於第一介電層的氯含量。
依據又一實施例，半導體裝置包括閘極堆疊，位於半導體結構上，且半導體結構具有第一源極/汲極區、第二源極/汲極區、以及夾設於第一源極/汲極區與第二源極/汲極區之間的通道區，且閘極堆疊位於通道區上；閘極遮罩，位於閘極堆疊上，且閘極遮罩包括：閘極堆疊上的第一介電層，且第一介電層具有第一氯含量；第一介電層上的第二介電層，第二介電層具有第二氯含量，且第一氯含量不同於第二氯含量；以及第二介電層上的第三介電層，且第三介電層的第一部份其蝕刻速率低於第三介電層的第二部份其蝕刻速率；以及蓋層，位於閘極遮罩上。在一實施例中，上述半導體裝置更包括沿著閘極堆疊的側壁與閘極遮罩的側壁延伸的間隔物。在一實施例中，蓋層沿著間隔物的上表面延伸。在一實施例中，蓋層的寬度大於閘極遮罩的寬度。在一實施例中，第一氯含量大於第二氯含量。在一實施例中，第三介電層的第二部份其矽含量低於第三介電層的第一部份其矽含量。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明實施例。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明實施例之精神與範疇，並可在未脫離本發明實施例之精神與範疇的前提下進行改變、替換、或更動。
118:側壁間隔物
230:襯墊介電膜
332:層間介電層
502:閘極介電層
504:閘極
602:閘極遮罩
604:蓋層
606:區域
9041:第一膜
9042:第二膜
9043:第三膜
912d:摻雜硼的部份

Claims (10)

  1. 一種半導體裝置的形成方法，包括：形成一閘極堆疊於一半導體結構上；使該閘極堆疊凹陷以形成一第一凹陷；沿著該第一凹陷的底部與側壁形成一第一介電層，且該第一介電層具有一第一蝕刻速率；形成一第二介電層於該第一介電層上，該第二介電層具有一第二蝕刻速率，且該第一蝕刻速率大於該第二蝕刻速率；形成一第三介電層於該第二介電層上；改變該第三介電層的一部份之蝕刻速率；使該第一介電層、該第二介電層、與該第三介電層凹陷，以形成一第二凹陷；以及形成一蓋層於該第二凹陷中。
  2. 如請求項1之半導體裝置的形成方法，更包括：沿著該閘極堆疊的側壁形成一間隔物。
  3. 一種半導體裝置的形成方法，包括：形成一閘極堆疊於一半導體結構上；形成一間隔物於該閘極堆疊的側壁上；蝕刻該閘極堆疊以形成一第一凹陷；順應性地沉積一第一介電層於該第一凹陷中，且該第一介電層具有一第一蝕刻速率；順應性地沉積一第二介電層於該第一介電層上，該第二介電層具有一第二蝕刻速率，且該第一蝕刻速率大於該第二蝕刻速率； 順應性地沉積一第三介電層於該第二介電層上，且該第三介電層具有一第三蝕刻速率；硬化該第三介電層，且該第三介電層的硬化部分其蝕刻速率小於該第三蝕刻速率；以及蝕刻該第一介電層、該第二介電層、與該第三介電層，以形成一第二凹陷，該第二凹陷露出該間隔物的一部分，且該第一介電層、該第二介電層、與該第三介電層的保留部分形成一閘極遮罩。
  4. 如請求項3之半導體裝置的形成方法，更包括在形成該閘極遮罩之後，蝕刻該間隔物以移除該間隔物的一部分。
  5. 一種半導體裝置，包括：一閘極堆疊，位於一半導體結構上，該半導體結構具有一第一源極/汲極區、一第二源極/汲極區、以及夾設於該第一源極/汲極區與該第二源極/汲極區之間的一通道區，且該閘極堆疊位於該通道區上；一閘極遮罩，位於該閘極堆疊上，且該閘極遮罩包括：該閘極堆疊上的一第一介電層，且該第一介電層具有一第一氯含量；該第一介電層上的一第二介電層，該第二介電層具有一第二氯含量，且該第一氯含量不同於該第二氯含量；以及該第二介電層上的一第三介電層，且該第三介電層的第一部分其蝕刻速率低於該第三介電層的第二部分其蝕刻速率；以及一蓋層，位於該閘極遮罩上。
  6. 如請求項5之半導體裝置，更包括沿著該閘極堆疊的側壁與該閘極遮罩的側壁延伸的一間隔物。
  7. 一種半導體裝置的形成方法，包括：形成一閘極堆疊於一半導體結構上；使該閘極堆疊凹陷以形成一第一凹陷；沿著該第一凹陷的底部與側壁形成一第一介電層，且該第一介電層具有一第一氯含量；形成一第二介電層於該第一介電層上，該第二介電層具有一第二氯含量，且該第一氯含量大於該第二氯含量；形成一第三介電層於該第二介電層上，改變該第三介電層的一部分的矽含量；使該第一介電層、該第二介電層、與該第三介電層凹陷，以形成一第二凹陷；以及形成一蓋層於該第二凹陷上。
  8. 如請求項7之半導體裝置的形成方法，其中形成該第一介電層的步驟包括在含有二氯矽烷與氨的前驅物氣體混合物的環境下進行原子層沉積制程。
  9. 一種半導體裝置的形成方法，包括：形成一閘極堆疊於一半導體結構上；形成一間隔物於該閘極堆疊的側壁上；蝕刻該閘極堆疊以形成一第一凹陷；順應性地沉積一第一介電層於該第一凹陷中，且該第一介電層具有一第一氯含量；順應性地沉積一第二介電層於該第一介電層上，該第二介 電層具有一第二氯含量，且該第一氯含量大於該第二氯含量；順應性地沉積一第三介電層於該第二介電層上，且該第三介電層具有一第一矽含量；硬化該第三介電層，且該第三介電層的硬化部分的矽含量大於該第一矽含量；以及蝕刻該第一介電層、該第二介電層、與該第三介電層，以形成一第二凹陷；該第二凹陷露出該間隔物的一部份，且該第一介電層、該第二介電層、與該第三介電層的剩餘部分形成一閘極遮罩。
  10. 一種半導體裝置，包括：一閘極堆疊，位於一半導體結構上，一閘極遮罩，位於該閘極堆疊上，且該閘極遮罩包括：該閘極堆疊上的一第一介電層，且該第一介電層具有一第一氯含量；該第一介電層上的一第二介電層，該第二介電層具有一第二氯含量，且該第一氯含量不同於該第二氯含量；以及該第二介電層上的一第三介電層，該第三介電層具有第一部分與第二部分，該第三介電層的第一部分具有一第一矽含量，該第三介電層的第二部分具有一第二矽含量，且該第一矽含量與該第二矽含量不同；以及一第四介電層，位於該閘極遮罩上。
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