TWI751687B - 具有減量熱致彎曲度的半導體結構 - Google Patents
具有減量熱致彎曲度的半導體結構 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 229910003460 diamond Inorganic materials 0.000 claims description 22
- 239000010432 diamond Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 16
- 229910002704 AlGaN Inorganic materials 0.000 claims description 15
- 238000002161 passivation Methods 0.000 claims description 14
- 238000010586 diagram Methods 0.000 claims description 11
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 2
- 230000003993 interaction Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 13
- 229910002601 GaN Inorganic materials 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000000284 resting effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005701 quantum confined stark effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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Abstract
一種具有導熱基板的單片微波積體電路(MMIC)結構;半導體層,其設置在所述基板的上表面的第一部分上;主動檯面狀半導體裝置層,其設置在所述半導體層上;以及被動電子裝置,其直接設置在所述基板的所述上表面的第二部分上。
Description
本發明總體上涉及半導體結構,並且更具體地涉及具有減量熱致彎曲度的半導體結構。
如本領域中已知的,當一結構具有接合/生長在一起的兩個失配材料時,不同的材料性質(諸如熱膨脹係數(CTE))使所述結構彎曲。這種彎曲致使晶片製造困難,表現為半導體裝置的效能和產量降低。在製造高功率單片微波積體電路(MMIC)中使用的一個這種結構用作為高熱傳導率基板的底部材料,諸如金剛石(具有範圍在1000-2000的熱傳導率),或碳化矽(SiC)(具有在120W/(m‧K)的數量級的熱傳導率,例如,由於其高程度的熱傳導率),以及半導體材料,諸如III族氮化物,(例如,氮化鎵(GaN)形成於(或接合至)基板的整個上表面,其中諸如FET的主動裝置被製造為檯面狀半導體結構,其擱置在
GaN材料和被動裝置(諸如匹配網路)、被動部件(諸如電容器和電阻器),以及擱置在GaN的一部分上的互連傳輸線的一部分上。然而,GaN上的金剛石的直接生長或在高溫下的接合建立了熱膨脹係數(CTE)的CTE致使的獨立式晶片彎曲度>1毫米的100mm晶圓。此彎曲度致使難以製造晶圓,表現為半導體裝置的效能和產量降低。
許多的論文和出版物已處理此彎曲問題包含:J.Thompson,G.Tepolt,L.Racz.A.Mueller,T.Langdo,D.Gauthier,B.Smith,Draper Laboratory“Embedded Package Wafer Bow Elimination Techniques”,http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5898491;Paulo Ki,Quanzhong Jiang,Wang N.Wang,and Duncan W.E.Allsopp“Stress Engineering During the Fabrication of InGaN/GaN Vertical Light Emitting Diodes for Reducing the Quantum Confined Stark Effect”,http://ieeexplore.ieee.org/document/7728035/;Nga P.Pham,Maarten Rosmeulen,George Bryce,Deniz S.Tezcan,B.Majeed,Haris Osmanv,Imec,Kapeldreef 75,B-3001 Leuven,Belgium“Wafer bow of substrate transfer process for GaNLED on Si 8 inch”http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6507078。
圖1顯示一種這種使用高導熱基板的結構,例如金剛石或碳化矽(SiC)。一種主動裝置,例如,HEMT
FET係形成在基板的上表面的一部份,而被動裝置,在此例如,電阻器係形成在基板的上表面的另一部份。電阻器和FET透過電互連件來電互連。應當理解的是,被動裝置可以透過電感器、電容器,例如,而電互連件可以是功率分配器、功率組合器、耦接器,諸如,例如,混合耦接器、正交耦接器、移相器、輸入匹配網路、輸出匹配網路,例如。注意,在高導熱基板的整個上部上佈置有半導體層,在此例如是氮化鎵(GaN)。半導體層的一部分是檯面狀半導體結構,其用於提供主動裝置的主動區,在此為FET,而半導體層的其它部分具有在其上形成的被動裝置和電互連件的部分。如圖所示,在基板上方形成介電質鈍化層,在此例如是氮化矽。
根據本發明,提供了一種單片微波積體電路(MMIC)結構,包含:導熱基板;半導體層,其設置在所述基板的上表面的第一部分上;主動半導體裝置,其設置在所述半導體層上;被動電子裝置,其直接設置在所述基板的所述上表面的第二部分上。在一個實施例中,所述主動裝置為檯面狀結構。
在一個實施例中,提供了一種半導體結構,包含:導熱基板;主動裝置,包含:檯面結構,其設置在所述基板的上表面上的層上;以及被動裝置,其設置在所述基板的所述上表面上,所述被動裝置的底部係直接設置
在所述基板的所述上表面上。
在一個實施例中,所述半導體結構包含將所述主動裝置和所述被動裝置互連的電互連件,以及其中所述電互連件的底表面係直接設置在所述基板的所述上表面上。
在一個實施例中,提供了一種形成半導體結構的方法,包含:提供金剛石基板,所述金剛石基板具有在所述金剛石基板的上表面上並與其直接接觸的III-V族半導體磊晶層;確定所述金剛石基板的上表面上的第一位置以供形成主動半導體裝置和所述金剛石基板的所述上表面上的第二位置以供形成被動裝置;移除具有所確定的第二位置的所述III-V族半導體磊晶層的部分,同時將所述金剛石基板的所述上表面上的所述III-V族半導體磊晶層留在所確定的第一位置上;以及直接在所述第一確定位置處的所述III-V族半導體磊晶層上形成主動裝置,並在所述第二位置處直接形成所述被動裝置。
在一個實施例中,提供了一種形成半導體結構的方法,包含:設計MMIC電路示意圖,這種電路具有主動半導體裝置、被動裝置和將所述主動裝置連接至所述被動裝置的電互連件;從所述MMIC設計的示意圖電路,使用任何傳統遮罩產生軟體程式產生遮罩組,以製造所設計的MMIC電路,所述遮罩組具有:用於形成直接接合或形成在導熱基板上的III-V族半導體磊晶層的主動區上的主動半導體裝置的一系列遮罩;用於形成直接在所述主動區
外部的所述基板上並且與其直接接觸的被動區上的所述被動裝置的第二系列遮罩;以及用於形成電互連件的第三系列遮罩,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所述第一端部和所述第二端部之間的電互連件的部分;提供晶圓,包含:所述導熱基板;以及,直接與所述導熱基板的上表面接合或在其上生長的所述III-V族半導體磊晶層;使用所述第一系列遮罩,形成半導體檯面狀結構,其中所述主動裝置將在所述磊晶層的部分上形成;蝕刻掉所述檯面狀結構外部的所述磊晶層的部分;在所述III-V族半導體磊晶層的所述檯面狀結構上形成所述主動半導體裝置;使用所述第二系列遮罩,直接在所述主動區外部的所述基板上並與其直接接觸的被動區形成所述被動裝置;以及使用所述第三系列遮罩形成所述電互連件,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所述第一端部和所述第二端部之間並且直接在所述基板上的電互連件的部分。
在一個實施例中,所述基板是金剛石或碳化矽(SiC)。
本發明人已經認識到,在晶圓製造程序的早期利用這種佈置,一旦發熱主動裝置的位置確定為在磊晶
層(例如,GaN/AlGaN)上形成,被動裝置的磊晶層上的部分以及不需要操作這種被動裝置的磊晶層的電互連件與電互連件可以從基板的上表面被移除。透過移除大部分的GaN/AlGaN表面,並且發明人注意到大部分的表面係用於被動裝置和電互連件,而金剛石或SiC基板主要留在後面。此表面是高度光滑的,並且將支援單片特徵的製造,諸如傳輸線和被動裝置。最重要的是,大面積的磊晶層被移除,降低了整體的應力和晶片的彎曲度,恢復到金剛石或SiC基板的特性,而不是作為磊晶層影響的複合材料。因此,半導體製造程序和複合晶圓基板被提供,其中磊晶材料的一大部分從發熱主動裝置區域被蝕刻掉,從而支援主動裝置的最小覆蓋和MMIC操作。因此,磊晶層僅保留在重要區域中;為了減少熱效應,發熱主動裝置區域使整個複合基板的晶圓彎曲,同時仍然提供功能性的MMIC電晶體電路。
本發明的一或多個實施例的細節闡述於附圖和以下的描述中。根據說明書和圖式並且根據申請專利範圍,本發明的其它特徵、目的和優點將是顯而易見的。
10:單片微波積體電路
11:上表面
12:基板
14:主動裝置
16:被動裝置
16E:邊緣
18:電互連件
19:檯面狀半導體結構
19E:邊緣
20:III族氮化物層
22:磊晶AlGaN層
23:開口
24:源極接點
26:汲極接點
28:源極電極
29:鈍化層
30:汲極電極
32:閘極接點
34:遮罩
40:遮罩
42:遮罩
44:遮罩
46:遮罩
48:遮罩
50:遮罩
52:遮罩
53:視窗
54:新的遮罩
55:視窗
401:步驟
402:步驟
403:步驟
404:步驟
405:步驟
406:步驟
[圖1]是根據現有技術的具有電連接到被動裝置的主動裝置的MMIC的一部分的簡化橫截面示意圖。
[圖2]是根據本發明的具有電連接到被動裝置的主動裝置的圖5的MMIC的一部分的簡化橫截面示意
圖。
[圖3A-3S]是用於在其製造的各個階段形成圖2的MMIC的程序的簡化橫截面示意圖。
[圖4]是顯示根據本發明的用於製造圖2的MMIC的步驟的程序流程圖;以及
[圖5]是根據本發明的在其上形成有MMIC的晶片的俯視平面圖的簡化示意圖。
在各個圖式中相似的元件符號指示相同的元件。
現在參考圖2,顯示形成在單晶或晶體導熱基板12上的MMIC 10,在此例如為金剛石或SiC。MMIC 10包含發熱、主動裝置(在此例如是HEMT FET 14)、被動裝置16(在此例如是電阻器),主動裝置14和被動裝置16透過電互連件18被電互連。在此實施例中,HEMT FET 14是檯面狀半導體結構19,其在金剛石基板12的上表面11上具有下部磊晶、III族氮化物層20(在此為GaN),並且在下部磊晶上部磊晶層20上具有上部磊晶上部層22(在此為AlGaN)。FET 14具有介電質鈍化層29(在此例如是SiNx),其形成在下部磊晶III族氮化物層20和上部磊晶上部層22的外表面上,如圖所示。如所示,源極和汲極接點24、26分別形成為與磊晶AlGaN層22歐姆接觸。如所示,源極和汲極電極28、30分別形成在源極和汲極接點上。如所示,閘
極電極32形成為與磊晶AlGaN層22肖特基接觸,以控制源極接點24和汲極接點26之間的載子的流動。應當注意的是,被動裝置16的底部被設置在基板12的上表面11上,並且與其直接接觸。如所示,還應當注意,在檯面狀半導體結構19的邊緣19E和被動裝置16的邊緣16E之間有一間隙(GAP)。還應當注意,電互連件18的底部的一部分設置於導熱基板12的上表面11上,並且與其直接接觸。
現在參考圖3A至3S,顯示用於形成圖2所示的MMIC 10的程序。因此,在提供基板12之後,下部半導體層20和上部半導體層22(圖3A)、遮罩34(圖3B)係在AlGaN層22的上表面的一部分上形成,所述部分係在將形成檯面狀的半導體結構19(圖2)的基板12的表面11上。接著將所述表面暴露於合適的蝕刻劑,以僅移除下部GaN半導體層22的上部暴露部分和下部半導體層20的上部,如圖3C所示。在遮罩34被移除之後,所述結構被顯示在圖3D中;注意,基板12的整個上表面11被下部GaN層20的未蝕刻部分覆蓋。
現在參考圖3E,遮罩40係形成在將要形成主動裝置(在此為FET 14(圖2))的檯面狀半導體結構19的部分上。如圖所示,下部GaN半導體層20的未蝕刻部分的整個暴露部分(未遮蔽部分)被向下蝕刻掉至基板12的上表面11。接著移除遮罩40,從而產生如圖3F所示的結構。
參照圖3G,遮罩42係形成在如圖3G所示的結構上,其中這種遮罩42具有視窗或開口44,以暴露
AlGaN的上部半導體層22的部分,以供分別形成源極歐姆接點24和汲極歐姆接點26,如圖所示。
如圖3H所示,遮罩42被移除,並且所述結構的表面被覆蓋有SiNx鈍化材料29。
參照圖3I,遮罩44係形成在沉積的鈍化材料29的一部分上,所述部分係在將要形成主動裝置(在此為FET 14(圖2))的檯面狀半導體結構19的部分的上方。如圖3J所示,鈍化層(19)的整個暴露部分(未遮蔽部分)被向下蝕刻掉至基板12的上表面11。還應注意,鈍化層29也可以被遮蔽,隨後用於形成被動結構的層。
遮罩44被隨後移除,留下如圖3K顯示的結構;應注意,導熱基板12的上表面暴露在將要形成主動裝置(在此為FET 14(圖2))的檯面狀半導體結構19的部分的外部。
現在參考圖3L,新的遮罩46係形成為在將要形成閘極接點32(圖2)的鈍化材料29的部分上具有視窗或開口47。
現在參考圖3M,將具有遮罩46的結構(圖3L)暴露於合適的附魔(enchant),以暴露將要形成閘極接點32的AlGaN層22的表面的部分,如圖3M所示。
現在參考圖3N,遮罩48被沉積在具有開口的所述結構上,其中閘極金屬32係用以致使與AlGaN層22的肖特基接點。接下來閘極金屬32被沉積在遮罩48上,並穿過在其中的開口到將製造肖特基接點32(圖2)並且進行處
理以製造這種肖特基閘極接點32的AlGaN層22的部分。遮罩48被移除、剝離,從而移除了其上的閘極金屬32的一部分,從而形成了如圖3O所示的肖特基閘極接點32。
現在參考圖3P,遮罩50被形成在分別在源極接點24和汲極接點26上的鈍化材料29的部分上具有視窗或開口23的結構上;其中所述結構的部分分別將要形成有源極電極28和汲極電極30(圖2)。透過與圖3M和3N中類似的程序,源極接點24和汲極接點26被暴露,接著被遮蔽以供源極和汲極電極金屬的沉積。
現在參考圖3Q,如圖所示,源極和汲極電極金屬分別透過視窗沉積到源極接點24和汲極接點26上,並且遮罩被剝離,從而移除了金屬中未被用於源極和汲極電極的部分。
參考頂部圖3R,遮罩52被形成在具有視窗53以暴露將要形成被動裝置16(圖2)(在此,在此範例中,電阻器)的結構上。電阻材料(在此為例如氮化鉭(TaN))係穿過視窗53沉積,如圖所示,以形成被動裝置16;應當注意,被動裝置16被顯示為直接形成在導熱基板12上並與其直接接觸。還應注意的是,被動裝置16也可以形成在鈍化層29的頂部上,作為直接在基板12的頂部上的替代方案。還應注意,在檯面狀半導體結構19的部分的邊緣之間存在上面結合圖2描述的間隙(GAP),其中主動裝置(在此為FET 14(圖2))被形成並且為被動裝置的邊緣。
參考現在圖3S,圖3R中的遮罩52被移除並且
以新的遮罩54取代,新的遮罩54具有視窗55,其暴露汲極接點30並且延伸在被動裝置16的一個端部53,如圖所示。電互連件18的金屬係透過視窗沉積,從而將汲極接點30連接到被動裝置16。接著移除遮罩54,從而產生圖2所示的MMIC 10。
現在參考圖4,簡化的流程圖顯示用於製造具有圖2中所示的部分的MMIC和上面結合圖3A-3S描述的步驟。因此,設計了MMIC電路示意圖(步驟401),這種電路具有主動半導體裝置和被動裝置以及用於將主動半導體裝置和被動裝置電互連的電互連件。從MMIC設計的示意性電路產生:遮罩組(使用任何傳統遮罩產生軟體程式),以供製造所設計的MMIC電路,所述第一遮罩組具有:用於形成直接接合或形成在導熱基板上的III-V族半導體磊晶層的主動區上的主動半導體裝置的一系列遮罩;用於形成直接在所述主動區外部的所述基板上並且與其直接接觸的被動區上的所述被動裝置的第二系列遮罩;以及用於形成電互連件的第三系列遮罩,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所述第一端部和所述第二端部之間的電互連件的部分(步驟402)。提供晶圓,包含:導熱基板12;以及直接與所述導熱基板的上表面接合或在其上生長的所述III-V族半導體磊晶層22(圖5A)(步驟403)。使用第一系列遮罩34、40、42、44、46、48形成半
導體檯面狀結構19,其中所述主動裝置14將在所述磊晶層22的部分上形成;蝕刻掉所述檯面狀結構19外部的所述磊晶層22的部分;在所述III-V族半導體磊晶層22的所述檯面狀結構上形成所述主動半導體裝置14(步驟404)。使用所述第二系列遮罩,直接在所述主動區外部的所述基板上並與其直接接觸的被動區形成所述被動裝置(步驟405)。使用所述第三系列遮罩形成所述電互連件18,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置16的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所述第一端部和所述第二端部之間並且直接在所述基板12上的電互連件18的部分(步驟406)。
現在參考圖5,平面圖的簡化示意圖顯示了具有形成的MMIC 10的晶片。MMIC 10包含如在圖2中所示的複數個HEMT FET、複數個的被動裝置(在此為電阻器)、電容器和電感器和電互連件(在此為微波傳輸線,諸如微帶(microstrip)或共面波導(CPW)),例如。如圖3所示,在此實施例中的HEMT FET是具有下部磊晶III族氮化物層20(在此為GaN)的檯面結構18,其位於金剛石基板12的上表面13和上部磊晶上部層22(在此為位於下部磊晶上部磊晶層20上的AlGaN)上,如上方結合圖2所述的。由虛線表示的2DEG通道24係形成在下部磊晶上部磊晶層20的上部。FET 14a具有介電質鈍化層29,在此例如為如上面結合圖2和圖3A-3S描述形成的SiNx。可觀察到,在基板12
的上表面11上具有磊晶III族氮化物層20的唯一區域是檯面結構19;並且更具體地,在基板12的上表面11上的唯一區域是主動裝置14。因此,檯面19係透過基板12的上表面11的暴露部分彼此分離。
因此,參照圖5,應當注意,FET被檯面結構19佔據,而在基板的上表面的更大的部分是無效的磊晶III族氮化物層20,其係用於形成被動裝置和電互連件。
現在應當理解,根據本發明的一種單片微波積體電路(MMIC)結構,包含:導熱基板;半導體層,其設置在所述基板的上表面的第一部分上;主動半導體裝置,其設置在所述半導體層上;以及被動電子裝置,其直接設置在所述基板的所述上表面的第二部分上。所述MMIC結構可以獨立地或組合地包含以下一或多個特徵,包含:其中所述主動裝置是檯面狀結構;其中所述半導體結構包含將所述主動裝置和所述被動裝置互連的電互連件,以及其中所述電互連件的底表面係直接設置在所述基板的所述上表面上;或包含將所述主動裝置和所述被動裝置互連的電互連件,以及其中所述電互連件係直接設置在所述基板上並與其間接接觸。
現在也應當理解,根據本發明的一種半導體結構,包含:導熱基板;主動裝置,包含:檯面結構,其設置在所述基板的上表面上的層上;以及被動裝置,其設置在所述基板的所述上表面上,所述被動裝置的底部係直接設置在所述基板的所述上表面上。
現在也應當理解,根據本發明的一種形成半導體結構的方法,包含:提供基板,所述基板具有在所述金剛石基板的上表面上並與其直接接觸的III-V族半導體磊晶層;確定所述基板的上表面上的第一位置以供形成主動半導體裝置和所述基板的所述上表面上的第二位置以供形成被動裝置;移除具有所確定的第二位置的所述III-V族半導體磊晶層的部分,同時將所述金剛石基板的所述上表面上的所述III-V族半導體磊晶層留在所確定的第一位置上;以及直接在所述第一確定位置處的所述III-V族半導體磊晶層上形成主動裝置,並在所述第二位置處直接形成所述被動裝置。
現在也應當理解,根據本發明的一種形成半導體結構的方法,包含:設計MMIC電路示意圖,這種電路具有主動半導體裝置、被動裝置和將所述主動裝置連接至所述被動裝置的電互連件;從所述MMIC設計的示意圖電路,使用任何傳統遮罩產生軟體程式產生遮罩組,以製造所設計的MMIC電路,所述遮罩組具有:用於形成直接接合或形成在導熱基板上的III-V族半導體磊晶層的主動區上的主動半導體裝置的一系列遮罩;用於形成直接在所述主動區外部的所述基板上並且與其直接接觸的被動區上的所述被動裝置的第二系列遮罩;以及用於形成電互連件的第三系列遮罩,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並
與其直接接觸的設置在所述第一端部和所述第二端部之間的電互連件的部分;提供晶圓,包含:所述導熱基板;以及,直接與所述導熱基板的上表面接合或在其上生長的所述III-V族半導體磊晶層;使用所述第一系列遮罩,形成半導體檯面狀結構,其中所述主動裝置將在所述磊晶層的部分上形成;蝕刻掉所述檯面狀結構外部的所述磊晶層的部分;在所述III-V族半導體磊晶層的所述檯面狀結構上形成所述主動半導體裝置;使用所述第二系列遮罩,直接在所述主動區外部的所述基板上並與其直接接觸的被動區形成所述被動裝置;以及使用所述第三系列遮罩形成所述電互連件,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所述第一端部和所述第二端部之間並且直接在所述基板上的電互連件的部分。所述方法可以獨立地或組合地包含以下一或多個特徵,包含:其中所述基板是金剛石或碳化矽(SiC),或包含將所述主動裝置和所述被動裝置互連的電互連件,以及其中所述電互連件係設置在所述基板上並與其間接接觸。
已經描述了本發明的許多實施例。然而,將理解的是,可以在不脫離本發明的精神和範圍的情況下進行各種修改。例如,MMC電路可以與圖2所示的電路不同。此外,可以在形成主動裝置之後形成被動裝置。因此,其它實施例在所附申請專利範圍的範圍內。
10:單片微波積體電路
11:上表面
12:基板
14:主動裝置
16:被動裝置
16E:邊緣
18:電互連件
19:檯面狀半導體結構
19E:邊緣
20:III-N族層
22:磊晶AlGaN層
24:源極接點
26:汲極接點
28:源極電極
29:鈍化層
30:汲極電極
32:閘極接點
Claims (8)
- 一種單片微波積體電路(MMIC)結構,包含:導熱基板,其包含金剛石或碳化矽(SiC);主動半導體裝置,其直接設置在所述導熱基板上,所述主動半導體裝置包含:含有GaN的下部磊晶半導體層,其設置在所述基板的上表面的第一部分上;含有AlGaN的上部磊晶半導體層,其設置在所述下部磊晶半導體層上;以及含有SiNx的鈍化層,其形成在所述下部磊晶半導體層的外表面和所述上部磊晶半導體層的外表面上;被動電子裝置,其直接設置在所述導熱基板的所述上表面的第二部分上;以及電互連件,其設置在所述主動半導體裝置的邊緣和所述被動電子裝置之間的間隙中,所述電互連件直接設置在所述導熱基板上。
- 如請求項1所述的MMIC結構,其中所述主動半導體裝置是檯面狀結構。
- 一種半導體結構,包含:導熱基板,其包含金剛石或碳化矽(SiC);主動裝置,包含:檯面結構,其設置在所述基板的上表面上,所述主動裝置,包含:含有GaN的下部磊晶半導體層,其設置在所述基板 的上表面的第一部分上;含有AlGaN的上部磊晶半導體層,其設置在所述下部磊晶半導體層上;以及含有SiNx的鈍化層,其形成在所述下部磊晶半導體層的外表面和所述上部磊晶半導體層的外表面上;被動裝置,其設置在所述基板的所述上表面上,所述被動裝置的底部係直接設置在所述基板的所述上表面上;以及電互連件,其設置在所述主動半導體裝置的邊緣和所述被動裝置之間的間隙中,所述電互連件直接設置在所述基板上。
- 一種半導體結構,包含:複數個主動半導體裝置、複數個被動裝置以及將所述主動裝置連接到所述被動裝置的複數個電互連件;所述主動半導體裝置中之各者具有直接接合到含有金剛石或碳化矽的導熱基板的III族氮化物半導體磊晶層的主動區;所述被動裝置中之各者具有與所述主動區外部的所述基板直接接觸的被動區;以及所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及設置在所述第一端部和所述第二端部之間並且與所述主動區外部的所述基板直接接觸的電互連件的部分。
- 一種形成半導體結構的方法,包含: 提供一基板,所述基板具有在所述金剛石基板的上表面上並與其直接接觸的III-V族半導體磊晶層;確定所述基板的上表面上的第一位置以供形成主動半導體裝置和所述基板的所述上表面上的第二位置以供形成被動裝置;移除具有所確定的第二位置的所述III-V族半導體磊晶層的部分,同時將所述基板的所述上表面上的所述III-V族半導體磊晶層留在所確定的第一位置上;以及直接在所述第一確定位置處的所述III-V族半導體磊晶層上形成主動裝置,並在所述第二位置處直接形成所述被動裝置。
- 一種形成半導體結構的方法,包含:設計MMIC電路示意圖,這種電路具有主動半導體裝置、被動裝置和將所述主動裝置連接至所述被動裝置的電互連件;從所述MMIC設計的示意圖電路,使用任何傳統遮罩產生軟體程式產生遮罩組,以製造所設計的MMIC電路,所述遮罩組具有:用於形成直接接合或形成在導熱基板上的III-V族半導體磊晶層的主動區上的主動半導體裝置的一系列遮罩;用於形成直接在所述主動區外部的所述基板上並且與其直接接觸的被動區上的所述被動裝置的第二系列遮罩;以及用於形成電互連件的第三系列遮罩,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所 述第一端部和所述第二端部之間的電互連件的部分;提供晶圓,包含:所述導熱基板;以及,直接與所述導熱基板的上表面接合或在其上生長的所述III-V族半導體磊晶層;使用所述第一系列遮罩,形成半導體檯面狀結構,其中所述主動裝置將在所述磊晶層的部分上形成;蝕刻掉所述檯面狀結構外部的所述磊晶層的部分;在所述III-V族半導體磊晶層的所述檯面狀結構上形成所述主動半導體裝置;使用所述第二系列遮罩,直接在所述主動區外部的所述基板上並與其直接接觸的被動區形成所述被動裝置;以及使用所述第三系列遮罩形成所述電互連件,所述電互連件具有在所述主動半導體裝置的電接點上的第一端部、在所述被動裝置的電接點區域上的第二端部,以及直接在所述主動區外部的所述基板上並與其直接接觸的設置在所述第一端部和所述第二端部之間並且直接在所述基板上的電互連件的部分。
- 如請求項6所述的方法,其中所述基板是金剛石或碳化矽(SiC)。
- 如請求項6所述的方法,包含形成將所述主動裝置和所述被動裝置互連的電互連件,以及其中所述電互連件係形成在所述基板上並與其間接接觸。
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