TWI741965B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The package (1) has a base plate (2) and a frame (4) joined to the outer periphery of the main surface of the base plate (2). The electronic component (5) with the semiconductor chip (7) is mounted on the main surface of the base board (2) by the first solder (6). A second solder (12) having a lower melting point than the first solder (6) is applied to a region on the main surface of the base board (2) where the electronic component (5) is not mounted. The cover 13 is joined to the frame (4) by the third solder (14) to seal the electronic component (5)

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

In high-frequency FETs that require high output, in order to ensure the reliability of the transistor, it is necessary to ensure high heat dissipation. For this reason, as a package for high-frequency FETs, copper or a metal compound of copper is selected as a metal package with a metal base. In order to mount a semiconductor chip and a substrate constituting a matching circuit in such a package, for example, gold-tin solder having high thermal conductivity is used. In addition, when high reliability is required, the airtightness in the sealed package is required, and for example, gold-tin solder is used for sealing. [Prior Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 62-194651

[Problems to be solved by the invention]

Solder swarf may be generated during soldering during mounting or sealing, and may move inside the sealed package. As a conductive foreign material, this solder scrap will short-circuit the wiring of the high-frequency circuit, degrade the characteristics of the product, and cause defects such as burning of the semiconductor chip.

In addition, in order to adhere foreign substances such as dust floating in the package, it has been proposed to form a polyimide-based resin layer on the upper surface of the package (for example, refer to Patent Document 1). However, foreign matter that is heavier than dust like solder scraps will fall to the bottom surface inside the package and cannot be adhered. Therefore, the occurrence of defects cannot be suppressed.

In order to solve the above-mentioned problems, the present invention aims to provide a semiconductor device and a manufacturing method thereof that can suppress occurrence of defects. [Means to solve the problem]

The semiconductor device of the present invention is characterized by comprising: a base plate; a package having a frame joined to the outer peripheral portion of the main surface of the base plate; and electronic components mounted on the base plate of the base plate by a first solder The main surface has a semiconductor chip; a second solder applied to the area of the main surface of the base board where the electronic component is not mounted, and has a lower melting point than the first solder; and a cover, which is made of a third solder It is bonded to the frame and seals the electronic component. [Effects of the invention]

In the present invention, the second solder with a low melting point is applied to the area where the electronic component is not mounted on the main surface of the base board. With this, the second solder can fix the solder swarf inside the package without being able to move. Therefore, it is possible to prevent short circuits between the wirings of the high-frequency circuit and suppress the occurrence of defects.

[Form to implement invention]

The description will be made with reference to the diagrams of the semiconductor device and its manufacturing method according to the embodiment. The same or corresponding elements are marked with the same symbols, and repeated descriptions may be omitted.

Embodiment 1 FIG. 1 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the first embodiment. FIG. 2 is a plan view of the inside of the semiconductor device related to the first embodiment. The semiconductor device of this embodiment is a package for high-frequency FET.

The package 1 has a base plate 2, ceramic terminals 3 joined to the outer periphery of the main surface of the base plate 2, and a frame 4. The electronic component 5 is mounted on the main surface of the base board 2 by solder 6. The electronic component 5 has a semiconductor wafer 7 such as a high-frequency amplifier for amplifying signals, and a substrate 8 on which a matching circuit of the high-frequency amplifier is printed. The semiconductor chip 7 and the substrate 8 are connected by wires 9. The substrate 8 is connected to a lead 10 of the ceramic terminal 3 by a wire 11.

The solder 12 is applied to the area on the main surface of the base board 2 where the electronic component 5 is not mounted, and is exposed inside the package 1. The back surface of the cover 13 is joined to the upper surface of the frame 4 by solder 14 to seal the electronic component 5. The melting point of the solder 12 is lower than that of the solders 6, 14. For example, the solders 6, 14 are gold-tin solder, and the solder 12 is tin-silver-copper solder.

In the sealing step, the package 1 is carried on the heating station 15 with the package 1 under the cover 13 and heated. Thereby, the solder 12 is melted without melting the solder 6. When joining the cover 13 to the frame 4, the cover 13 is cut on the upper surface of the frame 4 in order to blend with the solder 14. At this time, the solder scraps 16 generated from the solder 14 fall inside the package 1 to the main surface of the base plate 2 and become conductive foreign objects that may affect the product characteristics and reliability. However, the molten solder 12 can fix the solder swarf 16 so that the solder swarf 16 cannot move. Therefore, it is possible to prevent deterioration of product characteristics or burnout of semiconductor wafers due to the occurrence of short-circuits between wirings of high-frequency circuits, and to suppress occurrence of defects. In addition, it is possible to suppress the occurrence of defects even in the case of performing a PIND test that vibrates the semiconductor device in a high-acceleration environment and detects conductive foreign objects inside the package.

In addition, even after sealing, the package body 1 may be heated at a temperature at which the solder 12 is not melted but the solder 6 is not melted, so that the remaining solder scraps 16 that cannot be completely captured during the sealing can be fixed. With this, even when a foreign body is detected by the PIND test, the detected conductive foreign body can be prevented from moving.

Embodiment 2 FIG. 3 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the second embodiment. Fig. 4 is a plan view of the back surface of the cover of the second embodiment. In this embodiment, the solder 14 is applied to the entire back surface of the cover 13. The solder 14 is, for example, gold tin solder.

In the sealing step, the cover 13 is placed on the heating station 15 with the back side up, and the solder 14 is heated and melted. The frame 4 is joined with the solder 14 on the back side of the cover 13 to seal the electronic component 5. The solder 14 is exposed inside the package 1 and fixes the solder scraps 16 generated from the solder 6 when the electronic component 5 is mounted and the solder scraps 17 generated from the solder 14 when sealing. As a result, the solder scraps 16 and 17 can be prevented from moving, and the occurrence of defects can be suppressed more than in the first embodiment. The other structures and effects are the same as in the first embodiment.

Embodiment 3 Fig. 5 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the third embodiment. Fig. 6 is a plan view of the back surface of the cover of the third embodiment. In this embodiment, the solder 14 is applied to the outer periphery of the back surface of the cover 13, and the solder 18 having a lower melting point than the solder 14 is applied to the center of the back surface of the cover 13. For example, the solder 14 is a gold-tin solder, and the solder 18 is a tin-silver-copper solder.

As in the second embodiment, the solder scraps 16, 17 can be fixed by the molten solder 14, 18 in the sealing step. Next, after the sealing step, the lid 13 may be placed on the heating station 15 and heated in a state where the lid 13 is located below the package body 1, and the solder 18 may be melted without melting the solder 6 and the solder 14. Thereby, after the sealing, the solder scraps 16 and 17 remaining which cannot be completely captured during the sealing can be fixed. Therefore, the occurrence of defects can be suppressed more than in the second embodiment. The other structures and effects are the same as in the second embodiment.

Embodiment 4 FIGS. 7 and 8 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the fourth embodiment. The semiconductor chip 7 and the substrate 8 are mounted on the board 19 by solder 20. The plate 19 is, for example, the same material as the base plate 2. As shown in FIG. 7, this board 19 is joined to the main surface of the base board 2 by solder 6. Next, as shown in Fig. 8, the cover 13 is used to seal. By using the board 19, the high-frequency circuit composed of the semiconductor chip 7 and the substrate 8 is made higher than the main surface of the base board 2.

The semiconductor chip 7 and the substrate 8 can be welded to the board 19 outside of the package. Therefore, the solder swarf generated during soldering can be removed outside the package. In addition, because the size of the board 19 is larger than the semiconductor wafer 7 and the substrate 8, it is easy to mount the board 19 to the base board 2.

In addition, the characteristics of the high-frequency circuit can be confirmed before the board 19 is mounted on the base board 2. Therefore, assuming that the capacity of the semiconductor wafer 7 is insufficient, it can be discarded in the state of the board 19. Compared with discarding products assembled into expensive high-frequency FET packages, the loss due to discarding can be suppressed.

In addition, although the plate 19 may be made of a material different from that of the base plate 2, it is better to select a material with a similar coefficient of linear expansion. Thereby, the difference in the coefficient of linear expansion between the base plate 2 and the plate 19 caused by the temperature rise during soldering disappears, and the destruction of the solder 6 can be avoided. The other structures and effects are the same as in the first embodiment. In addition, the configuration of Embodiment 4 can also be combined with Embodiment 2 or 3.

1: Package body 2: Base plate 3: Ceramic terminal 4: frame 5: Electronic components 6, 12, 14, 18, 20: solder 7: Semiconductor wafer 8: substrate 9, 11: wire 10: Lead 13: cover 15: Heating station 16,17: Solder shavings 19: Board

FIG. 1 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the first embodiment. FIG. 2 is a plan view of the inside of the semiconductor device related to the first embodiment. FIG. 3 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the second embodiment. Fig. 4 is a plan view of the back surface of the cover of the second embodiment. Fig. 5 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the third embodiment. Fig. 6 is a plan view of the back surface of the cover of the third embodiment. Fig. 7 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the fourth embodiment. Fig. 8 is a cross-sectional view showing the manufacturing steps of the semiconductor device according to the fourth embodiment.

1: Package body

2: Base plate

3: Ceramic terminal

4: frame

5: Electronic components

6, 12, 14: Solder

7: Semiconductor wafer

8: substrate

9, 11: wire

10: Lead

13: cover

15: Heating station

16: Solder chips

Claims (3)

A semiconductor device, characterized by comprising: Base plate A package body having a frame joined to the outer periphery of the main surface of the above-mentioned base plate; An electronic component, which is mounted on the main surface of the base board by a first solder, and has a semiconductor chip; and A cover, the back of which is joined to the frame by a second solder and seals the electronic components, Wherein, the above-mentioned back surface of the above-mentioned cover is completely coated with the above-mentioned second solder, The second solder is exposed inside the package and fixes solder scraps generated from the first solder. The semiconductor device of claim 1, wherein the electronic component has a board on which the semiconductor chip is mounted, and the board is joined to the main surface of the base board by the first solder. A method for manufacturing a semiconductor device, which is characterized by comprising: The step of joining the frame to the outer periphery of the main surface of the base plate to form a package; A step of mounting an electronic component having a semiconductor chip on the main surface of the base board by a first solder; The step of fully coating the second solder on the back of the cover; and The step of placing the cover on a heating station with the back surface on top and heating to melt the second solder, and bonding the frame to the back surface of the cover by the second solder to seal the electronic component.

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