JPH05275553A - Electronic circuit device - Google Patents
Electronic circuit deviceInfo
- Publication number
- JPH05275553A JPH05275553A JP4125018A JP12501892A JPH05275553A JP H05275553 A JPH05275553 A JP H05275553A JP 4125018 A JP4125018 A JP 4125018A JP 12501892 A JP12501892 A JP 12501892A JP H05275553 A JPH05275553 A JP H05275553A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- melting point
- circuit board
- cap
- solders
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は加工処理・はんだの局部
溶融接続により半導体や部品を回路基板に封止した電子
回路装置、とくに封止部の信頼性を向上させるのに利用
可能な電子回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device in which a semiconductor or a component is sealed on a circuit board by processing / local fusion connection of solder, and particularly an electronic circuit which can be used to improve the reliability of the sealing portion. Regarding the device.
【０００２】[0002]
【従来の技術】従来、電子回路装置においては、半導体
や部品の機械的、化学的保護および量産性、信頼性の向
上を目的として、はんだによる面付実装が知られてい
る。その中でも、半導体の最も高密度な実装法として、
図４に示すごとく、半導体チップ１と基板２の周端部対
向面を電極４、５を介して微細なはんだ３で接続する方
法が知られている（例、特開昭４３−２８７３５号公
報、米国特許第３８７１０１４号明細書）。2. Description of the Related Art Conventionally, in electronic circuit devices, surface mounting using solder has been known for the purpose of mechanical and chemical protection of semiconductors and components, mass productivity and improvement of reliability. Among them, as the highest density mounting method for semiconductors,
As shown in FIG. 4, there is known a method of connecting the semiconductor chip 1 and the peripheral surface of the substrate 2 facing each other with fine solder 3 through electrodes 4 and 5 (eg, Japanese Patent Laid-Open No. 43-28735). , U.S. Pat. No. 3,871,014).
【０００３】[0003]
【発明が解決しようとする課題】しかるに、従来の方法
は、半導体チップ１と回路基板２とを接続する際にはん
だ３を完全に溶融し、上記電極４、５とのぬれ・拡散反
応を利用して、半導体チップ１と基板２とを接続してい
た。そのため、半導体チップ１と基板２との接続部のは
んだ３が冷却過程で合金組成の偏析や欠隔および残留応
力が発生して、伸びが小さな鋳造組織状態となる。この
鋳造状態は外力にたいして伸びが小さく、不均一な変形
を発生するため、疲労性がわるく、使用中の種々のスト
レスにたいして比較的短時間で、はんだ３が破壊する問
題があった。However, according to the conventional method, when the semiconductor chip 1 and the circuit board 2 are connected, the solder 3 is completely melted and the wetting / diffusion reaction between the electrodes 4 and 5 is utilized. Then, the semiconductor chip 1 and the substrate 2 were connected. Therefore, the solder 3 at the connecting portion between the semiconductor chip 1 and the substrate 2 undergoes segregation of alloy composition, gaps, and residual stress during the cooling process, resulting in a cast structure state in which elongation is small. In this cast state, the elongation is small with respect to external force and non-uniform deformation occurs, so that there is a problem that the fatigue property is poor and the solder 3 is broken in a relatively short time against various stresses during use.
【０００４】本発明は、従来の上記問題点を解決し、高
信頼性のはんだ封止を可能とする電子回路装置を提供す
ることにある。An object of the present invention is to provide an electronic circuit device which solves the above-mentioned conventional problems and enables highly reliable solder sealing.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記の目的を
達成するために、圧延などの強加工と熱処理を加えて延
性を著しく改善し、はんだ接続部に対応した形状に成形
加工をおこなった加工はんだ材を、回路基板とキャップ
との間に低融点のはんだを介して高融点のはんだを介挿
し、上記低融点のはんだを溶融によって回路基板上の部
品を封止するように構成したことを特徴とするものであ
る。In order to achieve the above-mentioned object, the present invention performs strong forming such as rolling and heat treatment to remarkably improve ductility, and forms into a shape corresponding to a solder connection portion. The processed solder material is configured such that the high melting point solder is interposed between the circuit board and the cap through the low melting point solder, and the low melting point solder is melted to seal the components on the circuit board. It is characterized by that.
【０００６】[0006]
【作用】しかして、本発明は、つぎのような現象および
原理にもとづいて、加工はんだ材を部品と基板との間に
接続部材として使用したものである。すなわち、金属の
多くは、溶融・凝固すると、ガスの吸截や欠陥が多く、
さらに純金属以外のほとんどの合金は凝固の過程で組成
偏析や重量偏析をともなう不均質な鋳造組織となる。こ
のような欠陥や不均質な組織からなる金属・合金は一般
に脆いため、構造部材などに使用する場合などにおいて
は圧延や熱処理をおこない、鋳造組織をこわして均質に
し、これにより靱性や延性を改善する方法がおこなわれ
ている。しかるに、ろう材としてのＰｂ−ＳｎやＡｕ−
Ｓｎなどの合金は、溶融接続を基本原理としているた
め、溶融凝固すると、かならず鋳造組織となるので、こ
れを加工して破壊することはほとんど不可能である。The present invention, however, uses the processed solder material as a connecting member between the component and the substrate based on the following phenomena and principles. That is, most of the metals, when melted and solidified, have many gas absorptions and defects,
Furthermore, most alloys other than pure metals have a heterogeneous cast structure with composition segregation and weight segregation during the solidification process. Metals and alloys with such defects and inhomogeneous structures are generally brittle, so when they are used for structural members, etc., they are rolled and heat treated to break the cast structure and make it homogeneous, which improves toughness and ductility. How to do is done. However, Pb-Sn and Au-as brazing filler metals
Since alloys such as Sn have a fusion bonding as a basic principle, when they are melted and solidified, they always have a cast structure. Therefore, it is almost impossible to process and destroy them.
【０００７】図５は縦軸に応力（ｋｇ／ｍｍ2 ）をと
り、横軸に伸びε（％）をとった場合のＰｂ−Ｓｎ合金
を例として加工材ａ’、ｂ’、ｃ’と、鋳造材ａ、ｂ、
ｃの引張特性がどの程度異なるかを示したものである。In FIG. 5, the work materials a ', b', and c'are given by taking as an example the Pb-Sn alloy in which stress (kg / mm @ 2) is plotted on the vertical axis and elongation .epsilon. (%) Is plotted on the horizontal axis. Cast materials a, b,
It shows how different the tensile properties of c are.
【０００８】同図に示すごとく、加工材ａ’、ｂ’、
ｃ’はいずれの組成においても、軟らかく、著しい伸び
の改善が見られる。この加工材ａ’、ｂ’、ｃ’は圧下
率９０％で冷間圧延したシートから引張試験片を作成し
たのち、約一週間位室温で熱処理したものである。つぎ
に図６は９５Ｐｂ／５Ｓｎはんだの鋳造材（図６(a)、
図５(c) に相当）と、加工材（図６(b) 、図５(c')に相
当）の組織を比較したものである。同図に示すごとく、
加工材の組織は鋳造材に比較して、結晶粒が細かく偏析
して高濃度のＳｎ相が球状化し、かつ内部歪みの少ない
ものになっている。この伸びは鋳造材の３〜４倍で、加
工・熱処理による特性改善の効果が理解できる。As shown in the figure, the processed materials a ', b',
c'is soft in any composition, and a remarkable improvement in elongation is observed. The processed materials a ′, b ′, and c ′ were prepared by forming a tensile test piece from a sheet cold-rolled at a rolling reduction of 90%, and then heat-treating it at room temperature for about one week. Next, FIG. 6 shows a casting material of 95Pb / 5Sn solder (FIG. 6 (a),
5 (c)) and the processed material (corresponding to FIG. 6 (b) and FIG. 5 (c ')) are compared. As shown in the figure,
As compared with the cast material, the texture of the processed material is such that the crystal grains are finely segregated, the high-concentration Sn phase is spheroidized, and the internal strain is small. This elongation is 3 to 4 times that of the cast material, and the effect of property improvement by working and heat treatment can be understood.
【０００９】本発明者らは、上記の現象から、上記の加
工材を接続材として使用することにより、種々のストレ
スによる疲労などに十分に耐えられる接続部が得られる
とおもうにいたったのである。すなわち、加工材より低
融点のはんだで、加工材の接続端部のみを溶融接続する
ことにより、加工材のすぐれた靱性および延性を失うこ
となく接続できるので、信頼性の高い接続ができ、かつ
このような効果が期待できるような材料としてはほとん
どのろう材について可能性があるからである。図７は
Ｍ．Ｈａｎｓｅｎによって１９５８年に発表されたＰｂ
−Ｓｎ合金の状態図、図８は同じくＰｂ−Ｉｎ合金の状
態図、図９は同じくＰｂ−Ｓｂ合金の状態図である。こ
れらの図から明らかなごとく、いずれも冷却凝固過程で
偏析や不均質な組織となり、これらを加工・熱処理すれ
ば、伸び特性の改善が期待できる。From the above phenomenon, the present inventors have made it clear that by using the above-mentioned processed material as a connecting material, a connecting portion that can sufficiently withstand fatigue due to various stresses can be obtained. .. That is, with a solder having a melting point lower than that of the processed material, by melting and connecting only the connection end portion of the processed material, it is possible to connect without losing the excellent toughness and ductility of the processed material, so that a highly reliable connection can be made, and This is because most of the brazing filler metals have a possibility of being expected to have such effects. FIG. Pb announced by Hansen in 1958
-Sn alloy phase diagram, Fig. 8 is a Pb-In alloy phase diagram, and Fig. 9 is a Pb-Sb alloy phase diagram. As is clear from these figures, segregation and inhomogeneous structures are formed in the cooling and solidification process, and if these are processed and heat-treated, improvement in elongation characteristics can be expected.
【００１０】[0010]
【実施例】以下本発明の一実施例を示す図１ないし図３
について説明する。図１は本発明を電子回路装置におけ
る封止に実施した場合を示す図１および図２について説
明する。同図に示すごとく、回路基板２上に接続用はん
だ２４により接続する半導体チップ１およびコンデンサ
などの部品を封止するため、上記半導体チップ１および
コンデンサなどの部品の上方部を覆うように配置された
キャップ２５と、上記回路基板２の周端部間に電極４、
５を介して加工成形された加工はんだ２６を介挿し、上
記電極４、５と加工はんだ２６との間に該加工はんだ２
６よりも低融点のはんだ（図示せず）を付着し、この低
融点のはんだのみを溶融して、上記キャップ２５と回路
基板２とを局部的に溶融接続したものである。なお、上
記キャップ２５、加工はんだ２６および回路基板２５に
て封止された内部は真空かあるいは不活性ガスの雰囲気
で部品を保護している。また、上記半導体チップ１およ
びコンデンサなどの部品を回路基板２に接続するための
接続用はんだ２４は、キャップ２５と回路基板２とを封
止する際に溶融しないように、高融点のはんだを使用し
ている。1 to 3 showing an embodiment of the present invention.
Will be described. FIG. 1 illustrates FIG. 1 and FIG. 2 showing a case where the present invention is applied to sealing in an electronic circuit device. As shown in the figure, in order to seal the components such as the semiconductor chip 1 and the capacitor connected to the circuit board 2 by the connecting solder 24, the semiconductor chip 1 and the capacitor are arranged so as to cover the upper parts of the components. The cap 25 and the electrode 4 between the peripheral end portion of the circuit board 2,
The working solder 26, which has been worked and formed via 5, is inserted, and the working solder 2 is interposed between the electrodes 4, 5 and the working solder 26.
A solder (not shown) having a melting point lower than that of No. 6 is adhered, and only the solder having the low melting point is melted to locally melt and connect the cap 25 and the circuit board 2. The inside of the cap 25, the processed solder 26 and the circuit board 25 is protected by vacuum or an inert gas atmosphere. Further, as the connecting solder 24 for connecting the semiconductor chip 1 and the components such as the capacitor to the circuit board 2, a high melting point solder is used so as not to melt when the cap 25 and the circuit board 2 are sealed. is doing.
【００１１】つぎに図３により導体パターンを有する部
品と回路基板との接続をはんだにより接続する電子回路
装置の製造方法を述べると、まず、図３(a) に示すごと
く各種材料からなる基板２上に各々の材料に適した方法
で電極５を形成する。たとえば上記基板２がアルミナセ
ラミックで形成されている場合には、Ａｇ−Ｐｂおよび
Ｗなどの導体ペーストを印刷、焼成して上記電極５を形
成する。導体ペーストがＷのときには、さらにＮｉメッ
キなどをおこなって電極５を形成する。このようにして
形成された電極５上に低融点のはんだを、たとえばＰｂ
−ＳｎあるいはＡｎ−Ｓｎなどの共晶はんだをはんだペ
ーストの印刷・リフロやはんだボール、真空蒸着などに
よる供給・リフロおよびはんだディップによりはんだ７
を形成して回路基板を作成する。同様な方法で半導体チ
ップ１にも電極４に低融点のはんだ９を形成する。つい
で図３(b) に示すごとく、上記電極５の形状をたとえば
円形、四角形、三角形などに対応する形状をした高融点
の加工はんだ８を形成する。すなわち、加工はんだ８は
たとえば９５ｗｔ％Ｐｂ−５ｗｔ％Ｓｎ、８０ｗｔ％Ａ
ｎ−２０ｗｔ％Ｓｎを成形して、上記回路基板２上の低
融点はんだ７に一致させて載置する。この状態で加熱
し、低融点はんだ７のみを溶融して加工はんだ８を電極
５上に固定する。なお、上記加工はんだ８は溶解・鋳造
して板状に圧延したのち、９０゜圧下率まで加工して５
０゜Ｃで２日間不活性雰囲気中で熱処理をおこなったも
ので、この引張特性は前記図１０に示すｃ’の特性にほ
ぼ一致した。ついで、図３(c) に示すごとく上記半導体
チップ１をそのはんだ４が上記加工はんだ８に一致する
ごとく載置したのち、低融点はんだ９の融点よりもわず
かに高い温度で加熱して加工はんだ８の上部に溶融接続
すると、図３(d) に示すごとく電子回路装置を得ること
ができる。上記実施例では上記加工はんだ８の形状は直
径０．１５ｍｍ、長さ０．３ｍｍの円柱を用いている。
また上記加工はんだ８の回路基板２への供給方法は、電
極５のパターンに対応して穴の開いたステンレスマスク
を使用している。このようにして得られたはんだ接続部
は、加工はんだ８の融点が高く、体積も多いため、上記
低融点はんだ７、９と接続加工する加工はんだ８の領域
が２０〜３０μｍと非常にわずかであるため、ほとんど
加工はんだである。これを温度サイクル−５５〜＋１５
０゜Ｃ、１サイクル／ｈｒ試験で寿命を評価すると、疲
労寿命は従来の鋳造はんだに比較して９５Ｐｂ−５Ｓｎ
はんだで５倍、８０Ａｕ−２０Ｓｎはんだで２倍であっ
た。同様な方法で前記図１および図２に示す電子回路装
置における封止にも適用することができる。Next, referring to FIG. 3, a method of manufacturing an electronic circuit device in which a component having a conductor pattern and a circuit board are connected by solder will be described. First, as shown in FIG. 3 (a), a board 2 made of various materials is used. The electrodes 5 are formed on the above by a method suitable for each material. For example, when the substrate 2 is made of alumina ceramic, a conductive paste such as Ag-Pb and W is printed and fired to form the electrode 5. When the conductor paste is W, Ni plating or the like is further performed to form the electrode 5. A low melting point solder, for example, Pb, is formed on the electrode 5 thus formed.
-Sn or An-Sn eutectic solder is printed by solder paste, supplied by reflow, solder balls, vacuum deposition, etc. Solder 7 by reflow and solder dip
To form a circuit board. The low melting point solder 9 is formed on the electrode 4 of the semiconductor chip 1 by the same method. Then, as shown in FIG. 3 (b), a high melting point work solder 8 is formed in which the electrode 5 has a shape corresponding to, for example, a circle, a quadrangle or a triangle. That is, the processed solder 8 is, for example, 95 wt% Pb-5 wt% Sn, 80 wt% A.
n-20 wt% Sn is molded and placed in conformity with the low melting point solder 7 on the circuit board 2. In this state, heating is performed to melt only the low melting point solder 7 and fix the processed solder 8 on the electrode 5. The working solder 8 is melted and cast, rolled into a plate shape, and then worked up to a 90 ° rolling reduction rate.
Heat treatment was carried out at 0 ° C. for 2 days in an inert atmosphere, and the tensile properties were almost the same as the properties of c ′ shown in FIG. Next, as shown in FIG. 3 (c), the semiconductor chip 1 is placed so that its solder 4 is aligned with the working solder 8 and then heated at a temperature slightly higher than the melting point of the low melting point solder 9 to work soldering. By fusion connecting to the upper part of 8, an electronic circuit device can be obtained as shown in FIG. In the above embodiment, the shape of the work solder 8 is a cylinder having a diameter of 0.15 mm and a length of 0.3 mm.
The method of supplying the processed solder 8 to the circuit board 2 uses a stainless mask having holes corresponding to the pattern of the electrodes 5. Since the solder connection portion thus obtained has a high melting point and a large volume of the working solder 8, the area of the working solder 8 to be connected to the low melting point solders 7 and 9 is as small as 20 to 30 μm. Because of this, it is mostly processed solder. This is the temperature cycle -55 to +15
When the life is evaluated by the 0 ° C, 1 cycle / hr test, the fatigue life is 95 Pb-5Sn as compared with the conventional casting solder.
It was 5 times for solder and 2 times for 80Au-20Sn solder. The same method can be applied to sealing in the electronic circuit device shown in FIGS. 1 and 2.
【００１２】[0012]
【発明の効果】本発明は、以上述べたごとく、軟らか
く、かつ延性や疲労特性のすぐれた加工はんだを用いて
半導体および部品の封止をおこなうことができるから、
簡単な構成、容易な操作により高信頼度の電子回路装置
を得ることができ、かつ今後ますます高信頼度および高
密度が要求される面付実装の分野、たとえば計算機など
の電子回路装置の高機能化に大きい貢献をすることがで
きる。As described above, according to the present invention, it is possible to seal a semiconductor and a component by using a processed solder which is soft and has excellent ductility and fatigue characteristics.
Highly reliable electronic circuit devices can be obtained with a simple configuration and easy operation, and in the field of surface mounting, where higher reliability and higher density are required in the future, for example, high-performance electronic circuit devices such as computers. It can make a great contribution to functionalization.
【図１】本発明の一実施例を示す電子回路装置の斜視図
である。FIG. 1 is a perspective view of an electronic circuit device showing an embodiment of the present invention.
【図２】図１のＡ−Ａ’断面図である。FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG.
【図３】製造過程を示す説明用断面図である。FIG. 3 is an explanatory sectional view showing a manufacturing process.
【図４】従来の電子回路装置を示す斜視図である。FIG. 4 is a perspective view showing a conventional electronic circuit device.
【図５】本発明にかかる加工はんだと従来のはんだとの
引張特性図である。FIG. 5 is a tensile characteristic diagram of a processed solder according to the present invention and a conventional solder.
【図６】本発明にかかる加工はんだと従来の鋳造はんだ
との組織を示す図面に代わる写真である。FIG. 6 is a photograph replacing a drawing showing the structures of a processed solder according to the present invention and a conventional cast solder.
【図７】本発明にかかるＰｂ−Ｓｎ合金の状態図であ
る。FIG. 7 is a phase diagram of a Pb-Sn alloy according to the present invention.
【図８】Ｐｂ−Ｉｎ合金の状態図である。FIG. 8 is a phase diagram of a Pb-In alloy.
【図９】Ｐｂ−Ｓｂ合金の状態図である。FIG. 9 is a phase diagram of a Pb-Sb alloy.
１…半導体チップ、２…回路基板、３、７…はんだ、
４、５…電極、６、８、２６…加工はんだ、９、２３…
低融点はんだ、１０…セラミック基板、１１…金メッ
キ、１２…メタライズ層、１３…半導体素子、１４…内
部リード、１５…ワイヤ、１６…封止キャップ、１７…
封止部、１８…セラミックパッケージ、１９…抵抗体、
２０…はんだシート、２１…硬化フラックスあるいは高
融点はんだ、２２…ガラス板、２４…接続用はんだ、２
５…キャップ。1 ... Semiconductor chip, 2 ... Circuit board, 3, 7 ... Solder,
4, 5 ... Electrodes, 6, 8, 26 ... Processed solder, 9, 23 ...
Low melting point solder, 10 ... Ceramic substrate, 11 ... Gold plating, 12 ... Metallization layer, 13 ... Semiconductor element, 14 ... Internal lead, 15 ... Wire, 16 ... Sealing cap, 17 ...
Sealing part, 18 ... Ceramic package, 19 ... Resistor,
20 ... Solder sheet, 21 ... Curing flux or high melting point solder, 22 ... Glass plate, 24 ... Connection solder, 2
5 ... Cap.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂口 勝 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 村田 旻 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 廣田 和夫 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsu Sakaguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Institute of Industrial Science (72) Inventor Murata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Production Technology Research Laboratory (72) Inventor Kazuo Hirota, 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture
Claims (1)
キャップで封止する電子回路基板において、上記回路基
板と、キャップとの間に低融点のはんだを介して高融点
の圧延し熱処理した加工はんだを介挿し、上記低融点の
はんだを溶融によって回路基板上の部品を封止するよう
に構成したことを特徴とする電子回路装置。1. An electronic circuit board for sealing a component on a circuit board having a metallization with a cap, a processed solder obtained by rolling and heat-treating a high melting point via a low melting point solder between the circuit board and the cap. An electronic circuit device, characterized in that a component on a circuit board is sealed by melting the above-mentioned low melting point solder by melting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4125018A JPH088408B2 (en) | 1992-05-18 | 1992-05-18 | Electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4125018A JPH088408B2 (en) | 1992-05-18 | 1992-05-18 | Electronic circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59208072A Division JPS6187396A (en) | 1984-10-05 | 1984-10-05 | Manufacture of electronic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05275553A true JPH05275553A (en) | 1993-10-22 |
| JPH088408B2 JPH088408B2 (en) | 1996-01-29 |
Family
ID=14899827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4125018A Expired - Lifetime JPH088408B2 (en) | 1992-05-18 | 1992-05-18 | Electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088408B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007067400A (en) * | 2005-08-30 | 2007-03-15 | Commissariat A L'energie Atomique | Method of covering member, particularly electric or electronic member, using improved solder seam |
| WO2020225852A1 (en) * | 2019-05-07 | 2020-11-12 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
-
1992
- 1992-05-18 JP JP4125018A patent/JPH088408B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007067400A (en) * | 2005-08-30 | 2007-03-15 | Commissariat A L'energie Atomique | Method of covering member, particularly electric or electronic member, using improved solder seam |
| WO2020225852A1 (en) * | 2019-05-07 | 2020-11-12 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
| TWI740470B (en) * | 2019-05-07 | 2021-09-21 | 日商三菱電機股份有限公司 | Semiconductor device and manufacturing method thereof |
| TWI741965B (en) * | 2019-05-07 | 2021-10-01 | 日商三菱電機股份有限公司 | Semiconductor device and manufacturing method thereof |
| TWI743018B (en) * | 2019-05-07 | 2021-10-11 | 日商三菱電機股份有限公司 | Semiconductor device and manufacturing method thereof |
| JPWO2020225852A1 (en) * | 2019-05-07 | 2021-10-21 | 三菱電機株式会社 | Semiconductor devices and their manufacturing methods |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH088408B2 (en) | 1996-01-29 |
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