TWI740468B - Overcurrent protection device and method of manufacturing the same - Google Patents

Abstract

The present disclosure relates to an overcurrent protection device. The overcurrent protection device includes a substrate, a heat insulating layer disposed on the substrate, an electrode disposed on the heat insulating layer, and a conductive layer disposed on the heat insulating layer and at least partially covering the electrode. The present disclosure also relates to a method of manufacturing an overcurrent protection device.

Description

Overcurrent protection device and manufacturing method thereof

The present invention relates to an overcurrent protection device.

Overcurrent protection device is a device that can protect circuits or electronic devices from damage caused by excessive current heating. For example, when the current passing through the fuse (or fuse) exceeds the rated current value, the fuse can be blown, breaking the circuit, and achieving the effect of protection.

The rated current of low-power (or low-power consumption) electronic devices (for example, wearable devices) is generally low, for example, about 10.0 milliamps (mA) to about 100.0 mA. How to apply the over-current protection device to low-power electronic devices is a problem that the technical field disclosed in this disclosure is desperate to solve.

An embodiment of the present disclosure relates to an overcurrent protection device, including a substrate, a thermal insulation layer provided on the substrate, an electrode provided on the thermal insulation layer, and a conductive layer provided on the thermal insulation layer and at least partially covering the electrode Floor.

An embodiment of the disclosure relates to an overcurrent protection device, which includes a substrate and a conductive layer disposed on the substrate. The conductive layer has a first section and a second section. A first part of the first section is connected to the second section, and a second part of the first section is separated from the second section to form a gap. The substrate has a recess under the notch.

An embodiment of the present disclosure relates to a manufacturing method of an overcurrent protection device, which includes providing a substrate, forming an insulating layer on the substrate, forming a conductive layer on the insulating layer, and partially removing the conductive layer.

1: Overcurrent protection device

1': Overcurrent protection device

10: substrate

10r: Depressed part

10rs: sidewall

10rm: bottom surface

11: Insulation layer

11r: Depressed part

11rs: sidewall

11rm: bottom surface

12: Electrode

13: Conductive layer

13r: gap

13s: sidewall

14: protective layer

15: Seed layer

16: terminal electrode

17: marking

61: Section

61a: part

61b: Part

62: section

101: Surface

102: Surface

103: Surface

111: Surface

112: Surface

113: Surface

131: Surface

132: Surface

h: height

s: spacing

w: width

Various aspects of at least one embodiment are discussed below with reference to the accompanying drawings, which are not intended to be drawn to scale. Where technical features in the drawings, embodiments, or any claim are accompanied by component symbols, these component symbols have been included for the sole purpose of increasing the intelligibility of the drawings, embodiments, or the scope of the patent application. Therefore, the presence or absence of element symbols is not intended to have a limiting effect on the scope of any element in the scope of the patent application. In the figures, the same or almost the same components shown in the various figures are represented by the same number. For clarity, not every component is labeled in every figure. The figures are provided for the purpose of illustration and explanation and are not regarded as one of the definitions of the limitations of the present invention. In the drawings: FIG. 1A shows a side view of an overcurrent protection device according to some embodiments of the present disclosure; FIG. 1B shows a side view of an overcurrent protection device according to some embodiments of the present disclosure; FIGS. 2A to 2 9B shows the manufacturing method of the overcurrent protection device according to some embodiments of the present disclosure.

FIG. 1A shows a side view of an overcurrent protection device 1 according to some embodiments of the present disclosure. The overcurrent protection device 1 includes a substrate 10, a heat insulating layer 11, an electrode 12, a conductive layer 13, a protective layer 14, a seed layer 15, a terminal electrode 16, and a label 17.

According to some embodiments of the present disclosure, the overcurrent protection device 1 can be applied to electronic In the device, if the current flowing through the conductive layer 13 exceeds the rated current or a predetermined current, the heat generated can cause the conductive layer 13 to be fused, thereby protecting the circuits, components, or components in the electronic device from the heat caused by the excessive current. damage. In some embodiments, the overcurrent protection device 1 can be applied to electronic devices with low power consumption (or low power consumption), such as (but not limited to) electronic bracelets, electronic watches, earphones, mobile phones, or other electronic devices. Wearable electronic devices. For example, the overcurrent protection device 1 can be applied to an electronic device with an operating current of about 10.0 milliamperes (mA) to about 100.0 mA.

In some embodiments, the substrate 10 may include (but is not limited to) borophosphosilicate glass (BPSG), undoped silicate glass (USG), silicon (silicon), silicon oxide ( silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, polyimide (PI), ABF substrate (Ajinomoto Build-up film (ABF), molding compounds, pre-impregnated composite fibers (for example, prepreg materials), combinations thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins (including fillers dispersed therein). Examples of the prepreg material may include, but are not limited to, a multilayer structure formed by stacking or laminating a plurality of prepreg materials and/or sheets. According to some embodiments of the present disclosure, the substrate 10 may be a circuit board (such as FR4). As shown in FIG. 1A, the substrate 10 has a surface 101, a surface 102 opposite to the surface 101, and a surface 103 extending between the surface 101 and the surface 102.

The thermal insulation layer 11 is provided on the surface 102 of the substrate 10. In other words, the thermal insulation layer 11 is located between the substrate 10 and the conductive layer 13. In some embodiments, the thermal insulation layer 11 may include (but is not limited to) epoxy resin (including fillers dispersed therein), silicon, or other suitable materials.

In some embodiments, the overcurrent protection device (such as the overcurrent protection device in Figure 1) Set 1) may not include a thermal insulation layer (such as the thermal insulation layer 11 in Figure 1). However, if the overcurrent protection device 1 does not include the thermal insulation layer 11, the heat generated by the current flowing through the conductive layer 13 may escape to the environment through the substrate 10. The heat is too late to accumulate, causing the current through the overcurrent protection device to reach the rated current. When current is applied, the conductive layer 13 still cannot be fused, resulting in damage to the electronic device. The present disclosure can block or reduce heat dissipation through the substrate 10 by providing an insulating layer 11 between the substrate 10 and the conductive layer 13, and ensure that the conductive layer 13 can be instantly fused when the current passing through the overcurrent protection device reaches the rated current. To protect the electronic device and reduce the risk of damage to the electronic device.

The thermal insulation layer 11 has a surface 111, a surface 112 opposite to the surface 111, and a surface 113 extending between the surface 111 and the surface 112. The surface 111 contacts the substrate 10 and the surface 112 contacts the conductive layer 13. In some embodiments, in a direction substantially perpendicular to the surface 102 of the substrate 10, the thermal insulation layer 11 may have a thickness of about 0.1 micrometer (rmicrometer, μm) to about 40.0 μm. However, this disclosure is not limited to this. In some embodiments, the thermal insulation layer 11 may have other thicknesses according to device specifications or manufacturing process requirements.

In some embodiments, the surface roughness of the thermal insulation layer 11 is greater than or equal to the surface roughness of the substrate 10. For example, the surface of the thermal insulation layer 11 (such as the surface 111 and/or the surface 112) has a roughness of about 0.3 μm to about 0.5 μm, and the surface of the substrate 10 (such as the surface 101 and/or the surface 102) has a roughness of about 0.2 μm. To a roughness of about 0.3μm. In some embodiments, the surface roughness of the surface 112 of the thermal insulation layer 11 is greater than or equal to the surface roughness of the surface 111 of the thermal insulation layer 11. In some embodiments, the surface roughness of the thermal insulation layer 11 and the surface roughness of the substrate 10 may be affected by the materials used individually, and are not limited to the specific values mentioned in this disclosure.

The electrode 12 is arranged on the heat insulating layer 11. In some embodiments, the electrodes 12 may be provided on both ends or both sides of the substrate 10. In some embodiments, the electrode 12 may have a thickness of about 1.0 μm to about 10.0 μm in a direction substantially perpendicular to the surface 102 of the substrate 10. However, This disclosure is not limited to this. In some embodiments, the electrode 12 may have other thicknesses according to device specifications or process requirements.

The conductive layer 13 is disposed on the heat insulating layer 11 and covers the electrode 12. In some embodiments, the conductive layer 13 may include (but is not limited to) copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W) , Chromium (Cr), Tin (Sn), or other metals or alloys. For example, in some embodiments, the alloy may include nickel-chromium alloys (such as nickel-chromium-aluminum, nickel-chromium-silicon), nickel-copper alloys (such as nickel-copper-manganese), and the like.

The conductive layer 13 has a surface 131 and a surface 132 opposite to the surface 131. In some embodiments, viewed from the side view of FIG. 1A, the conductive layer 13 may have a plurality of sections (not shown in FIG. 1A) separated from each other, and each section is separated or separated from each other by a gap 13r. The notch 13r has a spacing s. For example, the side walls 13s of each section are spaced from each other by s. Each section may have a width w and a height h. When viewed from a top view (as shown in FIG. 6A), the section 61 and the section 62 may be connected to each other. For example, when viewed from a top view (as shown in FIG. 6A), the conductive layer 13 has a curved pattern. However, this disclosure is not limited to this. In some embodiments, the conductive layer 13 may have any pattern. In some embodiments, the pattern of the conductive layer 13 can be designed according to device specifications or process requirements. For example, when viewed from a top view (as shown in FIG. 6A), the portion 61a of the section 61 is connected to the portion 62b of the section 62, and the portion 61b of the section 61 is separated from the section 62 to form a gap 13r.

In some embodiments, the distance s between the portions of the conductive layer 13 may be between about 10.0 μm and about 60.0 μm. In some embodiments, the width w of the conductive layer 13 may be between about 10.0 μm and about 100.0 μm. In some embodiments, the height (or thickness) h of the conductive layer 13 may be less than about 1.0 μm. In some embodiments, the height h of the conductive layer 13 may be between about 0.1 μm and about 3.0 μm. In some embodiments, when viewed from a top view (as shown in FIG. 6A), the conductive layer 13 may have a winding length between about 50.0 μm and about 3000.0 μm. In some embodiments, The height (or thickness) h, spacing s, width w, and winding length of the conductive layer 13 can be designed according to device specifications or process requirements, and are not limited to the specific values mentioned in this disclosure.

In some embodiments, the conductive layer 13 may have a resistance value of about 10 ohms (Ω) (or lower). In some embodiments, the conductive layer 13 can fuse in a short time when the conduction current is greater than its designed rated current. For example, the conductive layer 13 may fuse in about 5 seconds (or less) when its conduction current is greater than or equal to about 100 mA.

In some embodiments, photolithography and/or plating processes may be used to form the conductive layer (for example, the conductive layer 13 in FIG. 1A). For example, a patterned photoresist is formed on a substrate (such as the substrate 10 of FIG. 1A) to define the pattern of the conductive layer, and then the conductive layer material is formed on the photoresist by electroplating, and the conductive layer is filled with Into the pattern defined by the photoresist, then the photoresist is removed, leaving a patterned conductive layer. Since the photoresist needs to be deposited (or attached) on a relatively flat surface, in this embodiment, a thermal insulation layer (such as the thermal insulation layer 11 in FIG. 1A) is usually not used to avoid the rough (or uneven) surface of the thermal insulation layer. The effect of deposition or electroplating (such as affecting the uniformity of deposition or electroplating) makes the conductive layer ineffective. However, as mentioned in the previous disclosure, if the insulation layer is not used, the conductive layer may not be fused when the rated current is reached, which increases the risk of damage to the electronic device.

An embodiment of the present disclosure provides a process method (detailed in FIGS. 2A to 9B) in which the conductive layer 13 is formed by sputtering (such as vacuum sputtering) and patterned by laser etching Conductive layer. Since the process method of the present disclosure does not need to use yellow light lithography and/or electroplating process, and does not require photoresist, the conductive layer 13 can be formed on a relatively rough surface (such as the thermal insulation layer 11). Therefore, the embodiment of FIG. 1A of the present disclosure can use the heat insulating layer 11 to solve the above-mentioned problem. In addition, the resistance value of the conductive layer 13 can be dynamically (or real-time) adjusted as the cross-sectional area (such as the area formed by the width w and the height h) and the winding length change during the laser etching process, and can be precisely adjusted. It is accurately controlled within the desired range, thereby increasing the accuracy and design flexibility of the conductive layer 13. Furthermore, compared with the yellow light lithography and electroplating process, the use of laser etching to form the conductive layer 13 can increase the accuracy of the size of the conductive layer 13 (such as the width w, the spacing s, and the height h, etc.). According to some embodiments of the present disclosure, the size error of the conductive layer 13 is less than or equal to about ±2%.

On the other hand, if yellow light lithography and/or electroplating processes are used, it may be necessary to use materials with higher stability (such as gold, or other materials that are less prone to oxidation and less likely to change the resistance value) in order to maintain a higher yield. However, if a laser etching method is used to pattern the conductive layer, the resistance value can be dynamically adjusted. Therefore, even if metals with lower stability (such as aluminum, copper, or other materials that are easier to oxidize and change the resistance value) are used, the resistance value can still be adjusted dynamically. The resistance value can be adjusted to the required specifications by modifying the cross-sectional area and the winding length. Therefore, the manufacturing method of the present disclosure is not limited by the manufacturing materials. In addition, using a material with a low melting point as the conductive layer material can further reduce the rated current.

Continuing to refer to FIG. 1A, in some embodiments, during the laser etching of the conductive layer 13, the thermal insulation layer 11 under the conductive layer 13 may be partially etched, and an enlarged view of FIG. 1A is formed in the thermal insulation layer 11 The depression (or depression) 11r drawn in. The recess 11r is located below the notch 13r of the conductive layer 13. The recess 11 r is recessed into the heat insulating layer 11 from the surface 112 of the heat insulating layer 11. In other words, the recess 11r is recessed with respect to the surface 131 of the conductive layer 13.

In some embodiments, as shown in the enlarged view of FIG. 1A, the recess 11r has a bottom surface 11rm and a side wall 11rs extending between the surface 112 and the bottom surface 11rm. The bottom surface 11rm of the recess 11r is located between the surfaces 111 and 112 of the heat insulating layer 11. In some embodiments, the width of the recess 11r is about s.

In some embodiments, the sidewall 11rs of the recess 11r and the sidewall (or the sidewall of the notch) 13s of the conductive layer 13 form a continuous surface. For example, the side of the recess 11r The wall 11rs and the sidewall (or the sidewall of the notch) 13s of the conductive layer 13 form a substantially linear profile. In some embodiments, the sidewall 13s of the recess 11r may be substantially coplanar with the sidewall (or the sidewall of the notch) 13s of the conductive layer 13. In some embodiments, the sidewall 11s of the recess 11r may be substantially perpendicular to the surfaces 111 and 112 of the heat insulating layer 11. In some embodiments, the sidewall 11s of the recess 11r may be tilted relative to the surfaces 111 and 112 of the thermal insulation layer 11. In some embodiments, the bottom surface 11rm of the recess 11r may be substantially parallel to the surfaces 111 and 112 of the thermal insulation layer 11. In some embodiments, the bottom surface 11rm of the recess 11r may be a curved surface. In some embodiments, the recess 11r can ensure that the circuit (for example, the conductive layer 13) is in an insulated state, so as to avoid the occurrence of a micro short circuit phenomenon and improve the stability of the device.

The protective layer 14 is disposed on the conductive layer 13. In some embodiments, the protective layer 14 covers a portion of the surface 132 of the conductive layer 13. In some embodiments, the protective layer 14 covers, surrounds, or contacts the sidewall 13s of the conductive layer 13. A part of the protective layer 14 is accommodated or received in the recess 11r. For example, the protective layer 14 is deposited on the bottom surface 11rm of the recess 11r from the surface 132 of the conductive layer 13 through the sidewall 13s of the conductive layer 13. For example, the protective layer 14 contacts the sidewall 11rs and the bottom surface 11rm of the recess 11r. For example, a part of the protective layer 14 is located between the surfaces 111 and 112 of the thermal insulation layer 11.

In some embodiments, the protective layer 14 may include (but is not limited to) the same material as the thermal insulation layer 11. For example, epoxy resin (containing fillers dispersed therein), silicon, or other suitable materials. In some embodiments, the protective layer 14 may have a thickness ranging from about 20.0 μm to about 40.0 μm in a direction substantially perpendicular to the surface 102 of the substrate 10. However, this disclosure is not limited to this. In some embodiments, the protective layer 14 may have other thicknesses according to device specifications or process requirements.

The seed layer 15 is disposed on both ends of the substrate 10 and on the conductive layer 13. E.g. crystal The seed layer 15 surrounds the surface 103 of the substrate 10. In some embodiments, the seed layer 15 covers a portion of the surface 132 of the conductive layer 13. In some embodiments, the seed layer 15 and the protective layer 14 covering the surface 132 of the conductive layer 13 may be substantially coplanar. In some embodiments, the seed layer 15 may be disposed on the surface 101 of the substrate 10. For example, the seed layer 15 may have two parts (not shown in FIG. 1A) sandwiching both ends of the substrate 10. The seed layer 15 located at both ends of the substrate 10 covers the surface 103 of the substrate 10 and at least covers the surface 103 of the substrate 10. Part of surfaces 101 and 102. In some embodiments, the seed layer 15 located at both ends of the substrate 10 also covers the surface 113 of the thermal insulation layer 11.

The terminal electrodes 16 are arranged on both ends of the substrate 10 and on the seed layer 15. In some embodiments, the terminal electrode 16 covers a portion of the seed layer 15. In some embodiments, the terminal electrode 16 is separated from the substrate 10, the heat insulating layer 11, and the conductive layer 13 by the seed layer 15. In some embodiments, the terminal electrode 16 may be disposed on the surface 101 of the substrate 10. For example, the terminal electrode 16 may have two parts (not shown in FIG. 1A) sandwiching both ends of the substrate 10. The terminal electrodes 16 located at both ends of the substrate 10 cover the surface 103 of the substrate 10 and at least cover the surface 101 of the substrate 10. With part of 102. In some embodiments, the seed layer 15 and the terminal electrode 16 may include (but are not limited to) the materials listed above for the conductive layer 13, which will not be repeated here.

FIG. 1B shows a side view of an overcurrent protection device 1'according to some embodiments of the present disclosure. The overcurrent protection device 1'of FIG. 1B is similar to the overcurrent protection device 1 of FIG.

The thermal insulation layer 11 of the overcurrent protection device 1'has several parts (not shown in FIG. 1A), and the sidewalls 11s of each part are spaced from each other by s. The side wall 11s extends between the surfaces 111 and 112 of the heat insulating layer 11.

The substrate 10 of the overcurrent protection device 1'has a recessed portion (or recessed portion) 10r. The recess 10 r is located below the notch of the conductive layer 13. The recess 10r is recessed from the surface 102 of the substrate 10 trap. In other words, the recessed portion 10r is recessed with respect to the surface 111 of the heat insulating layer 11.

In some embodiments, as shown in the enlarged view of FIG. 1B, the recess 10r has a bottom surface 10rm and a sidewall 10rs extending between the surface 102 and the bottom surface 10rm of the substrate 10. The bottom surface 10rm of the recess 10r is located between the surfaces 101 and 102 of the substrate 10. In some embodiments, the width of the recess 10r is about s.

In some embodiments, the sidewall 10rs of the recess 10r and the sidewall 11s of the heat insulating layer 11 form a continuous surface. For example, the side wall 10rs of the recessed portion 10r and the side wall 11s of the heat insulating layer 11 form a substantially linear profile. In some embodiments, the sidewall 10s of the recess 10r may be substantially coplanar with the sidewall 11s of the thermal insulation layer 11. In some embodiments, the sidewall 10s of the recess 10r, the sidewall 11s of the heat insulating layer 11, and the sidewall (or the sidewall of the notch) 13s of the conductive layer 13 may be substantially coplanar. In some embodiments, the sidewall 10s of the recess 10r may be substantially perpendicular to the surfaces 101 and 102 of the substrate 10. In some embodiments, the sidewall 13s of the recess 10r may be inclined with respect to the surfaces 101 and 102 of the substrate 10. In some embodiments, the bottom surface 10rm of the recess 10r may be substantially parallel to the surfaces 101 and 102 of the substrate 10. In some embodiments, the bottom surface 10rm of the recessed portion 10r may be a curved surface.

In some embodiments, the protective layer 14 covers, surrounds, or contacts the sidewall 11s of the thermal insulation layer 11. A part of the protective layer 14 is accommodated or received in the recess 10r. For example, the protective layer 14 is deposited on the bottom surface 10rm of the recess 10r from the surface 132 of the conductive layer 13 through the sidewall 13s of the conductive layer 13 and the sidewall 11s of the heat insulating layer 11. For example, the protective layer 14 contacts the sidewall 10rs and the bottom surface 10rm of the recess 10r. For example, a part of the protective layer 14 is located between the surfaces 101 and 102 of the substrate 10.

In some embodiments, the overcurrent protection device may have both a recessed portion 10r in the substrate 10 and a recessed portion 11r in the heat insulating layer 11, and it is not limited to as depicted in this disclosure. The state of the system. For example, in some embodiments, the protective layer 14 may partially extend to the substrate 10 and partially extend to the thermal insulation layer 11. For example, in some embodiments, the insulation layer 11 may have side walls 11 s, wherein the two side walls 11 s have different depths in a direction substantially perpendicular to the surface 112 of the insulation layer 11. In some embodiments, the configuration of the recessed portion 10r and the recessed portion 11r can be designed according to device specifications or process requirements.

2A to 9B show a method of manufacturing an overcurrent protection device according to some embodiments of the disclosure. In some embodiments, Figure 2B, Figure 3B, Figure 4B, Figure 5B, Figure 6B, Figure 7B, Figure 8B and Figure 9B are Figure 2A, Figure 3A, Figure 4A, Figure 5A, Figure 6A, Figure 7A, Figure 8A and the cross-sectional view of the structure of FIG. 9A cut along the line AA'. According to some embodiments of the present disclosure, the manufacturing method disclosed in FIGS. 2A to 9B can be used to manufacture the overcurrent protection device 1 or 1'as shown in FIG. 1A or FIG. 1B. According to some embodiments of the present disclosure, the manufacturing method disclosed in FIGS. 2A to 9B can also be used to manufacture other overcurrent protection devices.

2A and 2B, a substrate 10 is provided. The substrate 10 has a surface 101, a surface 102 opposite to the surface 101, and a surface 103 extending between the surface 101 and the surface 102. In some embodiments, the scribe line may be formed in the substrate 10 by means of laser cutting. In some embodiments, the depth of the scribe channel may account for about 20% to about 60% of the thickness of the substrate 10.

3A and 3B, a heat insulating layer 11 is formed on the surface 102 of the substrate 10. The thermal insulation layer 11 has a surface 111, a surface 112 opposite to the surface 111, and a surface 113 extending between the surface 111 and the surface 112. In some embodiments, the thermal insulation layer 11 may be formed by coating, lamination, or other suitable methods.

4A and 4B, an electrode 12 is formed on the heat insulating layer 11. In some embodiments, the electrode 12 may be formed by sputtering, electroless plating, plating, printing or other feasible methods.

5A and 5B, a conductive layer 13 is formed on the heat insulating layer 11. In some embodiments, the conductive layer 13 can be conformally formed on the heat insulating layer 11 and the electrode 12. In some embodiments, the conductive layer 13 may be formed by sputtering.

6A and 6B, part of the conductive layer 13 is removed to obtain the desired pattern and resistance of the conductive layer 13. In some embodiments, part of the conductive layer 13 (or patterned conductive layer 13) can be removed by laser etching.

In some embodiments, in the steps of FIGS. 6A and 6B, the resistance value of the conductive layer 13 can be measured at the same time to adjust the shape of the conductive layer 13 in real time. For example, first patterning can be performed, and then the resistance value of the conductive layer 13 is measured, and then the pattern (or shape) of the conductive layer 13 can be fine-tuned according to the measured resistance value to obtain an accurate resistance value. In some embodiments, the above steps of measuring and fine-tuning the pattern can be repeated multiple times.

In some embodiments, the pattern of the conductive layer 13 can also be formed by dry etching, ion bumping, or other feasible methods. For example, the patterning of the conductive layer 13 by laser etching combined with other possible etching methods is not limited to the methods listed in this disclosure.

Viewed from the top view of FIG. 6A, the patterned conductive layer 13 may have a curved pattern. For example, the patterned conductive layer 13 may have a pattern bent and extended on the heat insulating layer 11. In some embodiments, in the steps from FIG. 5A to FIG. 6A, the height, spacing, width, and winding length of the conductive layer 13 can be designed according to device specifications or process requirements.

In some embodiments, as described above, during the laser etching of the conductive layer 13, the heat insulating layer 11 located under the conductive layer 13 may be partially etched, and a recess 11r is formed in the heat insulating layer 11 (refer to FIG. 6B Enlarged image). In some embodiments, if further etching through the thermal insulation layer 11 is performed, a recessed portion may also be formed in the substrate 10 (as shown in FIG. 2B).

Referring to FIGS. 7A and 7B, a protective layer 14 is formed on the conductive layer 13 to cover a part of the conductive layer 13. In some embodiments, the protective layer 14 may be formed by coating, laminating, or other suitable methods. In some embodiments, the protective layer 14 may be deposited in the recess 11r (refer to the enlarged view of FIG. 6B).

Referring to FIGS. 8A and 8B, a seed layer 15 is formed on the conductive layer 13 to cover a part of the conductive layer 13. In some embodiments, the seed layer 15 may be formed by sputtering titanium and copper (Ti/Cu) or TiW. In some embodiments, the seed layer 15 may be formed by electroless plating of Ni or Cu. In some embodiments, a mark 17 may be formed on the protective layer 14 to mark the rated current of the overcurrent protection device. In some embodiments, before forming the seed layer 15, the substrate 10 may be separated into a plurality of independent elements along the dicing line formed by laser scribing, so as to expose the surface 103 of the substrate 10.

9A and 9B, terminal electrodes 16 are formed on both ends of the substrate 10. In some embodiments, the terminal electrode 16 may be formed by electroplating Ni, Cu, Ag, Au or other metals. In some embodiments, the terminal electrode 16 may be formed by electroless plating of Ni, Pb or other metals. In some embodiments, the terminal electrode 16 may be formed by printing Cu, Ag, Au or other metals. In some embodiments, the overcurrent protection device formed by the methods shown in FIGS. 2A and 2B to 9A and 9B may be the same as the overcurrent protection device 1 shown in FIG. 1A.

It will be understood that the embodiments of the methods and devices discussed herein are not limited in application to the details of the structure and configuration of the components set forth in the following description or illustrated in the accompanying drawings. The method and device can be implemented in other embodiments and can be practiced or executed in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, the actions, elements, and features discussed in connection with any one or more embodiments are not intended to be excluded from a similar role in any other embodiment.

Moreover, the wording and terms used in this article are for descriptive purposes and should not be considered as limiting. Any reference to the embodiments or elements or actions of the systems and methods herein referred to in the singular form may also include an embodiment including a plurality of these elements, and any reference to any embodiment or element or action in the text in the plural form Any reference may also include embodiments that include only a single element. The reference in the singular or plural form is not intended to limit the currently disclosed system or method, its components, actions, or elements. The use of "include", "include", "have", "contain", "involved" and other variants in this article intends to cover the items listed thereafter and their equivalents and additional items. References to "or" can be regarded as inclusive so that the use of any term of "or" can indicate any one, more than one, and all of the described items. Any references to front and rear, left and right, top and bottom, upper and lower, and vertical and horizontal are intended to facilitate the description, and do not limit the system and method or its components to any one position or spatial orientation.

Therefore, when several aspects of at least one embodiment have been described, it should be understood that various changes, modifications, and improvements can be easily thought of by those familiar with the technology. These changes, modifications and improvements are intended to be part of the present invention and are intended to be within the scope of the present invention. Therefore, the above description and drawings are merely examples, and the scope of the present invention should be determined from the correct construction of the scope of the attached patent application and its equivalents.

1: Overcurrent protection device

10: substrate

11: Insulation layer

11r: Depressed part

11rs: sidewall

11rm: bottom surface

12: Electrode

13: Conductive layer

13s: sidewall

14: protective layer

15: Seed layer

16: terminal electrode

17: marking

101: Surface

102: Surface

103: Surface

111: Surface

112: Surface

113: Surface

131: Surface

132: Surface

h: height

s: spacing

w: width

Claims (15)

An overcurrent protection device, comprising: a substrate; an insulating layer arranged on the substrate; an electrode arranged on the insulating layer; and a conductive layer arranged on the insulating layer and at least partially covering the electrode ; Wherein the thermal insulation layer has a recess, which is located below the gap, and the side wall of the recess and the side wall of the gap are substantially coplanar. The overcurrent protection device according to claim 1, wherein the conductive layer has a first section and a second section, a first part of the first section is connected to the second section, and the first section A second part of one of the sections is separated from the second section to form a gap. The overcurrent protection device according to claim 1, wherein the heat insulating layer has a first surface facing the substrate and a second surface opposite to the first surface, and the roughness of the second surface is greater than that of the first surface The roughness of a surface. The overcurrent protection device according to claim 1, wherein the thickness of the conductive layer is less than 1.0 micrometer (micrometer, μm), and the width of the conductive layer is between 10.0 μm and 100.0 μm. The overcurrent protection device of claim 1, wherein the conductive layer is configured to melt in less than or equal to 5 seconds when a current flowing through the conductive layer is greater than or equal to 100 mA Off. An overcurrent protection device includes: a substrate; and a conductive layer disposed on the substrate, wherein the conductive layer has a first section and a second section, a first part of the first section and the The second section is connected, and a second part of the first section is separated from the second section to form a gap; wherein the substrate has a recess, which is located under the gap. The overcurrent protection device according to claim 6, further comprising: a heat insulating layer disposed between the substrate and the conductive layer. The overcurrent protection device according to claim 7, wherein the side wall of the heat insulating layer and the side wall of the notch are substantially coplanar. The overcurrent protection device according to claim 7, wherein the side wall of the heat insulating layer and the side wall of the recess are substantially coplanar. The overcurrent protection device according to claim 7, wherein the heat insulating layer has a first surface facing the substrate and a second surface opposite to the first surface, and the roughness of the second surface is greater than that of the first surface The roughness of a surface. The overcurrent protection device according to claim 6, wherein the thickness of the conductive layer is less than 1.0 micrometer Meter (micrometer, μm), and the width of the conductive layer is between 10.0 μm and 100.0 μm. The overcurrent protection device according to claim 6, wherein the conductive layer is configured to fuse in less than or equal to 5 seconds when a current flowing through one of the conductive layers is greater than or equal to 100 mA. A manufacturing method of an overcurrent protection device includes: providing a substrate; forming a heat insulating layer on the substrate; forming a conductive layer on the heat insulating layer; and partially removing the conductive layer and the heat insulating layer. The method for manufacturing an overcurrent protection device according to claim 13, wherein the partial removal of the conductive layer includes performing a laser etching operation. The method for manufacturing an overcurrent protection device according to claim 13, wherein partially removing the conductive layer includes measuring a resistance value of the conductive layer and adjusting the pattern of the conductive layer according to the resistance value.

Images