CN218336527U - Static suppressor - Google Patents

Abstract

Embodiments of the present disclosure relate to a static electricity suppressor. The static suppressor comprises a substrate, a conductive layer and a protective layer. The conductive layer is disposed on the substrate and has a gap. The protective layer is disposed on the conductive layer and defines a gas chamber over the gap.

Description

Static suppressor

Technical Field

The utility model relates to an electrostatic suppressor.

Background

When the electrostatic voltage of the electrostatic suppressor exceeds the trigger voltage, the resistance will drop sharply to conduct away the charge, thereby achieving the effect of protecting the circuit. In response to the demand of 5G/6G wireless transmission and industry 4.0, the development of electrostatic suppressor is moving toward small size. Small size components can increase the flexibility of circuit design, but are accompanied by reduced static withstand capability. In addition, the capacitance of the electrostatic suppressor is designed as low as possible to reduce signal distortion caused by high-speed signal transmission.

Therefore, it is one of the problems to be solved by the present invention to reduce the capacitance of the electrostatic suppressor while reducing the size of the device.

SUMMERY OF THE UTILITY MODEL

Embodiments of the present disclosure relate to a static electricity suppressor. The static suppressor includes a substrate, a conductive layer, and a protective layer. The conductive layer is disposed on the substrate and has a gap. The protective layer is disposed on the conductive layer and defines a gas chamber over the gap.

Embodiments of the present disclosure relate to a static electricity suppressor. The static suppressor includes a substrate and a conductive layer. The conductive layer is disposed on the substrate and has a gap. The conductive layer has a portion exposed to a gas, air, or vacuum environment.

Drawings

In the following detailed description, various aspects of embodiments of the disclosure will be discussed with reference to the accompanying drawings, which are not drawn to scale. Technical features in the drawings and detailed description are labeled with reference numerals to aid in understanding various aspects of embodiments of the disclosure, but not to limit the claims of the disclosure. In the drawings:

fig. 1A illustrates a side view of a static suppressor according to some embodiments of the present disclosure;

fig. 1B illustrates a partial side view of a static suppressor according to some embodiments of the present disclosure;

fig. 2A shows a top view of one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 2B illustrates a side view at one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 3A shows a top view of one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 3B illustrates a side view at one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 4A shows a top view of one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 4B illustrates a side view at one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 5A shows a top view of one or more steps in a method of manufacturing a static suppressor in accordance with some embodiments of the present disclosure;

fig. 5B illustrates a side view at one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 6A shows a top view in one or more steps of a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 6B illustrates a side view at one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure;

fig. 7A shows a top view of one or more steps in a method of manufacturing a static suppressor in accordance with some embodiments of the present disclosure; and

fig. 7B illustrates a side view at one or more steps in a method of manufacturing a static suppressor according to some embodiments of the present disclosure.

Detailed Description

Fig. 1A illustrates a side view of a static suppressor 1 according to some embodiments of the present disclosure. The static suppressor 1 includes a substrate 10, electrodes 11a, 11b, 11c, 11d, a conductive layer 12, a protective layer 13, a protective layer 14, a seed layer 15, and terminal electrodes 16.

The substrate 10 may include, but is not limited to, borosilicate glass (BPSG), undoped Silicate Glass (USG), silicon (silicon), silicon oxide (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), aluminum oxide (aluminum oxide), aluminum nitride (aluminum nitride), polyimide (Polyimide, PI), ABF matrix (Ajinomoto build-up film, ABF), molding compound (molding compound), pre-impregnated composite fibers (e.g., prepreg material), combinations thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins (containing fillers dispersed therein). Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepregs and/or sheets (sheets). In some embodiments, the substrate 10 may include, but is not limited to, a circuit board (e.g., FR 4).

As shown in fig. 1A, substrate 10 may include a surface 101, a surface 102 opposite surface 101, and a surface (or side surface) 103 extending between surface 101 and surface 102.

Electrodes 11a, 11b, 11c, and 11d may be disposed at both ends of surface 101 and surface 102 of substrate 10. In some embodiments, the electrodes 11a, 11b, 11c, and 11d are, but not limited to, copper (Cu), gold (Au), silver (Ag), or other metals or alloys. In some embodiments, the thickness of the electrodes 11a, 11b, 11c, and 11d may be between about 0.2 micrometers (μm) to about 30.0 μm. However, the present disclosure is not limited thereto. In some embodiments, the electrodes 11a, 11b, 11c and 11d may be disposed at other locations, may have any number, and may have other thicknesses depending on device specifications or process requirements. For example, in some embodiments, the electrodes may be disposed only at both ends of the surface of the substrate 10.

A conductive layer 12 may be disposed on the substrate 10 and the electrodes 11a, 11b. In some embodiments, the conductive layer 12 may be disposed on the surface 102 of the substrate 10. In some embodiments, the conductive layer 12 may contact the electrode 11a, the electrode 11b, and/or the surface 102 of the substrate 10. In some embodiments, the conductive layer 12 may include, but is not limited to, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), chromium (Cr), tin (Sn), or other metals or alloys. For example, in some embodiments, the alloy may include a nickel-chromium alloy (e.g., nickel-chromium-aluminum, nickel-chromium-silicon), a nickel-copper alloy (e.g., nickel-copper-manganese), and the like. In some embodiments, the conductive layer 12 may have a thickness between about 0.1 μm to about 5.0 μm. However, the present disclosure is not limited thereto. In some embodiments, the conductive layer 12 may have other thicknesses depending on device specifications or process requirements.

In some embodiments, the conductive layer 12 can include a surface 121 and a surface 122 opposite the surface 121. In some embodiments, the conductive layer 12 may have a gap 12g. In some embodiments, the gap 12g may penetrate the conductive layer 12. For example, gap 12g may extend between surface 121 and surface 122. In some embodiments, the gap 12g may have sidewalls 12gs. The sidewall 12gs may extend between the surface 121 and the surface 122.

In some embodiments, the surface 102 of the substrate 10 may be partially exposed from the conductive layer 12 through the gap 12g. In some embodiments, the surface 102 of the substrate 10 may be exposed to a gas, air, or vacuum environment through the gap 12g.

The gap 12g may have a width w2 in a direction substantially parallel to the surface 102 of the substrate 10. In some embodiments, the width w2 of the gap 12g may be less than about 15.0 μm. For example, the width w2 of the gap 12g may be between about 1.0 μm to about 15.0 μm. However, the present disclosure is not limited thereto. In some embodiments, the gap 12g may have other widths depending on device specifications or process requirements.

In some embodiments, the conductive layer 12 may include a portion 12a and a portion 12b that are separated from each other by a gap 12. For example, portion 12a may not contact portion 12b. For example, portion 12a may be unconnected to portion 12b. For example, as can be seen from the top view of fig. 4A, a gap 12g may separate the portion 12a and the portion 12b. In some embodiments, when the electrostatic Voltage of the electrostatic suppressor 1 does not exceed the Trigger Voltage (Trigger Voltage), the portion 12a and the portion 12b may be electrically insulated from each other. In some embodiments, the gap 12g may have a straight line pattern as shown in fig. 4A. However, the present disclosure is not limited thereto. In some embodiments, the gap 12g may have other patterns depending on device specifications or process requirements.

The protective layer 13 may be disposed on the surface 122 of the conductive layer 12. In some embodiments, the protective layer 13 may contact the surface 122 of the conductive layer 12. In some embodiments, the conductive layer 12 may be partially exposed from the protective layer 13. For example, the protective layer 13 may not cover at least a portion of the conductive layer 12. In some embodiments, the protective layer 13 may include, but is not limited to, a ceramic material, a glass material, or a polymer material. In some embodiments, the protection layer 13 may include, but is not limited to, a photoresist, such as a dry film photoresist or other glass transition temperature (Tg) and high toughness material.

In some embodiments, the protection layer 13 may include a surface 131 and a surface 132 opposite to the surface 131. In some embodiments, the surface 131 may contact the surface 122 of the conductive layer 12. In some embodiments, the protective layer 13 may have sidewalls 13gs. The sidewall 13gs may extend between the surface 131 and the surface 132. In some embodiments, the sidewall 13gs may be or may define a sidewall of the plenum 13g.

The protective layer 14 may be disposed on the protective layer 13. In some embodiments, protective layer 14 may contact surface 132 of protective layer 13. In some embodiments, the protective layer 14 does not contact the conductive layer 12. In some embodiments, the protective layer 13 may separate the protective layer 14 from the conductive layer 12. In some embodiments, the protective layer 13 may be located between the protective layer 14 and the conductive layer 12.

In some embodiments, the protective layer 14 may include, but is not limited to, a ceramic material, a glass material, or a polymer material. In some embodiments, the protective layer 14 may include, but is not limited to, a photoresist, such as a wet film photoresist (or liquid photoresist). In some embodiments, the protective layer 13 and the protective layer 14 may be of the same material. In some embodiments, protective layer 13 and protective layer 14 may be of different materials. In some embodiments, the protective layer 13 and the protective layer 14 may be formed in the same step. For example, the protective layer 13 and the protective layer 14 may be integrally formed.

The protective layer 13 and the protective layer 14 may define a gas chamber 13g of the electrostatic suppressor 1. The air chamber 13g may contain gas, air or may be evacuated. The air chamber 13g may be located above the gap 12g. The air chamber 13g and the gap 12g are in gas communication with each other. In the present disclosure, the gap 12g is formed in the conductive layer 12, and the air chamber 13g is above the conductive layer 12. However, since the gas chamber 13g and the gap 12g can be in gas communication with each other, the gap 12g and the gas chamber 13g can also be regarded together as a gas chamber of the static electricity suppressor 1. In some embodiments, the gas chamber of the electrostatic suppressor 1 is an internal space surrounded by the substrate 10, the conductive layer 12, the protective layer 13, and the protective layer 14.

In some embodiments, the surface 102 of the substrate 10 may be exposed to a gas, air, or vacuum environment in the plenum 13g through the gap 12g. In some embodiments, the protective layer 13 may define the volume of the gas cell 13g during processing to ensure that the conductive layer 12 has sufficient space for electrostatic discharge. In some embodiments, the protective layer 13 may define sidewalls 13gs of the gas cell 13g, while the protective layer 14 may define the top of the gas cell 13g. For example, the protective layer 14 may cover the gas cell 13g.

In some embodiments, the protective layer 13 may define a width w1 of the gas cell 13g in a direction substantially horizontal to the surface 102 of the substrate 10. In some embodiments, the width w1 may be greater than the width w2 of the gap 12g.

Seed layers 15 may be disposed on both ends of the substrate 10 and on the conductive layer 12. In some embodiments, the seed layer 15 may cover a portion of the surface 122 of the conductive layer 12.

Terminal electrodes 16 may be disposed at both ends of substrate 10 and on seed layer 15. In some embodiments, seed layer 15 and terminal electrode 16 may include, but are not limited to, the materials listed above for conductive layer 12, and are not described herein.

Fig. 1B illustrates a partial side view of a static-electricity suppressor according to some embodiments of the present disclosure. In some embodiments, the partial side view shown in fig. 1B may be a partial side view of the static suppressor 1 of fig. 1A. Herein, the same or similar components are denoted by the same symbols.

In some embodiments, the surface 102 of the substrate 10 may have a portion 102a, a portion 102b, and a portion 102c. In some embodiments, portion 102a may be convex relative to portion 102c. In some embodiments, portion 102c may be recessed relative to portion 102a in the direction of surface 101. In some embodiments, portion 102b may extend between portion 102a and portion 102c. In some embodiments, portion 102b may be substantially perpendicular to portion 102a and/or portion 102c. In some embodiments, the portion 102c may be exposed to the gas, air, or vacuum environment in the plenum 13g through the gap 12g.

In some embodiments, the gap 12g of the conductive layer 12 can have sidewalls 12gs. The sidewall 12gs may extend between the surface 121 and the surface 122 of the conductive layer 12. In some embodiments, the sidewall 12gs may be exposed to a gas, air, or vacuum environment in the plenum 13g.

In some embodiments, oxide 12o may be formed on the sidewalls 12gs of the gap 12g. In some embodiments, the thermal energy generated by the laser etching removal of the conductive layer 12 can oxidize the conductive layer 12, forming an oxide at the edges of the conductive layer 12. For example, in some embodiments, the oxide may comprise an oxide of the conductive layer 12. In some embodiments, oxide may be formed along the sidewalls 12gs of the gap 12g. In some embodiments, the oxide 12o may completely or partially cover the sidewalls 12gs. In some embodiments, the oxide 12o may be exposed to a gas, air, or vacuum environment in the gas chamber 13g. In some embodiments, the oxide 12o may avoid shorting of the conductive layer 12.

In some embodiments, the gap 12g may be recessed from the conductive layer 12 down to the substrate 10. In some embodiments, the sidewalls 12gs of the gap 12g may be substantially coplanar with the portion 102b of the surface 102 of the substrate 10. In some embodiments, the sidewall 12gs of the gap 12g and the portion 102b of the surface 102 of the substrate 10 may form a continuous surface.

According to some embodiments of the present disclosure, the present disclosure provides the static electricity suppressor 1 having the gas chamber 13g. Since the dielectric constant of the air chamber 13g is lower than that of the polymer material, the electrostatic suppressor 1 provided by the present disclosure can achieve a lower capacitance value compared to an electrostatic suppressor not including the air chamber 13g (its conductive layer is usually covered by the polymer material). For example, when the electrostatic voltage of the electrostatic suppressor 1 exceeds the trigger voltage, plasma can be generated in the gas chamber 13g, so that the charges can be conducted away, and the effect of suppressing the electrostatic discharge impact in the air discharge manner is achieved.

Compared with the electrostatic suppressor not including the gas cell 13g, the electrostatic suppressor 1 has a lower trigger voltage, a lower clamping voltage (clamping voltage), a much lower dynamic resistance than the protected circuit and a faster response time when subjected to the electrostatic discharge shock.

According to some embodiments of the present disclosure, the capacitance of the electrostatic suppressor 1 provided by the present disclosure may be lower than 0.05 picofarad (pF), the trigger voltage may be lower than 450 volts (volts, V), and the clamping voltage is lower than about 35 volts (volts, V). At a normal operating voltage (working voltage), the leakage current (leakage current) may be less than about 0.1 microampere (μ a).

In addition, the embodiments of the present disclosure provide a processing method (detailed in fig. 2A to 7B), in which the conductive layer 12 is formed by sputtering (e.g., vacuum sputtering), and the gap 12g is formed in the conductive layer 12 by laser etching. The conductive layer 12 is formed by sputtering, so that the thickness of the conductive layer 12 can be precisely controlled. The formation of the conductive layer 12 by sputtering is not limited by the process materials, so the selectivity of the materials is high. According to some embodiments of the present disclosure, the material for sputtering may be selected from copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), chromium (Cr), tin (Sn), nichrome, nickel-copper alloy, etc. to achieve the aforementioned lower trigger voltage and clamping voltage.

In addition, compared with the photolithography process, the laser etching can increase the precision of the dimension (e.g., width w 2) of the conductive layer 12, and improve the stability of the product, thereby achieving the effects of controlling the trigger voltage and reducing the leakage current. In addition, using laser etching, oxide 12o can be formed at the edge of the conductive layer 12 at the same time, thereby avoiding shorting of the conductive layer 12. According to some embodiments of the present disclosure, the conductive layer 12 is dimensionally error less than or equal to about ± 2%.

Furthermore, in some embodiments, the embodiments of the present disclosure provide a process to introduce an alloy heat treatment technique (e.g., annealing the conductive layer 12) to improve device reliability, and the IEC61000-4-2Level 4 standard established by IEC (International electric Commission).

Fig. 2A and 2B to fig. 7A and 7B illustrate a method of manufacturing an ignition resistor according to some embodiments of the present disclosure. In some embodiments, fig. 2B, 3B, 4B, 5B, 6B, and 7B are cross-sectional views of the structures of fig. 2A, 3A, 4A, 5A, 6A, and 7A taken along a section line AA', respectively. According to some embodiments of the disclosure, the manufacturing method disclosed in fig. 2A and 2B to fig. 7A and 7B may be used to manufacture the static electricity suppressor 1 shown in fig. 1A and 1B. The manufacturing methods disclosed in fig. 2A and 2B through fig. 7A and 7B may also be used to manufacture other static suppressors according to some embodiments of the present disclosure.

Referring to fig. 2A and 2B, a substrate 10 is provided, and electrodes 11a, 11B, 11c, and 11d are formed on the substrate 10. In some embodiments, the scribe lines may be formed in the substrate 10 by laser cutting. In some embodiments, the depth of the scribe line may be a proportion of about 20% to about 60% of the thickness of the substrate 10.

In some embodiments, the electrodes 11a, 11b, 11c and 11d can be formed by sputtering, electroless plating (electroplating), plating (plating), printing (printing) or other feasible methods. In some embodiments, as shown in fig. 2B, electrodes 11a, 11B, 11c, and 11d may be disposed at both ends of surface 101 and surface 102 of substrate 10.

Referring to fig. 3A and 3B, a conductive layer 12 is formed on a substrate 10. The conductive layer 12 may cover the substrate 10 and the electrodes 11a and 11b. In some embodiments, the conductive layer 12 is conformally (conformally) formed on the substrate 10 and the electrodes 11a and 11b. In some embodiments, the conductive layer 12 can be formed by sputtering (e.g., vacuum sputtering). In some embodiments, portions of the substrate 10 and the electrodes 11a and 11b may be exposed from the conductive layer 12. However, in other embodiments, the substrate 10 and the electrodes 11a and 11b may be completely covered by the conductive layer 12.

Referring to fig. 4A and 4B, a gap 12g is formed in the conductive layer 12. In some embodiments, the surface 102 of the substrate 10 may be partially exposed from the conductive layer 12 through the gap 12g. In some embodiments, the gap 12g is recessed from the conductive layer 12 down to the substrate 10. In some embodiments, the gap 12g may be formed by removing portions of the conductive layer 12 (or patterned conductive layer 12) and/or the substrate 10 by way of laser etching. In some embodiments, the gap 12g may have substantially flat sidewalls because laser etching may form a substantially flat cut surface. As shown in fig. 4B, the portion 102B of the surface 102 of the substrate 10 and the sidewalls 12gs of the gap 12g may be substantially coplanar. In some embodiments, the portion 102b of the surface 102 of the substrate 10 and the sidewall 12gs of the gap 12g may form a continuous surface.

In some embodiments, the thermal energy generated by the laser etching removal of the conductive layer 12 can oxidize the conductive layer 12, forming an oxide (e.g., oxide 12o of FIG. 1B) at the edges of the conductive layer 12. For example, in some embodiments, the oxide may comprise an oxide of the conductive layer 12. In some embodiments, oxide may be formed along the sidewalls 12gs of the gap 12g. In some embodiments, the oxide may completely or partially cover the sidewalls 12gs.

In other embodiments, the conductive layer 12 may be patterned by dry etching (dry etching), ion bombardment (ion bumping), exposure development, printing a mask pattern, or other feasible methods.

For example, the pattern of the conductive layer 12 is defined by exposure and development, the characteristics of the device are adjusted by changing the pattern of the conductive layer 12, and after sputtering the conductive layer 12, the gap 12g is formed by stripping or etching according to the material type of the conductive layer 12.

For example, the conductive layer 12 is patterned by printing a masking coating, and after sputtering the conductive layer 12, the masking coating is stripped to create the gap 12g.

For example, the conductive layer 12 may be patterned by laser etching in combination with other etching methods that are possible, and is not limited to the methods listed in this disclosure.

After the gap 12g is formed, the portion 12a of the conductive layer 12 is separated from the portion 12b.

In some embodiments, the conductive layer 12 may be further annealed to improve stability.

Referring to fig. 5A and 5B, a protective layer 13 is formed on the conductive layer 12. In some embodiments, the protective layer 13 may be formed by coating (coating), laminating (coating), or other suitable methods. In some embodiments, the conductive layer 12 may be partially exposed from the protective layer 13. For example, the protective layer 13 may not cover at least a portion of the conductive layer 12. For example, as shown in fig. 5A, the protective layer 13 may surround the periphery of the gap 12g.

In some embodiments, the sidewall 13gs of the protection layer 13 may be formed by patterning the protection layer 13 using a photolithography process. In some embodiments, the protective layer 13 may define the space for the subsequently formed gas cell 13g to ensure that the conductive layer 12 has sufficient space for electrostatic discharge. In some embodiments, the protective layer 13 may define a width w1 of the subsequently formed gas cell 13g.

Referring to fig. 6A and 6B, a protective layer 14 is formed on the protective layer 13. In some embodiments, the protective layer 14 may be formed by coating, laminating, or other suitable means. In some embodiments, protective layer 14 may cover gas chamber 13g. In some embodiments, the protective layer 14 does not contact the conductive layer 12.

In other embodiments, the protective layer 13 and the protective layer 14 may be integrally formed. In other embodiments, the protective layer 13 may be pre-aligned and adhered to the protective layer 13 by an automated device.

Referring to fig. 7A and 7B, a seed layer 15 is formed on the conductive layer 12 to cover a portion of the conductive layer 13. In some embodiments, seed layer 15 may be formed by sputtering NiCr, niCrSi, nicrccu, titanium and copper (Ti/Cu) or TiW. In some embodiments, seed layer 15 may be formed by end coating silver or copper. In some embodiments, prior to forming seed layer 15, substrate 10 may be separated into a plurality of individual elements along streets formed via laser scribing to expose surface 103 of substrate 10. Thus, in some embodiments, the seed layer 15 may be formed on the surface 103 of the substrate 10.

Next, terminal electrodes 16 are formed at both ends of the substrate 10. In some embodiments, the terminal electrodes 16 may be formed by electroplating Ni, cu, ag, au, or other metals. In some embodiments, the terminal electrode 16 may be formed by electroless plating of Ni, pb, or other metals. In some embodiments, terminal electrode 16 may be formed by printing Cu, ag, au, or other metals. In some embodiments, the static electricity suppressor formed by the method shown in fig. 2A and 2B to fig. 7A and 7B may be the same as the static electricity suppressor 1 shown in fig. 1A.

The embodiments of the structures and methods discussed in this disclosure are not limited to the specific embodiments and constructions or arrangements described and illustrated in the accompanying drawings, but can be practiced or carried out in various ways.

Also, the phraseology and terminology used in the present disclosure is for the purpose of description and should not be regarded as limiting. For example, words of the singular or plural are not intended to limit the presently disclosed structures and methods. The use of "including," "comprising," "having," "containing," "involving," and the like in this disclosure, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. An "or" as used in this disclosure may be taken to indicate any of the more than one item described. Front and back, left and right, top and bottom, upper and lower, and vertical and horizontal, etc. are intended to facilitate description and should not be construed as limiting structures and methods to one position, space, or orientation.

Therefore, various alterations, modifications, and improvements will occur to those skilled in the art based upon the particular embodiments recited in the disclosure. Such alterations, modifications, and improvements are intended to be within the scope of the disclosure.

Description of the symbols

1: static suppressor

10: substrate

11a: electrode for electrochemical cell

11b: electrode for electrochemical cell

11c: electrode for electrochemical cell

11d: electrode for electrochemical cell

12: conductive layer

12a: in part

12b: in part

12g: gap

12gs: side wall

12o: oxide compound

13: protective layer

13g: air chamber

13gs: side wall

14: protective layer

15: seed layer

16: terminal electrode

101: surface of

102: surface of

102a: in part

102b: in part

102c: in part

103: surface of

121: surface of

122: surface of

131: surface of

132: surface of

AA': tangent line

w1: width of

w2: width.

Claims (11)

1. An electrostatic suppressor comprising:

a substrate;

a conductive layer disposed on the substrate and having a gap; and

a protective layer disposed on the conductive layer and defining a gas chamber over the gap.

2. The static suppressor according to claim 1, wherein said substrate has a portion exposed to a gas, air or vacuum environment in said plenum through said gap.

3. The static suppressor according to claim 1, wherein said protective layer comprises:

a first protective layer contacting the conductive layer and defining sidewalls of the gas chamber; and

and the second protective layer is arranged on the first protective layer and covers the air chamber.

4. The electrostatic suppressor of claim 1, wherein the plenum has a first width and the gap has a second width, wherein the first width is greater than the second width.

5. The electrostatic suppressor of claim 1, wherein the substrate has a surface that is substantially coplanar with sidewalls of the gap.

6. The static suppressor according to claim 5, further comprising:

an oxide on the sidewalls of the gap.

7. The static suppressor of claim 1, wherein said conductive layer has a first portion and a second portion, wherein said gap separates said first portion from said second portion.

8. An electrostatic suppressor comprising:

a substrate; and

a conductive layer disposed on the substrate and having a gap;

wherein the conductive layer has a portion exposed to a gas, air, or vacuum environment.

9. The electrostatic suppressor of claim 8, wherein the substrate has a surface that is substantially coplanar with sidewalls of the gap.

10. The electrostatic suppressor of claim 9, further comprising:

an oxide on the sidewalls of the gap.

11. The static suppressor of claim 8, wherein said conductive layer has a first portion and a second portion, wherein said gap separates said first portion from said second portion.

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