TWM653159U - Electrostatic discharge suppressor - Google Patents

Abstract

The present disclosure relates to an electrostatic discharge (ESD) suppressor. The ESD suppressor includes a substrate, a first conductive layer disposed over the substrate, a second conductive layer disposed over the substrate and spaced apart from the first conductive layer by a first gap, and a third conductive layer disposed over the substrate and spaced apart from the second conductive layer by a second gap. The ESD suppressor also includes a protection layer disposed over the first conductive layer, the second conductive layer, and the third conductive layer. The protection layer covers the first gap and the second gap. The ESD suppressor can be adjusted in terms of the number of conduction paths, the direction of the traces, and the position of the joints (or the position of the grooves or the position of the drilled holes) according to different external circuit configurations. This increases circuit design flexibility, saves space, and improves process productivity.

Description

static suppressor

The present invention relates to an electrostatic suppressor, in particular to an electrostatic suppressor having a plurality of conduction paths.

When the electrostatic voltage of the static suppressor exceeds the trigger voltage, its resistance value will drop sharply to conduct the charge away, thereby achieving the effect of protecting the circuit. In response to the needs of 5G/6G wireless transmission and Industry 4.0, static suppressors are developing in the direction of small size. Small-sized components can increase the flexibility of circuit design, but are accompanied by the problem of reduced static electricity resistance. In addition, the capacitance of the static suppressor will be designed as low as possible to reduce signal distortion caused by high-speed or high-frequency signal transmission.

Therefore, how to reduce the capacitance of the ESD suppressor while reducing the size of the component is one of the problems that the present invention aims to solve.

In order to achieve the above purpose, the present invention provides an electrostatic suppressor. The static suppressor includes a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on the substrate and spaced apart from the first conductive layer through a first gap, and a second conductive layer disposed on the substrate and passing through A third conductive layer is spaced apart from the second conductive layer by a second gap. The static suppressor also includes a protective layer disposed on the first conductive layer, the second conductive layer and the third conductive layer. The protective layer covers the first gap and the second gap.

The invention also provides an electrostatic suppressor. The electrostatic suppressor includes a substrate, a first conductive path and a second conductive path. A portion of the first conductive path is located in a drill hole penetrating the substrate. The first conductive path and the second conductive path have different triggering voltages.

Multiple conductive path diameters can be used to adjust the number of conductive path diameters, line direction, and contact position (or groove position, drilling position) according to different external circuit settings, thereby achieving the effect of improving circuit design flexibility, saving space, and improving process yield.

FIG. 1A is a cross-sectional view of an electrostatic suppressor 1 according to some embodiments of the present disclosure. The static suppressor 1 may include a substrate 10, an electrode 11a (or a first electrode 11a), an electrode 11b (a second electrode 11b), an electrode 11c (a third electrode 11c), a conductive layer 12a (or It is called the first conductive layer 12a), the conductive layer 12b (or the second conductive layer 12b), the conductive layer 12c (or the third conductive layer 12c), the protective layer 13 and the protective layer 14.

The substrate 10 may include an insulating substrate, such as a ceramic substrate, a glass substrate, a resin substrate, an insulated metal substrate, and the like. In some embodiments, the substrate 10 may include (but is not limited to) borosilicate glass (BPSG), undoped silicate glass (USG), silicon, silicon oxide ( silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), aluminum oxide (aluminum oxide), aluminum nitride (aluminum nitride), polyimide (PI), ABF substrate (Ajinomoto build-up film (ABF), molding compounds, pre-impregnated composite fibers (eg, prepreg materials), combinations thereof, or the like. Examples of molding rubbers may include, but are not limited to, epoxy resins (including fillers dispersed therein). Examples of prepregs may include, but are not limited to, multi-layer structures formed by stacking or laminating multiple prepregs and/or sheets. In some embodiments, the substrate 10 may include, but is not limited to, a circuit board (such as FR4).

The substrate 10 may include a surface 101 (or referred to as the first surface 101 ) and a surface 102 (or referred to as the second surface 102 ) opposite to the surface 101 .

The electrode 11a, the electrode 11b, and the electrode 11c may each be provided on the surface 101 of the substrate 10. The electrodes 11a, 11b, and 11c may each extend from the surface 101 to the surface 102 via a side surface of the substrate 10 (eg, surface 103 or surface 104 of FIG. 1C). The electrode 11a, the electrode 11b, and the electrode 11c may each be disposed on the surface 102 of the substrate 10. The electrodes 11a, 11b and 11c on the surface 102 of the substrate 10 can each be used as a terminal or end point for electrical connection with the circuit substrate of the external circuit.

In some embodiments, the electrodes 11a, 11b and 11c may each include (but are not limited to) copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti). ), tungsten (W), chromium (Cr), tin (Sn), or other metals or alloys. For example, in some embodiments, the alloy may include nickel-chromium alloys (eg, nickel-chromium aluminum, nickel-chromium silicon), nickel-copper alloys (eg, nickel-copper-manganese), and the like. In some embodiments, the thickness of each of electrode 11a, electrode 11b, and electrode 11c may be between about 0.2 micrometer (μm) and about 30.0 μm, such as between about 5.0 μm and about 20.0 μm. . However, the disclosure is not limited thereto.

In some embodiments, the electrodes 11a, 11b, and 11c can each be disposed at other locations according to device specifications or process requirements, can have any number, and can have other sizes according to device specifications or process requirements.

The conductive layer 12a may be disposed on the substrate 10. The conductive layer 12a may cover or contact the electrode 11a. The electrode 11a may be disposed between the surface 101 of the substrate 10 and the conductive layer 12a. The conductive layer 12b may be disposed on the substrate 10. The conductive layer 12b may cover or contact the electrode 11b. The electrode 11b may be disposed between the surface 101 of the substrate 10 and the conductive layer 12b. The conductive layer 12c may be disposed on the substrate 10. The conductive layer 12c may cover or contact the electrode 11c. The electrode 11c may be disposed between the surface 101 of the substrate 10 and the conductive layer 12c.

In some embodiments, the conductive layer 12a, the conductive layer 12b, and the conductive layer 12c may each include the materials listed above for the electrodes 11a, 11b, and 11c. In some embodiments, the thickness of each of conductive layer 12a, conductive layer 12b, and conductive layer 12c may be between about 0.1 μm and about 5.0 μm. However, the disclosure is not limited thereto. In some embodiments, the conductive layer 12a, the conductive layer 12b, and the conductive layer 12c may have other thicknesses according to device specifications or process requirements.

The conductive layer 12a can be spaced apart from the conductive layer 12b through the gap 12r1 (also referred to as the first gap 12r1). For example, conductive layer 12a may not contact or be connected to conductive layer 12b. The conductive layer 12c can be spaced apart from the conductive layer 12b through the gap 12r2 (or called the second gap 12r2). For example, conductive layer 12c may not contact or be connected to conductive layer 12b.

In some embodiments, when the electrostatic voltage of the static suppressor 1 does not exceed the trigger voltage, the conductive layer 12a and the conductive layer 12b can be electrically insulated from each other, and the conductive layer 12c and the conductive layer 12b can be electrically insulated from each other. In some embodiments, gaps 12r1 and 12r2 may have a straight line pattern as shown in FIG. 1C. However, the disclosure is not limited thereto. In some embodiments, the gaps 12r1 and 12r2 may have other patterns according to device specifications or process requirements.

In some embodiments, the surface 101 of the substrate 10 may be partially exposed from between the conductive layer 12a and the conductive layer 12b through the gap 12r1. In some embodiments, the surface 101 of the substrate 10 may be exposed to a gas, air, or vacuum environment through the gap 12r1. In some embodiments, the surface 101 of the substrate 10 may be partially exposed from between the conductive layer 12b and the conductive layer 12c through the gap 12r2. In some embodiments, the surface 101 of the substrate 10 may be exposed to a gas, air, or vacuum environment through the gap 12r2.

In a direction substantially parallel to the surface 101 and/or the surface 102 of the substrate 10 , the gap 12r1 and the gap 12r2 may each have a width less than about 15.0 μm, for example, between about 1.0 μm and about 15.0 μm. For example, the minimum distance between conductive layer 12a and conductive layer 12b may be between about 1.0 μm and about 15.0 μm. For example, the minimum distance between conductive layer 12c and conductive layer 12b may be between about 1.0 μm and about 15.0 μm. However, the disclosure is not limited thereto. In some embodiments, the gap 12r1 and the gap 12r2 may each have other widths according to device specifications or process requirements.

In some embodiments, as shown in the enlarged view of FIG. 1B , gap 12r2 may be recessed downward into substrate 10 (the same is true for gap 12r1 ). The gap 12r2 may have a side wall s1 and a side wall s2. Sidewall s1 is part of conductive layer 12b and sidewall s2 is part of substrate 10 . The side walls s1 and s2 may be substantially coplanar. The side walls s1 and s2 may form a continuous surface.

In some embodiments, oxide 12o may be formed in gap 12r2. Oxide 12o may be formed on sidewall s1 of gap 12r2 or form sidewall s1. In some embodiments, gap 12r2 may be formed by laser etching (as shown in FIGS. 5A and 5B ), and in the process of removing a portion of the conductive layer to form conductive layer 12b and conductive layer 12c, the heat energy generated may oxidize the conductive layer, and oxide may be formed at the edges of conductive layer 12b and conductive layer 12c. For example, in some embodiments, oxide 12o may include oxides of conductive layer 12b and conductive layer 12c. In some embodiments, oxide 12o may be formed along sidewall s1 of gap 12r2. In some embodiments, oxide 12o may completely or partially cover sidewall s1. In some embodiments, the oxide 12o can be exposed to a gas, air or vacuum environment. In some embodiments, the oxide 12o can prevent the conductive layer 12b and the conductive layer 12c from short-circuiting.

The protective layer 13 can be disposed on the conductive layer 12a, the conductive layer 12b and the conductive layer 12c. The protective layer 13 can cover the gap 12r1 and the gap 12r2. The protective layer 13 can define an air chamber on the gap 12r1, which contains a gas, air or vacuum environment. The protective layer 13 can define an air chamber on the gap 12r2, which contains a gas, air or vacuum environment.

In some embodiments, the triggering voltage and/or the clamping voltage of the conduction path (such as the conduction path I1 or the conduction path I2 in FIG. 1C ) of the static suppressor 1 can be changed according to the electrical requirements.

For example, when performing a laser etching operation (as shown in FIG. 5A and FIG. 5B ) to form the gap 12r1 and the gap 12r2 , a process parameter (such as laser power, laser power, etc.) of the laser etching operation can be adjusted. (processing time, pulse frequency, gap width, gap depth, gap length, gap pattern, etc.), changing the trigger voltage and/or clamping voltage of the conduction path of the electrostatic suppressor 1.

For example, when setting the protective layer 13 (as shown in FIGS. 6A and 6B ), the atmospheric pressure in the gap 12r1 and/or the gap 12r2 can be adjusted by adjusting the pressing speed and/or the pressing pressure of the protective layer 13. Then the trigger voltage and/or clamping voltage of the conduction path of the static suppressor 1 is changed.

For example, before the gap 12r1 and the gap 12r2 are covered with the protective layer 13 (as shown in FIG. 6A and FIG. 6B ), a discharge dielectric may be filled in the gap 12r1 and/or the gap 12r2 to adjust the dielectric constant in the gap 12r1 and/or the gap 12r2, thereby changing the triggering voltage and/or the clamping voltage of the conduction path of the electrostatic suppressor 1. The discharge dielectric may include substances with different dielectric constants and may be gas, solid, liquid, etc. The discharge dielectric may include (but is not limited to) helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), hydrogen (H ₂ ), mercury (Hg), polyethylene (PE), polystyrene (PS), syndiotactic polystyrene (SPS), porcelain, polytetrafluoroethylene (PTFE), liquid crystal polymer (LCP), polyvinyl chloride (PVC), polycyclohexylenedimethylene terephthalate (PCT), polyphenylene sulfide (PS), thermoplastic elastomer (TPE), or a combination of one or more thereof.

In some embodiments, the protective layer 13 may include (but is not limited to) ceramic materials, glass materials or polymer materials. In some embodiments, the protective layer 13 may include (but is not limited to) photoresist, such as dry film photoresist or other materials with high glass transition temperature (glass transition temperature, Tg) and toughness.

The protective layer 14 may be disposed on the protective layer 13. The protective layer 14 may contact the protective layer 13. In some embodiments, the protective layer 14 may include (but not limited to) a ceramic material, a glass material, or a polymer material. In some embodiments, the protective layer 14 may include (but not limited to) a photoresist, such as a wet film photoresist (or a liquid photoresist). In some embodiments, the protective layer 13 and the protective layer 14 may have the same material. In some embodiments, the protective layer 13 and the protective layer 14 may have different materials. In some embodiments, in a direction substantially perpendicular to the surface 101 and/or the surface 102 of the substrate 10, the protective layer 13 and the protective layer 14 may each have a thickness greater than about 20.0 μm. In some embodiments, the protective layer 13 and the protective layer 14 can be formed in the same step. For example, the protective layer 13 and the protective layer 14 can be formed in one piece.

FIG. 1C shows a top view of a part of the static suppressor 1 according to some embodiments of the present disclosure. In order to present the relationship between the components more clearly, FIG. 1C omits the protective layer 13 and the protective layer 14 of FIG. 1A .

The substrate 10 may include a surface 103 (also called a third surface 103) extending between the surface 101 and the surface 102 (labeled in FIG. 1A) and a surface 104 (also called a fourth surface) extending between the surface 101 and the surface 102. Surface 104). Surface 103 may be opposite surface 104 . In some embodiments, surface 103 and surface 104 may each comprise a side, sides, periphery or boundary of static suppressor 1 .

In some embodiments, the substrate 10 may have a groove 11ah (or referred to as a first groove 11ah) that is recessed from the surface 103 to the inside of the substrate 10. The substrate 10 may have a groove 11bh (or referred to as a second groove 11bh) that is recessed from the surface 104 to the inside of the substrate 10. The substrate 10 may have a groove 11ch (or referred to as a third groove 11ch) that is recessed from the surface 103 to the inside of the substrate 10. The grooves 11ah, 11bh, and 11ch may be located on the side, side, periphery, or boundary of the electrostatic suppressor 1. In some embodiments, the diameter (or width, or maximum width) of each of the grooves 11ah, 11bh, and 11ch may be between about 0.1 millimeters (milimeter, mm) and about 0.2 mm. However, the present disclosure is not limited thereto.

In some embodiments, the grooves 11ah, the grooves 11bh and the grooves 11ch can each be disposed at other locations, have any number, and can have other sizes according to the device specifications or process requirements.

In some embodiments, a coating film 16a (or first coating film 16a) may be formed on the electrode 11a. A coating film 16b (or called a second coating film 16b) may be formed on the electrode 11b. A coating film 16c (or third coating film 16c) may be formed on the electrode 11c. In some embodiments, the coating films 16a, 16b, and 16c can each be electroplated with nickel/gold (Ni/Au), nickel/lead/gold (Ni/Pb/Au), or nickel/lead (Ni/Pb), etc. formed from metal. In some embodiments, the thickness of each of the coating films 16a, 16b, and 16c may be between about 5.0 μm and about 20.0 μm. However, the disclosure is not limited thereto.

In some embodiments, conductive layers 12a, 12b and 12c are formed on the electrodes 11a, 11b and 11c (as shown in FIGS. 5A and 5B). The plated films 16a, 16b and 16c are formed on the electrodes 11a, 11b and 11c after the protective layer 14 is provided (as shown in FIGS. 7A and 7B). Therefore, the protected layers 14 of the electrodes 11a, 11b and 11c are The covered part is not plated, but is provided with conductive layer 12a, conductive layer 12b and conductive layer 12c respectively.

In some embodiments, the electrostatic suppressor 1 may have a conductive path I1 (or referred to as the first conductive path I1) or a conductive path I2 (or referred to as the second conductive path I2). The conductive layer 12a and the conductive layer 12b are configured to serve as the conductive path I1. The conductive layer 12c and the conductive layer 12b are configured to serve as the conductive path I2. As mentioned above, in some embodiments, the triggering voltages of the conductive path I1 and the conductive path I2 may be different from each other by adjusting parameters, changing pressure, changing discharge dielectrics, etc. The clamping voltages of the conductive path I1 and the conductive path I2 may be different from each other.

FIG1D is a top view of an ESD suppressor 1 according to some embodiments of the present disclosure. In some embodiments, FIG1A is a cross-sectional view of the ESD suppressor 1 of FIG1D along the tangent line AA'. FIG1E and FIG1F are side views of the ESD suppressor 1 of FIG1D viewed from different sides.

Referring to FIGS. 1D , 1E and 1F , the electrode 11 a and the electrode 11 c may extend from the surface 101 to the surface 102 via the surface 103 . Each of the electrode 11a and the electrode 11c may have a portion disposed on the surface 103 of the substrate 10 . The electrode 11a may have a portion disposed on the groove 11ah. The electrode 11c may have a portion disposed on the groove 11ch. Electrode lib may extend from surface 101 through surface 104 onto surface 102 . The electrode 11b may have a portion disposed on the surface 104 of the substrate 10 . The electrode 11b may have a portion disposed on the groove 11bh.

2A, 2B, 2C, 2D, 2E, and 2F are top views of an ESD suppressor according to some embodiments of the present disclosure, which are similar to the top view of the ESD suppressor 1 in FIG1D , except that FIG2A, 2B, 2C, 2D, 2E, and 2F depict electrodes 11a, 11b, 11c, grooves 11ah, 11bh, and 11ch in different positions and shapes.

As shown in FIG. 2A , the grooves 11ah , 11bh and 11ch are located within the surface 103 and the surface 104 , that is, located on the side, sides, periphery or within the boundary of the static suppressor 1 . In this embodiment, the grooves 11ah, the grooves 11bh and the grooves 11ch may each be referred to as drilling holes penetrating the substrate 10. In some embodiments, the drilling design allows the electrodes on the upper and lower surfaces of the substrate 10 (surface 101 and surface 102 in Figure 1A) to form the shortest conductive path, reducing impedance and preventing energy loss during electrostatic conduction from affecting the startup and shutdown of the static suppressor. .

As shown in FIG. 2B , the grooves 11ah and 11ch may be located on the surface 103 or exposed from the surface 103 . In some embodiments, drilling designs and groove designs can be used together.

As shown in FIG. 2C and FIG. 2D , the electrostatic suppressor may further include an electrode 11d (or referred to as a fourth electrode 11d) and a groove 11dh (or referred to as a fourth groove 11dh, which may also be a drill hole design and referred to as a drill hole penetrating the substrate 10). The electrostatic suppressor may further include an electrode 11e (or referred to as a fifth electrode 11e) and a groove 11eh (or referred to as a fifth groove 11eh, which may also be a drill hole design and referred to as a drill hole penetrating the substrate 10). The more electrodes and grooves there are, the more conductive paths may be formed.

As shown in FIG. 2E , the electrodes 11a and 11d of the static suppressor can have curved patterns to form different conduction directions. As shown in Figure 2F, the curved electrode of Figure 2E can also use both a drilling design and a groove design.

According to some embodiments of the present disclosure, the electrostatic suppressor 1 provided by the present disclosure has a plurality of conductive path diameters. Compared with the electrostatic suppressor with a single conductive path diameter, the electrostatic suppressor 1 provided by the present disclosure can adjust the number of conductive path diameters, line direction, and contact position (or groove position, drilling position) according to the settings of different external circuits. Therefore, the circuit design flexibility is improved, space is saved, and the process yield is improved.

Furthermore, the gap 12r1 and the gap 12r2 can be air chambers. When the electrostatic voltage of the electrostatic suppressor 1 exceeds the trigger voltage, plasma can be generated in the air chamber, so that the charge can be conducted away, so as to suppress the electrostatic discharge impact by air discharge. Effect. Compared with an electrostatic suppressor that does not include an air chamber, when subjected to an electrostatic discharge impact, the electrostatic suppressor 1 has a lower trigger voltage, a lower clamping voltage, a much lower dynamic resistance than the protected circuit, and a faster response time. .

In addition, one embodiment of the present disclosure provides a process method (detailed in FIGS. 3A to 7B ), which is formed through CCD (charge-coupled device) alignment printing, sputtering (such as vacuum sputtering), etc. Between the electrode and the conductive layer, a gap is formed in the conductive layer by laser etching, and a protective layer is formed by exposure using yellow light lithography. The conductive layer is formed by sputtering, and the thickness of the conductive layer can be precisely controlled. Forming the conductive layer by sputtering is not limited by process materials, so the material selectivity is high. According to some embodiments of the present disclosure, sputtering materials may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), chromium (Cr), tin (Sn), nickel-chromium alloy, nickel-copper alloy, etc., to achieve the aforementioned lower trigger voltage and clamping voltage.

Compared with the yellow photolithography process, the use of laser etching can increase the accuracy of the gap size in the conductive layer and improve the stability of the product, thus achieving the effect of controlling the trigger voltage and reducing leakage current. In addition, laser etching can be used to simultaneously form oxide at the edges of the conductive layer, thereby preventing short circuits in the conductive layer. According to some embodiments of the present disclosure, the size error of the conductive layer is less than or equal to approximately 2%.

The protective layer formed by yellow light photolithography exposure can accurately establish the air chamber to ensure that the air chamber is completely covered and provide enough space for air discharge.

Furthermore, according to some embodiments of the present disclosure, one embodiment of the present disclosure provides a process method that introduces alloy heat treatment technology (such as annealing the conductive layer) to enhance component reliability and pass reliability tests (such as the IEC61000-4-2 Level 4 standard established by the IEC (International Electoral Commission), MIL-STD-883 test, etc.).

FIG. 3A to FIG. 7B show a method for manufacturing an electrostatic suppressor according to some embodiments of the present disclosure. According to some embodiments of the present disclosure, the manufacturing method disclosed in FIG. 3A to FIG. 7B can be used to manufacture the electrostatic suppressor 1 shown in FIG. 1A. According to some embodiments of the present disclosure, the manufacturing method disclosed in FIG. 3A to FIG. 7B can also be used to manufacture other electrostatic suppressors.

Referring to FIG. 3A, FIG. 3B and FIG. 3C, FIG. 3B and FIG. 3C are side views of the structure of FIG. 3A viewed from different sides. The manufacturing method disclosed herein may include providing a substrate 10, and may form a groove 11ah, a groove 11bh and a groove 11ch in the substrate 10. In some embodiments, a drill hole may be formed in the substrate 10 (as shown in FIG. 2A). In some embodiments, the groove or the drill hole may be formed by laser drilling or other feasible methods. The size, quantity and position of the drill hole may be designed according to the device specifications (e.g., rated current, trigger voltage, clamping voltage, etc.) or process requirements.

In some embodiments, electrodes 11a, 11b, and 11c may be formed on the substrate 10. The electrodes 11a, 11b and 11c can be formed by sputtering (such as vacuum sputtering), electroless plating, plating, printing, photolithography or other feasible methods.

In some embodiments, the scribe line can be formed in the substrate 10 by laser scribe. In some embodiments, the depth of the scribe line can be about 40% to about 60% of the thickness of the substrate 10.

Referring to FIG. 4A and FIG. 4B , FIG. 4B is a cross-sectional view of the structure of FIG. 4A along the cut line AA′. The manufacturing method disclosed herein may include forming a conductive layer 12 on the electrodes 11a, 11b, and 11c. The conductive layer 12 may be formed by sputtering (such as vacuum sputtering), electroless plating, plating, printing, photolithography, or other feasible methods.

5A and 5B , FIG5B is a cross-sectional view of the structure of FIG5A along the sectional line AA′. The manufacturing method disclosed herein may include forming a gap 12r1 and a gap 12r2 in the conductive layer 12 .

In some embodiments, the gaps 12r1 and 12r2 may be formed by removing part of the conductive layer 12 (or patterned conductive layer 12) and/or the substrate 10 by laser etching. In some embodiments, since laser etching can form a substantially flat cutting surface, the gaps 12r1 and 12r2 can have substantially flat sidewalls.

In some embodiments, heat generated by removing the conductive layer 12 by laser etching may oxidize the conductive layer 12 to form an oxide (such as oxide 12o in FIG. 1B ) at the edge of the conductive layer 12. For example, in some embodiments, the oxide may include an oxide of the conductive layer 12.

In other embodiments, the pattern of the conductive layer 12 can also be formed by dry etching, ion bumping, exposure and development, masking patterns during printing, or other feasible methods.

For example, the pattern of the conductive layer 12 is defined by exposure and development, and the device characteristics are adjusted by changing the pattern of the conductive layer 12. After the conductive layer 12 is sputtered, the gap 12r1 and the gap 12r2 are produced by stripping or etching according to the material type of the conductive layer 12.

For example, the pattern of the conductive layer 12 is defined by printing a masking coating, and after the conductive layer 12 is sputter-plated, the masking coating is peeled off to generate the gap 12r1 and the gap 12r2.

For example, the conductive layer 12 can be patterned by laser etching in combination with other feasible etching methods, which are not limited to the methods listed in the present disclosure.

After the gaps 12r1 and 12r2 are formed, the conductive layers 12a, 12b, and 12c are formed.

In some embodiments, the conductive layer 12a, the conductive layer 12b and the conductive layer 12c may be further annealed to improve stability.

6A and 6B, FIG6B is a cross-sectional view of the structure of FIG6A along the tangent line AA'. The manufacturing method disclosed herein may include forming a protective layer 13 on the conductive layer 12a, the conductive layer 12b, and the conductive layer 12c. In some embodiments, the protective layer 13 may be formed by coating, lamination, or other suitable methods.

In some embodiments, the protective layer 13 may be patterned using a photolithography process. In some embodiments, the protective layer 13 may define the space of the gas chamber to be formed subsequently to ensure that the conductive layers 12a, 12b, and 12c have sufficient space for electrostatic discharge.

Referring to FIG. 7A and FIG. 7B , FIG. 7B is a cross-sectional view of the structure of FIG. 7A along the tangent line AA'. The manufacturing method disclosed herein may include forming a protective layer 14 on the protective layer 13. In some embodiments, the protective layer 14 may be formed by coating, lamination, or other suitable methods. In other embodiments, the protective layer 13 and the protective layer 14 may be formed in one piece. In other embodiments, the protective layer 14 may be pre-formed and then adhered to the protective layer 13 by automated equipment.

Next, the substrate 10 may be separated into a plurality of independent components along the scribe lines formed by laser scribing. In some embodiments, a coating film 16a, a coating film 16b, and a coating film 16c may be formed (as shown in FIG. 1C ).

The embodiments of structures and methods discussed in this disclosure are not limited to the structures or configurations described and illustrated in the embodiments and accompanying drawings, but can be practiced or performed in various ways.

In addition, the words and terms used in this disclosure are for descriptive purposes and should not be considered limiting. For example, words in the singular or plural form are not intended to limit the structures and methods currently disclosed. "Including," "including," "having," "containing," "involving," etc. used in this disclosure encompass the items listed thereafter, their equivalents, and additional items. "Or" used in this disclosure may be considered to indicate any one of more than one item being described. Front and back, left and right, top and bottom, upper and lower, and vertical and horizontal are intended to facilitate description and should not be considered to limit the structures and methods to one position, space, or direction.

Therefore, those skilled in the art will appreciate that various changes, modifications, and improvements may be made based on the specific embodiments described herein. Such changes, modifications, and improvements are still within the scope of this disclosure.

1: Electrostatic Suppressor

10:Substrate

11a: Electrode/First Electrode

11ah: Groove/First Groove

11b: Electrode/Second Electrode

11bh: Groove/Second Groove

11c:Electrode/Third Electrode

11ch: Groove/Third Groove

11dh: Groove/Fourth Groove

11eh: Groove/fifth groove

12a: Conductive layer/first conductive layer

12b: Conductive layer/second conductive layer

12c: Conductive layer/third conductive layer

12o: Oxide

12r1: gap/first gap

12r2: gap/second gap

13:Protective layer

14: Protective layer

16a:Coating/first coating

16b:Coating/second coating

16c: coating/third coating

101: Surface/First Surface

102: Surface/Second Surface

103: Surface/third surface

104: Surface/Fourth surface

AA': tangent

I1: Conductive path/first conductive path

I2: conduction path/second conduction path

s1: side wall

s2: side wall

Various aspects of the presently disclosed embodiments are discussed in the following detailed description with reference to the accompanying drawings, which are not drawn to scale. The technical features in these drawings and embodiments are marked with component symbols. These component symbols are used to help understand the various aspects of the embodiments of the present disclosure, but do not limit the scope of the new patent application of the present disclosure. In these diagrams:

1A shows a cross-sectional view of an electrostatic suppressor according to some embodiments of the present disclosure;

1B shows a partial enlarged view of an electrostatic suppressor according to some embodiments of the present disclosure;

1C shows a top view of a portion of an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 1D is a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 1E is a side view of an electrostatic suppressor according to some embodiments of the present disclosure;

1F shows a side view of an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 2A shows a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

2B shows a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

2C shows a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 2D is a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 2E shows a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

2F shows a top view of an electrostatic suppressor according to some embodiments of the present disclosure;

3A is a top view of one or more steps of a manufacturing method of a static suppressor according to some embodiments of the present disclosure;

FIG. 3B is a side view showing one or more steps in a method for manufacturing an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 3C is a side view showing one or more steps in a method for manufacturing an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 4A is a top view showing one or more steps in a method for manufacturing an electrostatic suppressor according to some embodiments of the present disclosure;

4B is a side view of one or more steps of a manufacturing method of a static suppressor according to some embodiments of the present disclosure;

FIG. 5A is a top view showing one or more steps in a method for manufacturing an electrostatic suppressor according to some embodiments of the present disclosure;

FIG. 5B is a side view showing one or more steps in a method for manufacturing an electrostatic suppressor according to some embodiments of the present disclosure;

6A is a top view of one or more steps of a manufacturing method of a static suppressor according to some embodiments of the present disclosure;

6B is a side view of one or more steps of a manufacturing method of a static suppressor according to some embodiments of the present disclosure;

7A is a top view of one or more steps of a manufacturing method of a static suppressor according to some embodiments of the present disclosure; and

FIG. 7B is a side view of one or more steps of a manufacturing method of a static suppressor according to some embodiments of the present disclosure.

1: Electrostatic suppressor

10: Substrate

11a: Electrode/first electrode

11b: Electrode/Second Electrode

11c:Electrode/Third Electrode

12a: Conductive layer/first conductive layer

12b: Conductive layer/second conductive layer

12c: Conductive layer/third conductive layer

12r1: gap/first gap

12r2: Gap/Second Gap

13:Protective layer

14: Protective layer

101: Surface/First Surface

102: Surface/Second surface

Claims (12)

An electrostatic suppressor comprises: a substrate; a first conductive layer disposed on the substrate; a second conductive layer disposed on the substrate and separated from the first conductive layer by a first gap; a third conductive layer disposed on the substrate and separated from the second conductive layer by a second gap; and a protective layer disposed on the first conductive layer, the second conductive layer and the third conductive layer, wherein the protective layer covers the first gap and the second gap. An electrostatic suppressor as described in claim 1, wherein the second conductive layer and the first conductive layer are configured to serve as a first conductive path, and the second conductive layer and the third conductive layer are configured to serve as a second conductive path, wherein the first conductive path and the second conductive path have different triggering voltages. The static suppressor of claim 2, wherein the first conductive path and the second conductive path have different clamping voltages. The static suppressor of claim 1, wherein the first gap is recessed downward into the substrate. The electrostatic suppressor as described in claim 4 further comprises: An oxide located in the first gap. The electrostatic suppressor as described in claim 1, wherein the substrate includes a first surface and a second surface opposite to the first surface, and the electrostatic suppressor further includes: A first electrode located between the first surface of the substrate and the first conductive layer, wherein the first electrode extends to the second surface. The static suppressor as described in claim 6, wherein the static suppressor further includes: A second electrode is located between the first surface of the substrate and the second conductive layer, wherein the second electrode extends to the second surface. The static suppressor of claim 6, wherein the substrate includes a third surface extending between the first surface and the second surface, and the first electrode has a portion located recessed from the third surface. in a groove. The static suppressor of claim 6, wherein a portion of the first electrode is located in a drilled hole penetrating the substrate. A static suppressor containing: a substrate; a first conductive path having a portion located in a drilled hole extending through the substrate; and A second conductive path, wherein the first conductive path and the second conductive path have different trigger voltages. The static suppressor of claim 10, wherein the first conductive path and the second conductive path have different clamping voltages. The static suppressor of claim 10, wherein the first conductive path includes a first conductive layer and a second conductive layer separated from the first conductive layer through a gap, wherein the static suppressor further includes: oxide, located in this gap.

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