TWI735019B - Circuit board and method for making the same - Google Patents
Circuit board and method for making the same Download PDFInfo
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- TWI735019B TWI735019B TW108128165A TW108128165A TWI735019B TW I735019 B TWI735019 B TW I735019B TW 108128165 A TW108128165 A TW 108128165A TW 108128165 A TW108128165 A TW 108128165A TW I735019 B TWI735019 B TW I735019B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Abstract
Description
本發明涉及一種電路板以及所述電路板的製備方法。 The invention relates to a circuit board and a preparation method of the circuit board.
隨著手機等可擕式電子設備的功能的不斷增加,電路板也朝向多元化多類別的方向發展。雖然電路板的輕、薄、短、小是未來發展的趨勢,然而,基於承載電流、散熱、阻抗控制等需求(例如,電子設備電源消耗的增加導致電源不能滿足電子設備的續航要求,由於快速充電技術在一定程度上解決了這一問題,因此需要電路板可滿足大電流充電的需求),需要電路板具有較大的銅厚。 As the functions of portable electronic devices such as mobile phones continue to increase, circuit boards are also developing in the direction of diversification and multiple categories. Although the light, thin, short, and small circuit boards are the future development trend, however, based on the requirements of carrying current, heat dissipation, impedance control, etc. (for example, the increase in power consumption of electronic equipment causes the power supply to not meet the endurance requirements of electronic equipment, due to the rapid The charging technology solves this problem to a certain extent, so the circuit board is required to meet the needs of high current charging), and the circuit board is required to have a larger copper thickness.
傳統的工藝製作出的厚銅板品質很難達到要求,會存在側蝕問題。 The quality of thick copper plates produced by traditional processes is difficult to meet the requirements, and there will be problems of side corrosion.
有鑑於此,本發明提供一種能夠用於製備具有較大銅厚的電路板的方法,能夠避免側蝕現象產生。 In view of this, the present invention provides a method that can be used to prepare a circuit board with a relatively large copper thickness, which can avoid side corrosion.
另,還有必要提供一種由上述製備方法獲得的電路板。 In addition, it is also necessary to provide a circuit board obtained by the above-mentioned manufacturing method.
本發明提供一種電路板的製備方法,包括:提供一銅箔層並在所述銅箔層的表面覆蓋一介電層,所述介電層包括第一圖形開口;在所述第一圖形開口中電鍍銅以形成一鍍銅層;蝕刻至少部分所述銅箔層以形成一第一內側導電線路,從而得到一電路基板;以及在所述電路基板的至少一表面依次形成一絕緣層以及一外側導電線路,從而得到所述電路板。 The present invention provides a method for preparing a circuit board, which includes: providing a copper foil layer and covering a surface of the copper foil layer with a dielectric layer, the dielectric layer including a first pattern opening; Copper is electroplated to form a copper plating layer; at least part of the copper foil layer is etched to form a first inner conductive circuit, thereby obtaining a circuit substrate; and an insulating layer and an insulating layer are sequentially formed on at least one surface of the circuit substrate The outer conductive circuit, thereby obtaining the circuit board.
本發明還提供一種電路板,包括:一介電層,所述介電層包括圖形開口;一第一內側導電線路,包括第一導體部和第二導體部,所述第一導體部位於所述圖形開口內,所述第二導體部形成於所述第一導體部上,所述第一導體部與所述第二導體部在沿垂直於所述電路板的延伸方向的投影相互重合;一第二內側導電線路,形成於所述介電層上,所述第一內側導電線路的線路厚度大於所述第二內側導電線路的線路厚度;至少一絕緣層,覆蓋所述第一內側 導電線路;以及至少一外側導電線路,每一所述外側導電線路形成於其中一所述絕緣層上。 The present invention also provides a circuit board, including: a dielectric layer, the dielectric layer includes a pattern opening; a first inner conductive line, including a first conductor part and a second conductor part, the first conductor part is located at the In the pattern opening, the second conductor part is formed on the first conductor part, and the projections of the first conductor part and the second conductor part in the extension direction perpendicular to the circuit board coincide with each other; A second inner conductive circuit is formed on the dielectric layer, the circuit thickness of the first inner conductive circuit is greater than the circuit thickness of the second inner conductive circuit; at least one insulating layer covers the first inner Conductive circuit; and at least one outer conductive circuit, each of the outer conductive circuit is formed on one of the insulating layers.
相較於現有技術,本發明由於所述鍍銅層的厚度可通過控制電鍍時間來調整,可以通過設置電鍍時間獲得厚銅線路;由於僅對所述銅箔層進行蝕刻(並不對內嵌於所述介電層的鍍銅層作蝕刻),因此,有利於減小蝕刻的銅厚並避免側蝕現象產生;而且,由於所述鍍銅層直接形成於所述圖形開口內,而所述圖形開口的側壁可以設置為垂直於所述銅箔層,因此所述鍍銅層的側面也垂直設置,從而防止厚線路蝕刻時造成的側蝕現象,利於製備厚度大且間距小的導電線路。 Compared with the prior art, in the present invention, since the thickness of the copper plating layer can be adjusted by controlling the plating time, thick copper circuits can be obtained by setting the plating time; because only the copper foil layer is etched (not embedded in the The copper-plated layer of the dielectric layer is etched), therefore, it is beneficial to reduce the thickness of the copper to be etched and avoid side corrosion; moreover, because the copper-plated layer is directly formed in the pattern opening, and the The sidewalls of the pattern openings can be arranged perpendicular to the copper foil layer, so the sides of the copper plating layer are also arranged perpendicularly, so as to prevent side corrosion caused by etching of thick circuits and facilitate the preparation of conductive circuits with large thickness and small spacing.
10:銅箔層 10: Copper foil layer
11:鍍銅層 11: Copper plating layer
12:圖形化乾膜 12: Graphical dry film
20:介電層 20: Dielectric layer
21:第一圖形開口 21: The first graphic opening
30:第一保護層 30: The first protective layer
40:第二保護層 40: second protective layer
50:絕緣層 50: Insulation layer
60:第二銅箔層 60: The second copper foil layer
61:外側導電線路 61: Outer conductive circuit
70:防焊層 70: Solder mask
100:電路基板 100: Circuit board
101:第一內側導電線路 101: The first inner conductive line
102:第二內側導電線路 102: second inner conductive circuit
120:第二圖形開口 120: second graphic opening
200a、200b、200c:電路板 200a, 200b, 200c: circuit board
1011:第一導體部 1011: The first conductor part
1012:第二導體部 1012: second conductor part
圖1為本發明提供的第一銅箔層的剖視圖。 Fig. 1 is a cross-sectional view of the first copper foil layer provided by the present invention.
圖2為在圖1所示的銅箔層的表面覆蓋介電層後的剖視圖。 2 is a cross-sectional view of the copper foil layer shown in FIG. 1 after being covered with a dielectric layer.
圖3為在圖2所示的介電層中開設第一圖形開口後的剖視圖。 FIG. 3 is a cross-sectional view after opening a first pattern opening in the dielectric layer shown in FIG. 2.
圖4為在圖3所示的第一銅箔層上覆蓋第一保護層後的剖視圖。 4 is a cross-sectional view of the first copper foil layer shown in FIG. 3 after covering the first protective layer.
圖5為在圖4所示的第一圖形開口中形成鍍銅層後的剖視圖。 FIG. 5 is a cross-sectional view after a copper plating layer is formed in the first pattern opening shown in FIG. 4.
圖6為將圖5所示的第一保護層移除後的剖視圖。 FIG. 6 is a cross-sectional view after the first protective layer shown in FIG. 5 is removed.
圖7為在圖6所示的介電層和鍍銅層上覆蓋第二保護層後的剖視圖。 FIG. 7 is a cross-sectional view of the dielectric layer and the copper plating layer shown in FIG. 6 after being covered with a second protective layer.
圖8為本發明第一實施方式中蝕刻圖7所示的部分第一銅箔層後的剖視圖。 FIG. 8 is a cross-sectional view after etching a part of the first copper foil layer shown in FIG. 7 in the first embodiment of the present invention.
圖9為將圖8所示的第二保護層移除後得到的電路基板的剖視圖。 FIG. 9 is a cross-sectional view of the circuit substrate obtained by removing the second protective layer shown in FIG. 8.
圖10為在圖9所示的電路基板上形成絕緣層和第二銅箔層後的剖視圖。 Fig. 10 is a cross-sectional view of the circuit substrate shown in Fig. 9 after an insulating layer and a second copper foil layer are formed.
圖11為蝕刻圖10所示的第二銅箔層並覆蓋防焊層後得到的電路板的剖視圖。 11 is a cross-sectional view of the circuit board obtained by etching the second copper foil layer shown in FIG. 10 and covering the solder resist layer.
圖12為本發明第二實施方式中在圖7所示的第一銅箔層上覆蓋圖形化乾膜後的剖視圖。 FIG. 12 is a cross-sectional view of the first copper foil layer shown in FIG. 7 after being covered with a patterned dry film in the second embodiment of the present invention.
圖13為蝕刻圖12所示的部分第一銅箔層後的剖視圖。 FIG. 13 is a cross-sectional view of part of the first copper foil layer shown in FIG. 12 after etching.
圖14為本發明第三實施方式中在圖7所示的第一銅箔層上覆蓋圖形化乾膜後的剖視圖。 14 is a cross-sectional view of the first copper foil layer shown in FIG. 7 after being covered with a patterned dry film in the third embodiment of the present invention.
圖15為蝕刻圖14所示的部分第一銅箔層後的剖視圖。 FIG. 15 is a cross-sectional view of part of the first copper foil layer shown in FIG. 14 after etching.
圖16為在圖13後繼續製作形成的電路板的剖視圖。 Fig. 16 is a cross-sectional view of the circuit board formed after Fig. 13 is continued to be manufactured.
圖17為在圖15後繼續製作形成的電路板的剖視圖。 Fig. 17 is a cross-sectional view of the circuit board formed after Fig. 15 is continued to be manufactured.
下面將結合附圖及實施例對本發明作進一步說明。 The present invention will be further described below in conjunction with the drawings and embodiments.
第一實施方式 The first embodiment
請參閱圖1至圖11,本發明第一實施方式提供一種電路板的製備方法,包括如下步驟:步驟S1,請參閱圖1,提供一第一銅箔層10。
1 to 11, the first embodiment of the present invention provides a method for manufacturing a circuit board, including the following steps: Step S1, please refer to FIG. 1, providing a first
步驟S2,請參閱圖2,在所述第一銅箔層10的表面覆蓋一介電層20。
Step S2, referring to FIG. 2, a
在本實施方式中,所述介電層20的材質可選自環氧樹脂(epoxy resin)、聚丙烯(polypropylene,PP)、BT樹脂、聚苯醚(Polyphenylene Oxide,PPO)、聚丙烯(polypropylene,PP)、聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二醇酯(Polyethylene Terephthalate,PET)以及聚萘二甲酸乙二醇酯(Polyethylene Naphthalate,PEN)等樹脂中的一種。
In this embodiment, the material of the
所述介電層20可通過塗布的方式形成。
The
步驟S3,請參閱圖3,在所述介電層20中開設第一圖形開口21。
Step S3, referring to FIG. 3, a first pattern opening 21 is opened in the
在本實施方式中,所述第一圖形開口21可通過鐳射工藝開設。 In this embodiment, the first pattern opening 21 can be opened by a laser process.
步驟S4,請參閱圖4,在所述第一銅箔層10遠離所述介電層20的表面覆蓋一第一保護層30。
Step S4, referring to FIG. 4, a first
其中,所述第一保護層30可為一干膜。
Wherein, the first
步驟S5,請參閱圖5,在所述第一圖形開口21中電鍍銅,從而形成一鍍銅層11。
Step S5, referring to FIG. 5, electroplating copper in the first pattern opening 21 to form a
可以理解,所述鍍銅層11可通過一次或至少兩次電鍍步驟形成。所述鍍銅層11的厚度可通過控制電鍍時間來調整。所述鍍銅層11的厚度可大致等於所述介電層20的厚度,因此可根據所述鍍銅層11所需的厚度塗布所述介電層20。進一步地,由於電鍍液可能於不同深度處具有不同的濃度,因此可在電
鍍過程中或者兩次電鍍步驟之間改變所述第一銅箔層10的方位(如上下顛倒),從而提高所述鍍銅層11厚度的均勻性。
It can be understood that the
步驟S6,請參閱圖6,移除所述第一保護層30。
Step S6, referring to FIG. 6, remove the first
進一步地,可研磨所述介電層20和/或所述鍍銅層11遠離所述第一銅箔層10的表面,以使所述介電層20和所述鍍銅層11表面齊平。
Further, the surface of the
步驟S7,請參閱圖7,在所述介電層20以及所述鍍銅層11上覆蓋一第二保護層40。
Step S7, referring to FIG. 7, a second
其中,所述第二保護層40可為一干膜。
Wherein, the second
步驟S8,請參閱圖8,蝕刻至少部分所述第一銅箔層10以形成一第一內側導電線路101。
Step S8, referring to FIG. 8, at least part of the first
在本實施方式中,所述第一銅箔層10被全部蝕刻,此時所述第一內側導電線路101僅包括所述鍍銅層11。
In this embodiment, the first
步驟S9,請參閱圖9,移除所述第二保護層40,從而得到一電路基板100。
Step S9, referring to FIG. 9, the second
步驟S10,請參閱圖10,在所述電路基板100相對的兩個表面均依次一絕緣層50和一第二銅箔層60。
In step S10, referring to FIG. 10, an insulating
在本實施方式中,所述絕緣層50的材質可選自環氧樹脂(epoxy resin)、聚丙烯(polypropylene,PP)、BT樹脂、聚苯醚(Polyphenylene Oxide,PPO)、聚丙烯(polypropylene,PP)、聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二醇酯(Polyethylene Terephthalate,PET)以及聚萘二甲酸乙二醇酯(Polyethylene Naphthalate,PEN)等樹脂中的一種。可選的,所述絕緣層50的材質為聚丙烯。
In this embodiment, the material of the insulating
步驟S11,請參閱圖11,蝕刻每一第二銅箔層60以形成一外側導電線路61,並在所述外側導電線路61上覆蓋一防焊層70,從而得到所述電路板200a。
Step S11, referring to FIG. 11, each second
在本實施方式中,所述防焊層70的材質為防焊油墨。所述防焊層70可用於暴露部分所述外側導電線路61以形成多個焊墊(圖未標)。
In this embodiment, the material of the
第二實施方式 Second embodiment
本發明第二實施方式提供一種電路板的製備方法,所述方法在步驟S1-S7均與第一實施方式相同,此不贅述。與第一實施方式不同之處在於: The second embodiment of the present invention provides a method for manufacturing a circuit board, and the method in steps S1 to S7 is the same as that of the first embodiment, which will not be repeated here. The difference from the first embodiment is:
如圖12所示,在步驟S8中,首先在所述第一銅箔層10上覆蓋一圖形化乾膜12,所述圖形化乾膜12包括第二圖形開口120,所述第二圖形開口120用於暴露部分所述介電層20。即,所述圖形化乾膜12除所述第二圖形開口120的區域對應所述鍍銅層11以及另一部分所述介電層20。
As shown in FIG. 12, in step S8, a patterned
然後,如圖13所示,以所述圖形化乾膜12為光罩蝕刻所述第一銅箔層10。此時,所述鍍銅層11(以下稱為:“第一導體部1011”)以及所述第一銅箔層10與所述鍍銅層11對應的區域(以下稱為:“第二導體部1012”)共同形成所述第一內側導電線路101。所述第一銅箔層10蝕刻後還形成一第二內側導電線路102,所述第二內側導電線路102形成於所述介電層20上。其中,所述第一內側導電線路101的線路厚度大於所述第二內側導電線路102的線路厚度。
Then, as shown in FIG. 13, the first
第三實施方式 The third embodiment
本發明第二實施方式提供一種電路板的製備方法,所述方法在步驟S1-S7均與第二實施方式相同,此不贅述。與第二實施方式不同之處在於: The second embodiment of the present invention provides a method for preparing a circuit board, and the method in steps S1 to S7 is the same as that of the second embodiment, which will not be repeated here. The difference from the second embodiment is:
如圖14所示,在步驟S8中,所述圖形化乾膜12的第二圖形開口120用於暴露全部所述鍍銅層11。如圖15所示,以所述圖形化乾膜12為光罩蝕刻所述第一銅箔層10後僅形成所述第一內側導電線路101,所述第一內側導電線路101包括所述第一導體部1011和所述第二導體部1012。
As shown in FIG. 14, in step S8, the second pattern opening 120 of the patterned
在上述製備方法中,所述鍍銅層11的厚度可通過控制電鍍時間來調整,因此可以通過設置電鍍時間獲得厚銅線路。由於僅對所述第一銅箔層10進行蝕刻(並不對內嵌於所述介電層20的鍍銅層11作蝕刻),因此,有利於減小蝕刻的銅厚並避免側蝕現象產生。而且,由於所述鍍銅層11直接形成於所述第一圖形開口21內,而所述第一圖形開口21的側壁可以設置為垂直於所述第一銅箔層10,因此所述鍍銅層11的側面也垂直設置,從而防止厚線路蝕刻時造成的側蝕現象,利於製備厚度大且間距小的導電線路(如,厚度為2OZ時間距達50-100微米,厚度為3OZ時間距達75-175微米)。
In the above preparation method, the thickness of the copper-plated
請參閱圖11,本發明還提供由上述第一實施方式的製備方法制得的電路板200a,所述電路板200a包括一介電層20、一第一內側導電線路101、至少一絕緣層50和至少一外側導電線路61。
Referring to FIG. 11, the present invention also provides a
所述介電層20包括第一圖形開口21。所述第一內側導電線路101包括第一導體部1011。所述第一導體部1011位於所述第一圖形開口21內。
The
所述絕緣層50覆蓋所述第一內側導電線路101。每一所述外側導電線路61形成於其中一所述絕緣層50上。
The insulating
在本實施方式中,所述電路板200還包括至少一防焊層70,每一所述防焊層70覆蓋其中一所述外側導電線路61。
In this embodiment, the circuit board 200 further includes at least one
請參閱圖16,本發明還提供由上述第二實施方式的製備方法制得的電路板200b。與所述電路板200a不同之處在於,所述第一內側導電線路101還包括第二導體部1012,所述第二導體部1012形成於所述第一導體部1011上,所述第一導體部1011與所述第二導體部1012在沿垂直於所述電路板200的延伸方向的投影相互重合。所述電路板200b還包括第二內側導電線路102,所述第二內側導電線路102形成於所述介電層20上,所述第一內側導電線路101的線路厚度大於所述第二內側導電線路102的線路厚度。所述第二導體部1012的高度等於所述第二內側導電線路102的高度。
Referring to FIG. 16, the present invention also provides a
請參閱圖17,本發明還提供由上述第三實施方式的製備方法制得的電路板200c。與所述電路板200b不同之處在於所述第二內側導電線路102可以省略。
Referring to FIG. 17, the present invention also provides a
最後需要指出,以上實施例僅用以說明本發明的技術方案而非限制,儘管參照以上較佳實施例對本發明進行了詳細說明,本領域的普通技術人員應當理解,可以對本發明的技術方案進行修改或等同替換都不應脫離本發明技術方案的精神和範圍。 Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out. Modifications or equivalent replacements should not depart from the spirit and scope of the technical solutions of the present invention.
11:鍍銅層 11: Copper plating layer
20:介電層 20: Dielectric layer
50:絕緣層 50: Insulation layer
61:外側導電線路 61: Outer conductive circuit
70:防焊層 70: Solder mask
101:第一內側導電線路 101: The first inner conductive line
200a:電路板 200a: circuit board
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CN104219892A (en) * | 2013-05-29 | 2014-12-17 | 富葵精密组件(深圳)有限公司 | A method for manufacturing circuit board |
TW201446103A (en) * | 2013-05-31 | 2014-12-01 | Zhen Ding Technology Co Ltd | Circuit board and method for manufacturing same |
TW201838494A (en) * | 2017-04-07 | 2018-10-16 | 南亞電路板股份有限公司 | Circuit board structure and method for fabricating the same |
TW201917795A (en) * | 2017-10-18 | 2019-05-01 | 鈺橋半導體股份有限公司 | Interconnect substrate having cavity for stackable semiconductor assembly and manufacturing method thereof |
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