TWI732688B - Piezoelectric micromachined ultrasonic transducer and method of fabricating the same - Google Patents

Abstract

A PMUT includes a substrate, a stopper, and a multi-layered structure, where the substrate includes a corner, and a cavity is disposed in the substrate. The stopper is in contact with the corner of the substrate and the cavity. The multi-layered structure is disposed over the cavity and attached to the stopper and the multi-layered structure includes at least one through hole in contact with the cavity.

Description

Piezoelectric micromechanical ultrasonic transducer and manufacturing method thereof

The present disclosure relates to the technical field of Micro Electro Mechanical System (MEMS), in particular to a piezoelectric micromachined ultrasonic transducer (PMUT) and a manufacturing method thereof.

In the past few decades, Micro Machined Transducers (MUTs) have been extensively studied and have become an important component of various consumer electronics products, such as fingerprint sensors and proximity (proximity) sensing. Component in the device and gesture sensor. Generally speaking, MUTs can be divided into two categories, such as capacitive micromachined ultrasonic transducers (CMUTs) and piezoelectric micromachined ultrasonic transducers (PMUTs). For a typical piezoelectric micromachined ultrasonic transducer, the piezoelectric micromachined ultrasonic transducer includes a film layer composed of elastic materials, electrodes, and piezoelectric materials. This film layer is set on the acoustic wave resonator. The cavity is used to improve the acoustic performance of the piezoelectric micromachined ultrasonic transducer. During the operation of the piezoelectric micromachined ultrasonic transducer, the ultrasonic waves generated by the vibration of the film will be transmitted from the piezoelectric micromachined ultrasonic transducer to the target, and then the piezoelectric micromachined ultrasonic transducer can Detects the reflected sound waves generated by ultrasonic waves hitting the target.

Generally, the piezoelectric micromachined ultrasonic transducer will operate at the bending resonance frequency of the film, which can be determined by selecting the correct material, the size and thickness of the film. Therefore, good matching of the resonance frequency of individual piezoelectric micromachined ultrasonic transducers is a necessary condition for normal operation. For the conventional piezoelectric micromachined ultrasonic transducer, the cavity under the film layer can be formed by etching the back surface of the substrate. This cavity can penetrate the substrate so that the cavity opening adjacent to the membrane layer can be used to define the size (or diameter) of the membrane layer. However, since the cavity provided under the film layer is formed by etching the backside of the substrate, the opening size of the cavity adjacent to the substrate may vary greatly in different regions within the same wafer or between different wafers. Therefore, it inevitably leads to the variation of the resonance frequency of each piezoelectric micromachined ultrasonic transducer. In addition, the above-mentioned method of forming a cavity by etching the back surface of the substrate is also quite time-consuming, which is not conducive to the mass production of piezoelectric micromachined ultrasonic transducers.

Therefore, there is a need to provide an improved piezoelectric micromechanical ultrasonic transducer and a manufacturing method thereof, so that the size of the cavity in the piezoelectric micromechanical ultrasonic transducer and the size of the film layer above the cavity can be accurately controlled.

In view of this, in order to improve the uniformity of the cavity size of the piezoelectric micromachined ultrasonic transducer, it is necessary to propose an improved piezoelectric micromachined ultrasonic transducer and a manufacturing method thereof.

According to an embodiment of the present disclosure, a piezoelectric micromachined ultrasonic transducer is disclosed, including a substrate, a barrier structure, and a multilayer structure. The base includes corners, and the cavity is provided in the base. The blocking structure contacts the corners and cavities of the substrate. The multilayer structure will be disposed above the cavity and then to the barrier structure. The multilayer structure includes at least one through hole contacting the cavity.

According to another embodiment of the present disclosure, a manufacturing method of a piezoelectric micromechanical ultrasonic transducer is disclosed, which includes the following steps. First, a substrate is provided, and a barrier structure contacting the substrate is formed. Then, a multilayer structure is formed on the substrate and the barrier structure. Afterwards, at least one through hole penetrating the multilayer structure is formed. Then, an etchant is provided to the substrate through the through hole to etch part of the substrate to form a cavity, wherein the barrier structure directly contacts the cavity.

According to the embodiment of the present disclosure, the film layer disposed on the front surface of the substrate includes at least one through hole, and the through hole allows the etchant to flow therethrough, and the etchant will etch the substrate under the film layer. Therefore, the cavity can be formed by etching the front surface of the substrate. In addition, the barrier structure disposed under the film layer can be used to define the size of the film layer that can vibrate during the operation of the piezoelectric micromachined ultrasonic transducer. Therefore, the manufacturing cost of the piezoelectric micromechanical ultrasonic transducer can be reduced, and the reliability and electrical properties of the piezoelectric micromechanical ultrasonic transducer can be effectively improved.

The present disclosure provides several different embodiments, which can be used to implement different features of the present disclosure. To simplify the description, this disclosure also describes examples of specific components and settings. The purpose of providing these examples is only for illustration, and not for any limitation. For example, the following description of "the first feature is formed on or above the second feature" can mean "the first feature is in direct contact with the second feature", or it can mean "the first feature is in direct contact with the second feature". There are other features among the features", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and notes are used to make the description more concise and clear, rather than to indicate the relevance between different embodiments and/or configurations.

In addition, regarding the space-related narrative vocabulary mentioned in this disclosure, for example: "below", "low", "below", "above", "above", "below", "top" ", "bottom" and similar words, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawing. In addition to the swing outward shown in the diagram, these spatially related words are also used to describe the possible swing directions of the semiconductor device in use and operation. As the swing direction of the semiconductor device is different (rotated by 90 degrees or other orientations), the space-related narratives used to describe its swing direction should also be interpreted in a similar way.

Although this disclosure uses terms such as first, second, and third to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, And/or blocks should not be restricted by these terms. These terms are only used to distinguish an element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they do not mean or represent the element. Any previous ordinal number does not represent the order of arrangement of a component and another component, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block It.

The term "about" or "substantially" mentioned in this disclosure usually means within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, the meaning of "approximate" or "substantial" can still be implied when there is no specific description of "approximate" or "substantial".

The specific sequence or level of the flowchart blocks disclosed in the following process/flow chart can be understood as an exemplary description. It is understandable that, according to different design preferences, the specific sequence or level of the flowchart blocks disclosed in the process/flow chart can be rearranged. In addition, part of the flowchart blocks can be combined or omitted. The attached method request items show the elements in each flowchart block in the order of examples, but this does not mean that the method request items are limited to this specific order or level.

Although specific embodiments are used below to describe the invention of the present disclosure, the principles of the invention of the present disclosure can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present disclosure, specific details will be omitted, and the omitted details belong to the scope of knowledge of ordinary knowledgeable persons in the technical field.

In order to enable those skilled in the art to realize the present disclosure, the method of manufacturing a piezoelectric micromachined ultrasonic transducer will be described below. Since piezoelectric micro-machined ultrasonic transducers can be manufactured through standard CMOS manufacturing process, related electronic components, such as field-effect transistors, can also be manufactured through the same CMOS process on the same substrate of piezoelectric micro-machined ultrasonic transducers. Amplifier and integrated circuit.

FIG. 1 is a schematic cross-sectional view of a structure after forming a trench in a substrate according to an embodiment of the disclosure. Referring to FIG. 1, a substrate 102 is provided. The substrate 102 has two opposite surfaces, such as a first surface 104A and a second surface 104B. The substrate 102 may be a semiconductor substrate, such as a crystalline silicon or AlN substrate, and the thickness of the substrate 102 may be 30-600 μm. Anisotropic etching, such as reactive ion etching (RIE), can be used to form the trench 106 in the substrate 102. Each trench 106 may be a deep trench, the depth 102D of which is 10-40 μm (for example, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm), and the distance 106L between two adjacent trenches 106 is 500 μm to 3 mm. Because the position of each groove 106 can be precisely defined by the photolithography process, the distance 106L between the grooves 106 can be accurately controlled without deviating from a predetermined value.

FIG. 2 is a schematic cross-sectional view of a structure after depositing a first dielectric layer in a trench according to an embodiment of the disclosure. The first dielectric layer 108 may be composed of, for example, silicon oxide (SiOx), silicon nitride (SiNx), aluminum nitride (AIN), aluminum oxide (Al ₂ 0 ₃ ), other suitable dielectric materials, or the above The combination of, is deposited on the substrate 102 and fills the trench 106. According to an embodiment of the disclosure, the composition of the first dielectric layer 108 is different from the composition of the substrate 102.

FIG. 3 is a schematic cross-sectional view of the structure after forming a groove to expose the dielectric layer in the groove according to an embodiment of the disclosure. Referring to FIG. 3, a photolithography and etching process may be performed to remove part of the first dielectric layer 108 and part of the substrate 102. When the photolithography and etching processes are completed, the groove 110 may be formed on the outer side of the trench 106 so that the first dielectric layer 108 originally located in the trench 106 may be exposed. In addition, the protrusion 112 of the base 102 may be formed between two opposite grooves 110. The top surface 110A of the base 102 exposed from the grooves 110 may be lower than the top surface 112A of the protrusion 112 of the base 102.

FIG. 4 is a schematic cross-sectional view of a structure after depositing a second dielectric layer on the first dielectric layer according to an embodiment of the disclosure. After the process shown in FIG. 3, the second dielectric layer 114 may be deposited on the first dielectric layer 108 and filled into the groove 110. The composition of the second dielectric layer 114 may be silicon _{oxide (SiO x} ), silicon nitride (SiN _x ), aluminum nitride (AIN), aluminum oxide (Al ₂ 0 ₃ ), other suitable dielectric materials, Or a combination of the above. According to an embodiment of the present disclosure, the composition of the second dielectric layer 114 may be the same as the composition of the first dielectric layer 108. In addition, the top surface 114A of the second dielectric layer 114 located outside the trench 106 may be aligned with or higher than the top surface 112A of the protrusion 112.

FIG. 5 is a schematic cross-sectional view of a structure after planarizing the first dielectric layer and the second dielectric layer disposed on the substrate according to an embodiment of the disclosure. Referring to FIG. 5, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to planarize the top surfaces of the protrusion 112, the first dielectric layer 108, and the second dielectric layer 114. When the planarization process is completed, the height 108H of the first dielectric layer 108 may be higher than the height 114H of the second dielectric layer 114. In addition, the first dielectric layer 108 can be used as a barrier structure 116 to define the position of the cavity formed in the subsequent process.

FIG. 6 is a schematic cross-sectional view after forming a multilayer structure on a substrate according to an embodiment of the disclosure. Referring to Figure 6, an optional seed layer 127, bottom electrode 122, piezoelectric layer 124, piezoelectric layer 128, top electrode 126, and passivation layer 129 can be deposited on the substrate 102 and the first dielectric layer 108 to The multilayer structure 120 disposed on the substrate 102 is formed. The piezoelectric layer 128 may be composed of piezoelectric materials, such as aluminum nitride (AlN), scandium-doped aluminum nitride (AlScN), lead zirconate titanate (PZT), zinc oxide (ZnO), poly Polyvinylidene fluoride (PVDF), or lead mangnesium niobate-lead titanate (PMN-PT), but not limited to this. According to an embodiment of the present disclosure, when the piezoelectric layer 128 and the piezoelectric layer 124 are formed by the same deposition process, the piezoelectric layer 128 and the piezoelectric layer 124 may have the same composition, but are not limited thereto. An optional seed layer 127, such as SiO ₂ , SiON, AlN, or AlScN, may be disposed between the bottom electrode 122 and the substrate 102. The surface texture of the seed layer 127 can affect the crystallinity of the layers deposited thereon. The bottom electrode 122 and the top electrode 126 may be the same or different materials composed of molybdenum (Mo), titanium (Ti), aluminum (Al), or platinum (Pt). The piezoelectric layer 124 may be composed of piezoelectric materials, such as AlN, AlScN, PZT, ZnO, PVDF, PMN-PT, but is not limited thereto. The passivation layer 129 may be used to passivate and/or protect the piezoelectric layers 124 and 128 and the top electrode 126 underneath, and may be composed of an insulating material or a piezoelectric material. According to some embodiments of the present disclosure, the passivation layer 129 may be composed of SiO ₂ , SiON, AlN, AlScN, PZT, ZnO, PVDF, PMN-PT, but is not limited thereto.

In addition, at least one conductive pad 132 is formed in the piezoelectric layer 128 and is electrically connected to the bottom conductive layer 122 and the top conductive layer 126. After the multilayer structure 120 is formed, at least one through hole 130 having a height of 130H, such as through hole 130a and through hole 130b, may be formed in the multilayer structure 120 to expose the top surface 112A of the protrusion 112 from the bottom of the through hole 130 . According to the embodiment of the present disclosure, the height of the blocking structure 116 may be greater than 1/2 of the average height of the through holes 130, for example, more than twice the average height of the through holes 130.

According to the structure shown in Figure 6, although the through holes 130 seem to be separated from each other, some of the through holes 130 can be connected to each other, so that in a plan view, the through holes 130 can form a continuous pattern, such as an annular groove, Polygonal slot, or arc-shaped slot. FIG. 7 is a schematic top view of a structure having a plurality of through holes in a multilayer structure, wherein FIG. 6 is a schematic diagram along the tangent line A-A' in FIG. 5. Referring to FIG. 7, the through hole 130 includes a circular through hole 130a provided in the center and an annular through hole 130b surrounding the circular through hole 130a. In addition, the blocking structure 116 shown in FIG. 6 may be a continuous structure provided along the circumference of the annular through hole 130b.

The shape of each through hole 130 is not limited to the through hole shape shown in FIG. 7. For example, as shown in Fig. 8(a), the through hole 130 includes a circular through hole 130a arranged in the center and a plurality of separated arc-shaped through holes 130b arranged around the circular through hole 130a. In addition, referring to FIG. 8(b), all the through holes 130 are circular through holes 130a, 130b, which are randomly or orderly distributed in the multilayer structure 120.

FIG. 9 is a schematic cross-sectional view of a structure after a cavity is formed in a substrate according to an embodiment of the disclosure. Referring to FIG. 9, the front surface of the substrate 102 can be etched to form a cavity 150 having a predetermined diameter 150L. The etching process may include the following steps: providing an etchant to the substrate 102 through the through hole 130 until the bottom surface 150A of the cavity is etched to a specific depth 150H of 5 to 35 μm, such as 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, Or 35μm, but not limited to this. According to an embodiment of the present disclosure, when the blocking structure 116 is silicon oxide and the substrate 102 is silicon, the etchant may be sulfur hexafluoride (SF ₆ ). During the etching process, since the etching selection ratio of the substrate 102 to the barrier structure 116 and the seed layer 127 in the multilayer structure 120 is greater than 10, only the substrate 102 that directly contacts the etchant and is not protected by the barrier structure 116 will be etched. In other words, during the step of forming the cavity 150 in the substrate 102, the etchant may be confined in the area defined by the barrier structure 116. According to an embodiment of the disclosure, the inner sidewall of the blocking structure 116 coincides with the sidewall of the cavity 150. In addition, the bottom surface 150A of the cavity 150 is higher than the bottom surface of the barrier structure 116, so that the lower portion of the barrier structure 116 can remain buried in the substrate 102. Furthermore, after the cavity 150 is formed, at least one corner 104C of the substrate 102 will be adjacent to the bottom surface of the multilayer structure 120, and the corner 104C of the substrate 102 can directly contact the blocking structure 116. According to an embodiment of the present disclosure, the top surface of the blocking structure 116 is higher than the highest point of the corner 104C of the substrate 102.

FIG. 10 is a schematic cross-sectional view of the structure after the dielectric layer is filled into the through hole according to an embodiment of the disclosure. Referring to FIG. 10, a dielectric layer 136 (or called an elastic layer) with required elasticity can be formed on the multilayer structure and filled into the through holes 130 to mechanically support the multilayer structure and adjust the resonance frequency of the corresponding PMUT. Therefore, a film layer 138 including at least the bottom electrode 122, the piezoelectric layer 124, the top electrode 126, and the dielectric layer 136 can be obtained. Since the diameter or size of each through hole 130 is sufficiently small (for example, 10 to 300 nm), the upper portion of each through hole 130 can be easily blocked or sealed by the dielectric layer 136 during the process of depositing and forming the dielectric layer 136. Therefore, the dielectric layer 136 is not deposited in the cavity 150. In addition, the dielectric layer 136 may serve as a protective layer covering a portion of the conductive pad 132. A contact hole 140 may be further formed in the dielectric layer 136 to expose part of the conductive pad 132. Additional conductive traces (not shown) may be electrically connected to the conductive pad 132 in order to transmit electrical signals to or from the film layer 138. It should be noted that, according to an embodiment of the present disclosure, since the thickness or elasticity of the stacked layer disposed under the dielectric layer 136 is much smaller than the thickness or elasticity of the dielectric layer 136, the mechanical behavior of the film layer 138 is mainly determined by the film layer. 138 is dominated by the dielectric layer 136.

During the operation of the PMUT, when sound waves apply sound pressure on the film layer 138 or when an external electrical signal is applied to the film layer 138, the film layer 138 suspended on the cavity 150 may vibrate. By providing the barrier structure 116, the size and position of the film layer 138 suspended on the cavity 150 can be precisely defined, and the cavity 150 can be formed by etching the front surface of the substrate 102. Therefore, the uniformity of the resonance frequency of each PUMT can be improved, and the time required to form the cavity can be reduced.

According to some embodiments of the present disclosure, other electronic components, such as conductive pads or through silicon vias (TSV), may also be formed on or in the substrate 102. FIG. 11 is a schematic cross-sectional view of a structure in which through silicon vias are located in a substrate according to an embodiment of the disclosure. Referring to FIG. 11, a silicon via 160 penetrating the substrate 102 can be formed, so that both ends of the silicon via 160 can be exposed from the first surface 104a and the second surface 104b of the substrate 102, respectively. In addition, two conductive pads 132 are provided on the substrate 102. One of the conductive pads 132 may be electrically connected to the electrode of the PMUT, and the other of the conductive pads 132 may be partially formed in the second dielectric layer and electrically connected to the silicon via 160.

According to another embodiment of the present disclosure, additional photolithography and etching processes may be performed on the back surface of the substrate 102 shown in FIG. 10 to form another cavity under the cavity 150. FIG. 12 is a schematic cross-sectional view of a structure in which through silicon vias are located in a substrate according to an embodiment of the disclosure. Referring to FIG. 12, another cavity 152 can be further formed under the cavity 150 by etching the back surface of the substrate 102. The shape of the cavity 152 may be designed according to the shape of the cavity 150. However, the diameter 152L of the cavity 152 may be slightly smaller than the diameter 150L of the cavity 150. For example, when viewed from a top view, the cavity 150 may be a circle with a diameter of 1 mm, and the cavity 152 may also be a circle, but the diameter is relatively small, such as 0.8 mm.

The manufacturing method of the barrier structure is not limited to the above-mentioned embodiment. According to some embodiments of the present disclosure, the barrier structure can also be fabricated by performing the processes shown in FIG. 13 and FIG. 14.

FIG. 13 is a schematic cross-sectional view of a structure in which the dielectric layer has at least one through hole according to an embodiment of the disclosure. Referring to Fig. 13, the structure shown in Fig. 13 can be manufactured through the process shown in Figs. 1 to 6. However, in the embodiment shown in FIG. 13, the first dielectric layer 108 is not only filled into the trench 106, but also disposed between the multilayer structure 120 and the substrate 102. Therefore, the entire multilayer structure 120 can be separated from the substrate 102 by providing the first dielectric layer 108. In addition, at least one through hole 130 may extend into the first dielectric layer 108 to expose a part of the surface of the substrate 102.

FIG. 14 is a schematic cross-sectional view of a structure after a cavity is formed in the substrate according to an embodiment of the disclosure. Referring to FIG. 14, a process similar to the embodiment of FIG. 9 can be used to perform an etching process to form a cavity 150 in the substrate 102. However, according to the embodiment shown in FIG. 14, the etchant can not only etch the substrate 102, but also etch the first dielectric layer 108 disposed under the multilayer structure 120. Therefore, when the etching process is completed, the first dielectric layer 108 above the cavity 150 can be completely removed, thereby exposing the bottom surface of the multilayer structure 150 above the cavity 150. In addition, when the etching process is completed, the upper sidewall 108A of the barrier structure 116 may be misaligned with the lower sidewall 108B of the barrier structure 116, but it is not limited thereto.

Figures 15 to 17 illustrate a method of fabricating a component including PMUT according to an embodiment of the disclosure. Referring to Fig. 15, a base 102 having a protrusion 112 may be provided. The substrate 102 may be a semiconductor substrate, such as a crystalline silicon or AlN substrate, and the thickness of the substrate 102 may be 30-600 μm. A dielectric layer 208 can be deposited on the substrate 102, such as silicon _{oxide (SiO x} ), silicon nitride (SiN _x ), aluminum nitride (AIN), aluminum oxide (Al ₂ 0 ₃ ), and other suitable dielectric materials , Or a combination of the above, to surround the protrusion 112. A CMP process can be used to make the top surface of the dielectric layer 208 flush with the top surface of the protrusion 112, but it is not limited thereto. The thickness (or height 208H) of the dielectric layer 208 may be set in the range of 3-15 μm, such as 3 μm, 5 μm, 9 μm, 11 μm, 13 μm, or 15 μm, but is not limited thereto.

Referring to Fig. 16, the structure shown in Fig. 16 can be manufactured through a process similar to that shown in Fig. 6. However, in Figure 16, no trenches will be formed in the substrate 102. In the subsequent etching process, the dielectric layer 208 disposed on the substrate 102 can be used as a barrier structure 216 to resist etching. In addition, the height 208H of the blocking structure 216 may be greater than half of the average height 130H of the through hole 130.

Referring to Fig. 17, the structure shown in Fig. 17 can be made through a process similar to that shown in Fig. 9. According to the embodiment shown in FIG. 17, the etchant can not only etch the substrate 102 between the barrier structures 216 but also the substrate 102 under the barrier structures 216. In addition, two cavities (the lower cavity 250 and the upper cavity 252) having different diameters may be formed in the substrate 102. For example, the maximum diameter 250L of the lower cavity 250 may be greater than the maximum diameter 252L of the upper cavity 252. In addition, the side wall of the blocking structure 216 may coincide with the side wall of the upper cavity 252. Also, when viewed from a plan view, the shape of the lower cavity 250 may be formed corresponding to the shape of the upper cavity 252. For example, when the top-view profile of the upper cavity 252 is a circle with a diameter of 1 mm, the top-view profile of the lower cavity 250 may also be a circle, but has a relatively large diameter, such as 1.2 mm. Because the thickness (or height 208H) of the barrier structure 216 is set in the range of 3-15 μm, even if part of the barrier structure 216 is not supported by the substrate 102, the barrier structure 216 can still maintain sufficient rigidity. Therefore, during the operation of the PMUT, the blocking structure 216 will not deform or vibrate, and can be used to accurately define the size of the film layer disposed above the lower cavity 250 and the upper cavity 252.

According to an embodiment of the present disclosure, the multilayer structure disposed on the front surface of the substrate includes at least one through hole, and the through hole allows the etchant to flow therethrough and etch the substrate under the film layer. Therefore, a cavity can be formed by etching the front surface of the substrate. In addition, the barrier structure disposed under the multilayer structure can be used to define the size of the film layer that can vibrate during PMUT operation. Therefore, the manufacturing cost of the PMUT can be reduced, and the reliability and electrical properties of the PMUT can be effectively improved. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

102: Base 102D: Depth 104A: First surface 104B: second surface 104C: corner 106: groove 106L: distance 108: first dielectric layer 108A: Upper side wall 108B: Lower side wall 108H: height 110: Groove 110A: Top surface 112: protrusion 112A: Top surface 114: second dielectric layer 114H: height 116: blocking structure 120: Multi-layer structure 122: bottom electrode 124: Piezo Layer 126: Top electrode 127: Seed layer 128: Piezo layer 129: Passivation layer 130: Through hole 130a: Through hole 130b: Through hole 130H: height 132: Conductive pad 136: Dielectric layer 138: Membrane 140: contact hole 150: Cavity 150A: bottom surface 150H: Depth 150L: diameter 152: Cavity 152L: diameter 160: Silicon perforation 208: Dielectric layer 208H: height 216: Barrier Structure 250: Lower cavity 252: Upper cavity

In order to make the following easier to understand, the drawings and detailed text descriptions can be referred to when reading this disclosure. Through the specific embodiments in this text and with reference to the corresponding drawings, the specific embodiments of the present disclosure are explained in detail, and the principle of the specific embodiments of the present disclosure is explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced. FIG. 1 is a schematic cross-sectional view of a structure after forming a trench in a substrate according to an embodiment of the disclosure. FIG. 2 is a schematic cross-sectional view of a structure after depositing a first dielectric layer in a trench according to an embodiment of the disclosure. FIG. 3 is a schematic cross-sectional view of a structure after forming a groove to expose the first dielectric layer in the groove according to an embodiment of the disclosure. FIG. 4 is a schematic cross-sectional view of a structure after depositing a second dielectric layer on the first dielectric layer according to an embodiment of the disclosure. FIG. 5 is a schematic cross-sectional view of the structure after planarizing the first dielectric layer and the second dielectric layer disposed on the substrate according to an embodiment of the disclosure. FIG. 6 is a schematic cross-sectional view of a structure after forming a multilayer structure on a substrate according to an embodiment of the disclosure. FIG. 7 is a schematic top view of a structure in which a plurality of through holes are located in a multilayer structure according to an embodiment of the disclosure. FIG. 8 is a schematic top view of a structure in which a plurality of through holes are located in a multilayer structure according to an embodiment of the disclosure. FIG. 9 is a schematic cross-sectional view of a structure after a cavity is formed in the substrate according to an embodiment of the disclosure. FIG. 10 is a schematic cross-sectional view of the structure after the dielectric layer is filled into the through hole according to an embodiment of the disclosure. FIG. 11 is a schematic cross-sectional view of a structure in which silicon vias are located in a substrate according to an embodiment of the disclosure. FIG. 12 is a schematic cross-sectional view of a structure having a cavity penetrating the substrate according to an embodiment of the disclosure. FIG. 13 is a schematic cross-sectional view of a structure in which the dielectric layer includes at least one through hole according to an embodiment of the disclosure. FIG. 14 is a schematic cross-sectional view of a structure after a cavity is formed in the substrate according to an embodiment of the disclosure. FIG. 15 to FIG. 17 show a method of manufacturing a device including PMUT according to an embodiment of the disclosure.

102: Base

104C: corner

108: first dielectric layer

108H: height

110: Groove

114: second dielectric layer

116: blocking structure

122: bottom electrode

124: Piezo Layer

126: Top electrode

127: Seed layer

128: Piezo layer

129: Passivation layer

130: Through hole

130a: Through hole

130b: Through hole

130H: height

132: Conductive pad

136: Dielectric layer

138: Membrane

140: contact hole

150: Cavity

150A: bottom surface

150H: Depth

150L: diameter

Claims (19)

A piezoelectric micromechanical ultrasonic transducer (PMUT), including: A base, including a corner; A cavity arranged in the substrate; A blocking structure contacting the corner of the substrate and the cavity; and A multi-layer structure is arranged above the cavity and attached to the barrier structure, wherein the multi-layer structure includes at least one through hole contacting the cavity. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein the height of the blocking structure is greater than 1/2 of the height of the at least one through hole. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein the multilayer structure includes at least two electrodes and a piezoelectric layer, and the piezoelectric layer is disposed between the electrodes. The piezoelectric micromachined ultrasonic transducer according to claim 1, further comprising a dielectric layer disposed on the multilayer structure and filling an upper portion of the at least one through hole. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein the material of the substrate is different from the material of the blocking structure, and when gaseous hydrofluoric acid is used as an etchant, the etchant is effective against the substrate and The etching selection ratio of the barrier structure is greater than 10. The piezoelectric micromachined ultrasonic transducer according to claim 5, wherein the substrate is composed of crystalline silicon, and the blocking structure is composed of silicon oxide. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein the lower part of the blocking structure is embedded in the substrate. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein a bottom surface of the cavity is higher than a bottom surface of the blocking structure. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein a side wall of the blocking structure coincides with a side wall of the cavity. The piezoelectric micromechanical ultrasonic transducer according to claim 1, further comprising a dielectric layer disposed between the substrate and the multilayer structure, wherein the dielectric layer and the barrier structure have the same composition. The piezoelectric micromachined ultrasonic transducer according to claim 1, further comprising another cavity arranged below the cavity and directly contacting the cavity, wherein the diameter of the other cavity is smaller than the diameter of the cavity. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein an upper side wall of the blocking structure is not aligned with a lower side wall of the blocking structure. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein the blocking structure is extended to cover a top surface of the substrate. The piezoelectric micromachined ultrasonic transducer according to claim 1, wherein a part of the cavity is located under the blocking structure. The piezoelectric micromachined ultrasonic transducer according to claim 1, further comprising another cavity disposed above the cavity, wherein a side wall of the blocking structure coincides with a side wall of the other cavity. A method for manufacturing a piezoelectric micromechanical ultrasonic transducer, including: Provide a base; Forming a barrier structure that contacts the substrate; Forming a multilayer structure, the multilayer structure being disposed on the substrate and the barrier structure; Forming at least one through hole, the at least one through hole penetrating the multilayer structure; and An etchant is provided to the substrate through the at least one through hole to etch a part of the substrate to form a cavity, wherein the barrier structure directly contacts the cavity. The method for manufacturing a piezoelectric micromachined ultrasonic transducer according to claim 16, wherein the step of forming the blocking structure contacting the substrate includes: Forming two grooves in the substrate; Filling the trenches with a first dielectric layer; Etching the substrate to expose the first dielectric layer in each trench; Forming a second dielectric layer on the first dielectric layer and the substrate; and The first dielectric layer and the second dielectric layer are planarized until the top surfaces of the first dielectric layer and the second dielectric layer are aligned with a top surface of the substrate. The manufacturing method of the piezoelectric micromachined ultrasonic transducer as described in claim 16 further includes: Forming a dielectric layer on the substrate to fill a plurality of trenches; Forming a multilayer structure, the multilayer structure being disposed on the substrate and the dielectric layer; Forming at least one through hole, the at least one through hole penetrating the multilayer structure and the dielectric layer disposed on the substrate; and In the step of etching the portion of the substrate to form the cavity, the dielectric layer above the cavity is removed. The method for manufacturing a piezoelectric micromachined ultrasonic transducer according to claim 16, wherein, in the step of etching the part of the substrate to form the cavity, a bottom surface of the blocking structure is exposed from the cavity Out.

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