CN114335320A - Piezoelectric micromechanical ultrasonic transducer and manufacturing method thereof - Google Patents

Abstract

The invention discloses a piezoelectric micro-mechanical ultrasonic transducer and a manufacturing method thereof, wherein the piezoelectric micro-mechanical ultrasonic transducer comprises: a substrate including a corner portion; a cavity disposed within the substrate; a barrier structure contacting the corner of the substrate and the cavity; and a multi-layered structure disposed over the cavity and attached to the barrier structure, wherein the multi-layered structure includes at least one via contacting the cavity. The manufacturing method comprises the following steps: providing a substrate; forming a barrier structure, wherein the barrier structure is contacted with the substrate; forming a multi-layer structure disposed on the substrate and the barrier structure; forming at least one through hole penetrating through the multilayer structure; and providing an etchant to the substrate through the at least one through hole to etch a portion of the substrate to form a cavity, wherein the barrier structure directly contacts the cavity.

Description

Piezoelectric micromechanical ultrasonic transducer and manufacturing method thereof

Technical Field

The invention relates to the technical field of Micro Electro Mechanical Systems (MEMS), in particular to a Piezoelectric Micro machined Ultrasonic Transducer (PMUT) and a manufacturing method thereof.

Background

Micro Mechanical Ultrasonic Transducers (MUTs) have received extensive attention and research over the past several decades and have become important components in various consumer electronics products, such as fingerprint sensors, proximity sensors, and gesture sensors. Generally, MUTs can be divided into two broad categories, for example, Capacitive Micromachined Ultrasonic Transducers (CMUTs) and Piezoelectric Micromachined Ultrasonic Transducers (PMUTs). For a typical piezoelectric micromachined ultrasonic transducer, the piezoelectric micromachined ultrasonic transducer includes a film layer formed by an elastic material, an electrode and a piezoelectric material, and the film layer is disposed on a cavity serving as an acoustic wave resonator to improve the acoustic performance of the piezoelectric micromachined ultrasonic transducer. During the operation of the piezoelectric micromachined ultrasonic transducer, the ultrasonic wave generated by the vibration of the membrane layer is transmitted from the piezoelectric micromachined ultrasonic transducer to the target object, and then the piezoelectric micromachined ultrasonic transducer can detect the reflected acoustic wave generated after the ultrasonic wave hits the target object.

Typically, piezoelectric micromachined ultrasonic transducers will operate at the membrane layer's bending resonance frequency, which can be determined by choosing the correct materials, membrane layer dimensions and thickness. Therefore, a good matching of the resonance frequencies of the individual piezoelectric micromachined ultrasonic transducers is a necessary condition for proper operation. For existing piezoelectric micromachined ultrasonic transducers, the cavity under the membrane layer may be formed by etching the back surface of the substrate. The cavity can penetrate the substrate, such that the cavity opening adjacent to the film can be used to define the size (or diameter) of the film. However, since the cavity disposed below the film is formed by etching the back surface of the substrate, the size of the opening of the cavity adjacent to the substrate may vary considerably in different areas within the same wafer or between different wafers, which inevitably results in variation of the resonant frequency of each piezoelectric micromachined ultrasonic transducer. In addition, the above-mentioned method of forming the cavity by etching the back surface of the substrate is time-consuming, which is not favorable for mass production of the piezoelectric micromachined ultrasonic transducer.

Therefore, it is desirable to provide an improved piezoelectric micromachined ultrasonic transducer and a method for fabricating the same, so that the size of the cavity and the size of the film layer above the cavity in the piezoelectric micromachined ultrasonic transducer can be precisely controlled.

Disclosure of Invention

In view of the above, in order to improve the uniformity of the cavity size of the piezoelectric micromachined ultrasonic transducer, it is necessary to provide an improved piezoelectric micromachined ultrasonic transducer and a method for manufacturing the same.

According to an embodiment of the present invention, there is provided a piezoelectric micromachined ultrasonic transducer including: a substrate including a corner portion; a cavity disposed within the substrate; a barrier structure contacting the corner of the substrate and the cavity; and a multi-layered structure disposed over the cavity and attached to the barrier structure, wherein the multi-layered structure includes at least one via contacting the cavity.

According to another embodiment of the present invention, a method for manufacturing a piezoelectric micromachined ultrasonic transducer is provided, including: providing a substrate; forming a barrier structure, wherein the barrier structure is contacted with the substrate; forming a multi-layer structure disposed on the substrate and the barrier structure; forming at least one through hole penetrating through the multilayer structure; and providing an etchant to the substrate through the at least one through hole to etch a portion of the substrate to form a cavity, wherein the barrier structure directly contacts the cavity.

According to an embodiment of the present invention, the layer disposed on the front surface of the substrate includes at least one via hole allowing an etchant to flow therethrough, and the etchant etches the substrate below the layer. Thus, the cavity may be formed by etching the front surface of the substrate. In addition, the size of the membrane layer that can vibrate during the operation of the piezoelectric micromachined ultrasonic transducer can be defined by the blocking structure disposed below the membrane layer. Therefore, the manufacturing cost of the piezoelectric micromachined ultrasonic transducer can be reduced, and the reliability and the electrical property of the piezoelectric micromachined ultrasonic transducer can be effectively improved.

Drawings

FIG. 1 is a cross-sectional view of a structure after forming a trench in a substrate according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view of the structure after depositing a first dielectric layer in the trench in accordance with one embodiment of the present invention;

FIG. 3 is a cross-sectional view of the structure after forming a recess to expose the first dielectric layer in the trench according to an embodiment of the present invention;

FIG. 4 is a cross-sectional view of the structure after depositing a second dielectric layer on the first dielectric layer in accordance with one embodiment of the present invention;

FIG. 5 is a cross-sectional view of a planarized first dielectric layer and a planarized second dielectric layer disposed on a substrate in accordance with one embodiment of the present invention;

FIG. 6 is a cross-sectional view of a structure after forming a multi-layer structure on a substrate according to one embodiment of the present invention;

FIG. 7 is a schematic top view of a multi-layer structure with a plurality of vias in accordance with one embodiment of the present invention;

FIG. 8 is a top view of a structure having a plurality of vias in a multilayer structure according to another embodiment of the present invention;

FIG. 9 is a cross-sectional view of a structure after forming a cavity in a substrate according to an embodiment of the present invention;

FIG. 10 is a cross-sectional view of the structure after filling a dielectric layer into the via hole according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view of a through-silicon-via in a substrate according to an embodiment of the invention;

FIG. 12 is a cross-sectional view of a structure with a cavity penetrating through a substrate according to an embodiment of the present invention;

FIG. 13 is a cross-sectional view of a dielectric layer including at least one via in accordance with an embodiment of the present invention;

FIG. 14 is a cross-sectional view of a structure after forming a cavity in a substrate according to one embodiment of the present invention;

fig. 15-17 are schematic diagrams illustrating a method of fabricating a device including a PMUT according to an embodiment of the invention.

Description of reference numerals:

102 … substrate

102D,150H … depth

104a … first surface

104B … second surface

104C … corner

106 … groove

106L … distance

108 … first dielectric layer

108A … Upper side wall

108B … lower side wall

108H,114H,130H,208H … height

110 … groove

110A,112A … Top surface

112 … projection

114 … second dielectric layer

116,216 … barrier structure

120 … multilayer structure

122 … bottom electrode

124, 128 … piezoelectric layer

126 … top electrode

127 … seed layer

129 … passivation layer

130,130a,130b … through-hole

132 … electric conduction pad

136,208 … dielectric layer

138 … film layer

140 … contact hole

150,152 … cavity

150A … bottom surface

150L,152L … diameter

160 … through-silicon-via

250 … lower cavity

252 … Upper Cavity

Detailed Description

The invention is further described with reference to the following figures and detailed description of embodiments.

The present invention provides several different embodiments that can be used to implement different functions of the present invention. For simplicity of illustration, examples of specific components and arrangements are also described. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of the first feature being formed over or on the second feature may refer to the first feature being in direct contact with the second feature, or to the second feature being in the presence of other features, such that the first feature is not in direct contact with the second feature. Moreover, various embodiments of the present invention may use repeated reference numerals and/or textual labels. These repeated reference numbers and lettering are used for brevity and clarity of description and are not intended to indicate a relationship between the various embodiments and/or configurations.

In addition, for spatially related descriptive words mentioned in the present invention, for example: the use of "under", "lower", "under", "over", "under", "top", "bottom" and the like in describing, for purposes of convenience, the relative relationship of one element or feature to another element(s) or feature in the drawings. In addition to the orientations shown in the drawings, these spatially relative terms are also used to describe possible orientations of the semiconductor device during and during use. With respect to the swinging direction of the semiconductor device (rotated 90 degrees or other orientations), the spatially relative descriptions for describing the swinging direction should be interpreted in a similar manner.

Although the present invention has been described using terms such as first, second, third, etc. to describe various elements, components, regions, layers and/or sections, it should be understood that such elements, components, regions, layers and/or sections should not be limited by such terms. These terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block, and do not denote any order or importance, nor do they denote any order or importance, but rather the term "sequence" or "sequence" is used to distinguish one element, component, region, layer and/or block from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of embodiments of the present invention.

The terms "about" or "substantially" as used herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate, i.e., the meaning of "about" or "substantially" may be implied without specifically stating "about" or "substantially".

The particular order or hierarchy of process blocks disclosed in the process/flow diagrams below is to be understood as exemplary illustrations. It will be appreciated that the specific order or hierarchy of process blocks illustrated in the process/flow diagrams can be rearranged as a function of design preferences. Furthermore, portions of the flow diagrams may be combined or omitted. The accompanying method claims present elements of the various flow diagrams in a sample order, and are not intended to imply that the method claims are limited to the specific order or hierarchy presented.

Although the technical solutions of the present invention are described below by way of specific embodiments, the inventive principles of the present invention may be applied to other embodiments. Moreover, certain details may be omitted so as not to obscure the spirit of the invention, the details being omitted being within the knowledge of a person of ordinary skill in the art.

In order to enable one of ordinary skill in the art to practice the present invention, a method of fabricating a piezoelectric micromachined ultrasonic transducer will be described. Since the piezoelectric micromachined ultrasonic transducer can be fabricated by a standard CMOS process, related electronic components such as field effect transistors, amplifiers and integrated circuits can also be fabricated on the same substrate of the piezoelectric micromachined ultrasonic transducer by the same CMOS process.

FIG. 1 is a cross-sectional view of a structure after forming a trench in a substrate according to an embodiment of the present invention. As shown in fig. 1, a substrate 102 is provided, the substrate 102 having two opposite surfaces, such as a first surface 104A and a second surface 104B. The substrate 102 may be a semiconductor substrate, such as a crystalline silicon or AlN substrate, and the thickness of the substrate 102 may be 30 to 600 μm. The trench 106 may be formed in the substrate 102 by anisotropic etching, such as Reactive Ion Etching (RIE). Each trench 106 may be a deep trench having a depth 102D of 10-40 μm (e.g., 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, or 40 μm), and a distance 106L between two adjacent trenches 106 is 500 μm to 3 mm. Since the position of each trench 106 can be precisely defined by the photolithography process, the distance 106L between each trench 106 can be precisely controlled without deviating from a predetermined value.

FIG. 2 is a cross-sectional view of the structure after depositing a first dielectric layer in the trench according to one embodiment of the present invention. As shown in fig. 2, a first dielectric layer 108 may be deposited on the substrate 102 and fill the trench 106. The first dielectric layer 108 may be made of silicon oxide (SiOx), silicon nitride (SiNx), aluminum nitride (AIN), aluminum oxide (a1203), other suitable dielectric materials, or combinations thereof. According to an embodiment of the invention, the composition of the first dielectric layer 108 is different from the composition of the substrate 102.

FIG. 3 is a cross-sectional view of the structure after forming a recess to expose the dielectric layer in the trench according to an embodiment of the present invention. As shown in fig. 3, photolithography and etching processes may be performed to remove portions of the first dielectric layer 108 and portions of the substrate 102. After the photolithography and etching processes are completed, the recess 110 is formed outside the trench 106, so that the first dielectric layer 108 originally located in the trench 106 is exposed. In addition, the protrusion 112 of the substrate 102 may be formed between two opposite grooves 110. The top surface 110A of the substrate 102 exposing each recess 110 may be lower than the top surface 112A of the protrusion 112 of the substrate 102.

FIG. 4 is a cross-sectional view of the structure after depositing a second dielectric layer on the first dielectric layer according to one embodiment of the present invention. After the process shown in fig. 3, a second dielectric layer 114 may be deposited over the first dielectric layer 108 and fill the recess 110. The composition of the second dielectric layer 114 may be silicon oxide (SiOx), silicon nitride (SiNx), aluminum nitride (AIN), aluminum oxide (a1203), other suitable dielectric materials, or combinations thereof. According to an embodiment of the invention, the composition of the second dielectric layer 114 may be the same as the composition of the first dielectric layer 108. Furthermore, the top surface 114A of the second dielectric layer 114 located outside the trench 106 may be flush with or higher than the top surface 112A of the protrusion 112.

FIG. 5 is a cross-sectional view of a structure after planarization of a first dielectric layer and a second dielectric layer disposed on a substrate according to an embodiment of the invention. As shown in fig. 5, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be performed to planarize the top surfaces of the protrusion 112, the first dielectric layer 108 and the second dielectric layer 114. When the planarization process is completed, the height 108H of the first dielectric layer 108 may be higher than the height 114H of the second dielectric layer 114. In addition, the first dielectric layer 108 may serve as a blocking structure 116 for defining the position of a cavity formed in a subsequent process.

FIG. 6 is a cross-sectional view of a substrate after forming a multi-layer structure thereon according to one embodiment of the present invention. As shown in fig. 6, an optional seed layer 127, a bottom electrode 122, a piezoelectric layer 124, a piezoelectric layer 128, a top electrode 126, and a passivation layer 129 may be deposited on the substrate 102 and the first dielectric layer 108 to form a multi-layer structure 120 disposed on the substrate 102. The piezoelectric layer 128 may be composed of a piezoelectric material, such as, but not limited to, aluminum nitride (AlN), scandium-doped aluminum nitride (AlScN), lead zirconate titanate (PZT), zinc oxide (ZnO), polyvinylidene fluoride (PVDF), or lead magnesium niobate-lead titanate (PMN-PT). According to an embodiment of the present invention, piezoelectric layer 128 and piezoelectric layer 124 may have the same composition when piezoelectric layer 128 and piezoelectric layer 124 are formed in the same deposition process, but is not limited thereto. An optional seed layer 127, such as SiO2, SiON, AlN, or AlScN, may be disposed between the bottom electrode 122 and the substrate 102. The surface texture of the seed layer 127 may affect the crystallinity of the layers deposited thereon. The bottom electrode 122 and the top electrode 126 may be the same or different materials composed of molybdenum (Mo), titanium (Ti), aluminum (Al) or platinum (Pt). Piezoelectric layer 124 can be composed of a piezoelectric material such as, but not limited to, AlN, AlScN, PZT, ZnO, PVDF, PMN-PT. The passivation layer 129 may serve to passivate and/or protect the underlying piezoelectric layers 124, 128 and top electrode 126, and may be composed of an insulating material or a piezoelectric material. According to some embodiments of the present invention, the passivation layer 129 may be composed of SiO2, SiON, AlN, AlScN, PZT, ZnO, PVDF, PMN-PT, but is not limited thereto.

In addition, at least one conductive pad 132 is formed in the piezoelectric layer 128 and is electrically connected to the bottom conductive layer 122 and the top conductive layer 126. After forming the multi-layered structure 120, at least one via 130 having a height 130H, such as the via 130a and the via 130b, may be formed in the multi-layered structure 120 to expose the top surface 112A of the protrusion 112 from the bottom of the via 130. According to an embodiment of the invention, the height of the blocking structure 116 may be greater than 1/2, for example more than twice the average height of the vias 130, the average height of the vias 130.

According to the structure shown in fig. 6, although the through-holes 130 seem to be separated from each other, some of the through-holes 130 may be connected to each other, so that the through-holes 130 may constitute a continuous pattern, such as a circular groove, a polygonal groove, or an arc-shaped groove, in a plan view. Fig. 7 is a schematic top view of a structure having a plurality of through holes in a multi-layer structure, wherein fig. 6 is a schematic view along a cut line a-a' in fig. 5. As shown in fig. 7, the through-hole 130 includes a circular through-hole 130a disposed at the center and a ring-shaped through-hole 130b surrounding the circular through-hole 130 a. Further, the blocking structure 116 shown in fig. 6 may be a continuous structure disposed along the circumference of the annular through hole 130 b.

The shape of each through-hole 130 is not limited to the through-hole shape shown in fig. 7. For example, as shown in fig. 8(a), the through-hole 130 includes a circular through-hole 130a disposed at the center and a plurality of separate arc-shaped through-holes 130b disposed around the circular through-hole 130 a. Further, as shown in fig. 8(b), all the through holes 130 are circular through holes 130a,130b, randomly or orderly distributed in the multilayer structure 120.

FIG. 9 is a cross-sectional view of the structure after forming a cavity in the substrate according to one embodiment of the present invention. As shown in fig. 9, a cavity 150 having a predetermined diameter 150L may be formed by etching the front surface of the substrate 102. The etching process may include the steps of: the etchant is supplied to the substrate 102 through the via hole 130 until the bottom surface 150A of the cavity is etched to a specific depth 150H having a depth of 5-35 μm, such as 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, or 35 μm, but is not limited thereto. According to an embodiment of the invention, when the barrier structure 116 is silicon oxide and the substrate 102 is silicon, the etchant may be sulfur hexafluoride (SF 6). During the etching process, since the etching selectivity of the substrate 102 to the barrier structure 116 and the seed layer 127 in the multi-layer structure 120 is greater than 10, only the substrate 102 that is in direct contact with the etchant and not protected by the barrier structure 116 will be etched. In other words, during the step of forming the cavity 150 in the substrate 102, the etchant may be confined in the area defined by the barrier structure 116. According to an embodiment of the present invention, the inner sidewall of the blocking structure 116 may coincide with the sidewall of the cavity 150. In addition, the bottom surface 150A of the cavity 150 is higher than the bottom surface of the barrier structure 116, so that the lower portion of the barrier structure 116 can remain embedded in the substrate 102. Also, after the cavity 150 is formed, at least one corner 104C of the substrate 102 is adjacent to the bottom surface of the multi-layer structure 120, and the corner 104C of the substrate 102 may directly contact the barrier structure 116. According to an embodiment of the invention, the top surface of the blocking structure 116 may be higher than the highest point of the corner 104C of the substrate 102.

Fig. 10 is a cross-sectional view of the structure after filling the dielectric layer into the via hole according to an embodiment of the present invention. As shown in fig. 10, a dielectric layer 136 (or referred to as an elastic layer) having a desired elasticity may be formed on the multi-layered structure and filled into the via 130 in order to mechanically support the multi-layered structure and adjust the resonant frequency of the corresponding PMUT. Thus, a film 138 comprising at least the bottom electrode 122, the piezoelectric layer 124, the top electrode 126 and the dielectric layer 136 is obtained. Since the diameter or size of each via 130 is sufficiently small (e.g., 10-300 nm), the upper portion of each via 130 can be easily blocked or sealed by the dielectric layer 136 during the deposition process to form the dielectric layer 136. Thus, the dielectric layer 136 is not deposited in the cavity 150. In addition, the dielectric layer 136 may serve as a protective layer covering a portion of the conductive pad 132. A contact hole 140 may be further formed in the dielectric layer 136 to expose a portion of the conductive pad 132. Additional conductive traces (not shown) may be electrically connected to the conductive pads 132 to transmit electrical signals into the film 138 or out of the film 138. It should be noted that, according to an embodiment of the present invention, since the thickness or elasticity of the stacked layers disposed under the dielectric layer 136 is much smaller than that of the dielectric layer 136, the mechanical behavior of the film 138 is mainly dominated by the dielectric layer 136 in the film 138.

During operation of the PMUT, the membrane layer 138 suspended over the cavity 150 may vibrate when sound waves exert an acoustic pressure on the membrane layer 138 or when an external electrical signal is applied to the membrane layer 138. By providing the barrier structure 116, the size and position of the film 138 suspended over the cavity 150 may be precisely defined, and the cavity 150 may be formed by etching the front surface of the substrate 102. Therefore, the uniformity of the resonance frequency of each PUMT can be improved, and the time taken to form the cavity can be reduced.

Other electronic components, such as conductive pads or Through Silicon Vias (TSVs), may also be formed on the substrate 102 or in the substrate 102 according to some embodiments of the invention. FIG. 11 is a cross-sectional view of a through-silicon-via in a substrate according to an embodiment of the invention. As shown in fig. 11, the through-silicon-via 160 penetrating the substrate 102 may be formed such that both ends of the through-silicon-via 160 may be exposed from the first surface 104a and the second surface 104b of the substrate 102, respectively. In addition, two conductive pads 132 are provided on the substrate 102. One of the conductive pads 132 may be electrically connected to an electrode of the PMUT, while the other of the conductive pads 132 may be partially formed in the second dielectric layer and electrically connected to the through-silicon-via 160.

In accordance with another embodiment of the present invention, additional photolithography and etching processes may be performed on the backside of the substrate 102 shown in FIG. 10 to form another cavity below the cavity 150. FIG. 12 is a cross-sectional view of a through-silicon-via in a substrate according to an embodiment of the invention. As shown in fig. 12, another cavity 152 may be formed by etching the back side of the substrate 102 to further form below the cavity 150. The shape of the cavity 152 may be designed according to the shape of the cavity 150. However, the diameter 152L of the cavity 152 may be slightly smaller than the diameter 150L of the cavity 150. For example, the cavity 150 may be circular with a diameter of 1mm when viewed from above, and the cavity 152 may also be circular, but with a relatively small diameter, such as 0.8 mm.

The method of fabricating the barrier structure is not limited to the above-described embodiments. According to some embodiments of the present invention, the barrier structure may also be fabricated by performing the processes shown in fig. 13 and 14.

FIG. 13 is a cross-sectional view of a dielectric layer having at least one via according to an embodiment of the present invention. As shown in fig. 13, the structure shown in fig. 13 can be fabricated by the processes shown in fig. 1 to 6. However, in the embodiment shown in fig. 13, the first dielectric layer 108 is not only filled into the trench 106, but also disposed between the multi-layer structure 120 and the substrate 102. Therefore, the entire multi-layer structure 120 can be separated from the substrate 102 by disposing the first dielectric layer 108. In addition, the at least one via 130 may extend into the first dielectric layer 108 to expose a portion of the surface of the substrate 102.

FIG. 14 is a cross-sectional view of the structure after forming a cavity in the substrate according to one embodiment of the present invention. As shown in fig. 14, an etching process may be performed to form a cavity 150 in the substrate 102 using a process similar to the embodiment of fig. 9. However, according to the embodiment shown in fig. 14, the etchant may not only etch the substrate 102, but also etch the first dielectric layer 108 disposed under the multi-layer structure 120. Therefore, when the etching process is completed, the first dielectric layer 108 above the cavity 150 may be completely removed, thereby exposing the bottom surface of the multi-layer structure 150 above the cavity 150. In addition, when the etching process is completed, the upper sidewall 108A of the barrier structure 116 may be misaligned (misalign) with the lower sidewall 108B of the barrier structure 116, but is not limited thereto.

Fig. 15-17 illustrate a process flow of a method of fabricating a device including a PMUT according to one embodiment of the invention. As shown in fig. 15, a substrate 102 having a protrusion 112 may be provided. The substrate 102 may be a semiconductor substrate, such as a crystalline silicon or AlN substrate, and the thickness of the substrate 102 may be 30 to 600 μm. A dielectric layer 208, such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum nitride (AIN), aluminum oxide (a1203), other suitable dielectric materials, or combinations thereof, may be deposited on the substrate 102 to surround the protrusion 112. The top surface of the dielectric layer 208 may be made flush with the top surface of the protrusion 112 by using a CMP process, but is not limited thereto. The thickness (or height 208H) of the dielectric layer 208 is set within a range of 3-15 μm, such as 3 μm, 5 μm, 9 μm, 11 μm, 13 μm, or 15 μm, but is not limited thereto.

As shown in fig. 16, the structure shown in fig. 16 can be fabricated by a process similar to that shown in fig. 6. However, in fig. 16, no trench may be formed in the substrate 102. In a subsequent etching process, the dielectric layer 208 disposed on the substrate 102 may serve as a barrier structure 216 against etching. In addition, the height 208H of the barrier structures 216 may be greater than half the average height 130H of the vias 130.

As shown in fig. 17, the structure shown in fig. 17 can be fabricated by a process similar to that shown in fig. 9. According to the embodiment shown in fig. 17, the etchant may etch not only the substrate 102 between the barrier structures 216, but also the substrate 102 under the barrier structures 216. In addition, two cavities (a lower cavity 250 and an upper cavity 252) having different diameters may be formed in the substrate 102. For example, the maximum diameter 250L of the lower cavity 250 may be greater than the maximum diameter 252L of the upper cavity 252. Additionally, the sidewalls of the barrier structure 216 may coincide with the sidewalls of the upper cavity 252. Further, the shape of the lower cavity 250 may be formed to correspond to the shape of the upper cavity 252 when viewed from a top view. For example, when the top profile of the upper cavity 252 is a circle with a diameter of 1mm, the top profile of the lower cavity 250 may also be a circle, but with a relatively larger diameter, such as 1.2 mm. Since the thickness (or height 208H) of the barrier structure 216 is set within a range of 3-15 μm, the barrier structure 216 can maintain sufficient rigidity even if a portion of the barrier structure 216 is not supported by the substrate 102. Thus, the blocking structure 216 does not deform or vibrate during operation of the PMUT and may be used to accurately define the dimensions of the film layers disposed over the lower cavity 250 and the upper cavity 252.

According to an embodiment of the present invention, the multi-layer structure disposed on the front surface of the substrate includes at least one via hole allowing an etchant to flow therethrough and etch the substrate under the film. Thus, the cavity may be formed by etching the front surface of the substrate. In addition, the barrier structure disposed below the multi-layer structure may be used to define the dimensions of the film layer that may vibrate during PMUT operation. Therefore, the manufacturing cost of the PMUT can be reduced, and the reliability and the electrical property of the PMUT are effectively improved.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.

Claims (19)

1. A piezoelectric micromachined ultrasonic transducer, comprising:

a substrate including a corner portion;

a cavity disposed within the substrate;

a barrier structure contacting the corner of the substrate and the cavity; and

a multilayer structure disposed over the cavity and attached to the barrier structure, wherein the multilayer structure includes at least one via contacting the cavity.

2. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein the height of the blocking structure is greater than 1/2 height of the at least one via.

3. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein the multilayer structure comprises at least two electrodes and a piezoelectric layer disposed between the at least two electrodes.

4. The piezoelectric micromachined ultrasonic transducer of claim 1, further comprising a dielectric layer disposed on the multilayer structure and filling an upper portion of the at least one via.

5. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein the substrate is made of a material different from that of the barrier structure, and when gaseous hydrofluoric acid is used as an etchant, an etching selectivity ratio of the etchant to the substrate and the barrier structure is greater than 10.

6. The piezoelectric micromachined ultrasonic transducer of claim 5, wherein the substrate is comprised of crystalline silicon and the barrier structure is comprised of silicon oxide.

7. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein a lower portion of the blocking structure is embedded in the substrate.

8. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein a bottom surface of the cavity is higher than a bottom surface of the barrier structure.

9. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein a sidewall of the blocking structure coincides with a sidewall of the cavity.

10. The piezoelectric micromachined ultrasonic transducer of claim 1, further comprising a dielectric layer disposed between the substrate and the multilayer structure, wherein the dielectric layer and the barrier structure have the same composition.

11. The piezoelectric micromachined ultrasonic transducer of claim 1, further comprising another cavity disposed below and in direct contact with the cavity, wherein the diameter of the other cavity is smaller than the diameter of the cavity.

12. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein an upper sidewall of the barrier structure is not aligned with a lower sidewall of the barrier structure.

13. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein the blocking structure is extended to cover a top surface of the substrate.

14. The piezoelectric micromachined ultrasonic transducer of claim 1, wherein a portion of the cavity is located below the barrier structure.

15. The piezoelectric micromachined ultrasonic transducer of claim 1, further comprising another cavity disposed above the cavity, wherein a sidewall of the blocking structure coincides with a sidewall of the another cavity.

16. A method for manufacturing a piezoelectric micromechanical ultrasonic transducer is characterized by comprising the following steps:

providing a substrate;

forming a barrier structure, wherein the barrier structure is contacted with the substrate;

forming a multi-layer structure disposed on the substrate and the barrier structure;

forming at least one through hole penetrating through the multilayer structure; and the number of the first and second groups,

providing an etchant to the substrate through the at least one via to etch a portion of the substrate to form a cavity, wherein the barrier structure directly contacts the cavity.

17. The method of fabricating a piezoelectric micromachined ultrasonic transducer according to claim 16, wherein the step of forming the barrier structure contacting the substrate comprises:

forming two trenches in the substrate;

filling the two trenches with a first dielectric layer;

etching the substrate to expose the first dielectric layer in each trench;

forming a second dielectric layer on the first dielectric layer and the substrate; and the number of the first and second groups,

and flattening the first dielectric layer and the second dielectric layer until the top surfaces of the first dielectric layer and the second dielectric layer are flush with the top surface of the substrate.

18. The method of fabricating a piezoelectric micromachined ultrasonic transducer of claim 16, further comprising:

forming a dielectric layer on the substrate to fill the plurality of trenches;

in forming the multilayer structure, the multilayer structure is disposed on the substrate and the dielectric layer;

when the at least one through hole is formed, the at least one through hole penetrates through the multilayer structure and the dielectric layer arranged on the substrate; and

in the step of etching a portion of the substrate to form the cavity, the dielectric layer over the cavity is removed.

19. The method of fabricating a piezoelectric micromachined ultrasonic transducer according to claim 16, wherein a bottom surface of the barrier structure is exposed from the cavity in the step of etching a portion of the substrate to form the cavity.

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