TWI722485B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI722485B
TWI722485B TW108124414A TW108124414A TWI722485B TW I722485 B TWI722485 B TW I722485B TW 108124414 A TW108124414 A TW 108124414A TW 108124414 A TW108124414 A TW 108124414A TW I722485 B TWI722485 B TW I722485B
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Taiwan
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layer
dielectric
barrier layer
semiconductor structure
silicon
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TW108124414A
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TW202013611A (zh
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張根育
蔡純怡
林威戎
蔡明興
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種半導體結構的形成方法，包含：沿著介電層中的開口之側壁形成介電焊接層；於所述介電焊接層上形成障壁層；回蝕刻所述障壁層的一部分以暴露出介電焊接層的上部分之側表面；以及於所述介電焊接層的上部分之側表面上和障壁層上形成導電材料。本發明實施例也提供一種半導體結構。

Description

半導體結構及其形成方法
本發明實施例係關於半導體結構及其形成方法，且特別是有關於半導體結構中的接觸導電部件及其形成方法。
半導體積體電路（integrated circuit，IC）工業已歷經快速的發展。積體電路材料及設計在技術上的進步已產生許多世代的積體電路，每一代生產的積體電路變得比先前生產的積體電路更小且其電路也變得更複雜。在積體電路發展的進程中，功能性密度（例如，每一個晶片區域中內連接裝置的數目）已經普遍增加，而幾何尺寸（例如，製程中所能創造出最小的元件或線路）則是普遍下降。這種微縮化的過程通常可藉由增加生產效率及降低相關支出提供許多利益。
隨著裝置的微縮化，製造商開始使用新的和不同的材料及/或材料的組合來加速裝置的微縮化。單獨或結合微縮化與新的和不同的材料，也帶來了在前幾代更大的幾何形狀下不曾存在的挑戰。
根據本發明的一實施例，提供一種半導體結構的形成方法，包含：沿著介電層中的開口之側壁形成介電焊接層（dielectric welding layer）；於所述介電焊接層上形成障壁層；回蝕刻所述障壁層的一部分以暴露出介電焊接層的上部分之側表面；以及於所述介電焊接層的上部分之側表面上和障壁層上形成導電材料。
根據本發明的另一實施例，提供一種半導體結構，包含：介電層，具有側壁，所述介電層位於基板之上；介電焊接層，沿著所述側壁，所述介電焊接層暴露出側壁的上部分；障壁層，沿著所述介電焊接層，所述障壁層暴露出介電焊接層的上部分；以及導電材料，沿著所述障壁層、所述側壁的所述上部分和所述介電焊接層的所述上部分。
又根據本發明的另一實施例，提供一種半導體結構，包含：介電層；導電材料，形成於所述介電層中並由障壁層側向地連接（laterally bound）；介電焊接層，側向地位於所述障壁層和所述介電層之間，其中所述障壁層和所述介電焊接層沿著所述介電層的側壁具有不一致（mismatched）的高度。
以下揭示提供許多不同的實施例或是例子來實行本發明實施例之不同部件。以下描述具體的元件及其排列的例子以簡化本發明實施例。當然這些僅是例子且不該以此限定本發明實施例的範圍。例如，在描述中提及第一個部件形成於第二個部件“之上”或“上”時，其可能包括第一個部件與第二個部件直接接觸的實施例，也可能包括兩者之間有其他部件形成而沒有直接接觸的實施例。另外，本發明可能在不同實施例中重複參照符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間的關係。
此外，其中用到與空間相關的用詞，例如： “在…下方”、“下方”、“較低的”、 “上方”、 “較高的”、及其類似的用詞係為了便於描述圖式中所示的一個元件或部件與另一個元件或部件之間的關係。這些空間關係詞係用以涵蓋圖式所描繪的方位之外的使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位（旋轉90度或其他方位），則其中使用的空間相關形容詞也可相同地照著解釋。
本發明實施例廣泛地提供涉及導電部件的示例實施例，例如金屬接觸（contacts）、導孔（vias）、導線等，以及用於形成那些導電部件的方法。在一些示例中，回拉（pull-back）（例如，蝕刻）形成於穿過介電層的開口中之障壁層及/或焊接層（welding layer），以在低於介電質的頂表面之開口中產生高度差。因此，進行回拉（例如，蝕刻）以移除障壁層及/或焊接層在開口角落的多餘結構，進而改善輪廓控制和尺寸精度。除此之外，這有助於在導電材料沉積於障壁層上及/或黏附（adhesion）期間減少空隙的形成。
此處的示例實施例是在電晶體的產線前段（Front End of the Line，FEOL）及/或產線中段（Middle End of the Line，MEOL）製程中形成導電部件的背景下進行描述。可將本發明一些方面實現在其他製程及/或其他裝置中。例如，示例實施例可以在產線後段（Back End of the Line，BEOL）製程中實現。描述了示例方法和結構的一些變化型（variations）。儘管可以特定順序來描述方法實施例，但仍然可用任何邏輯順序進行各種其他方法實施例，並且可包含比此處描述之更少或更多的步驟。在一些圖式中，可省略其中所示之元件或部件的一些參考數字以避免模糊其他元件或部件；這是為了便於描述這些圖式。
第1圖根據一些實施例顯示形成半導體裝置結構的製程100之示例性流程圖。第2圖至第12圖根據一些實施例顯示在形成導電部件的示例方法期間各個階段的各個中間結構之視圖。如下所述，中間結構用於場效電晶體（Field Effect Transistors，FET）的實現。其他結構可以在其他示例實施例中實現。
如圖式所示和此處所述，裝置為場效電晶體（FET），其可為平面場效電晶體或鰭式場效電晶體（FinFET）。在其他實施方式中，裝置可包含垂直環繞式閘極（Vertical Gate All Around，VGAA）場效電晶體、水平環繞式閘極（Horizontal Gate All Around，HGAA）場效電晶體、雙極型接面電晶體（bipolar junction transistors，BJT）、二極體、電容器、電感器、電阻器等。在平面場效電晶體及/或鰭式場效電晶體中，閘極堆疊32形成於半導體基板30的主動區域上，如第2圖所示。在平面場效電晶體中，主動區域可以是由隔離區域所劃定的半導體基板30之頂表面上的部分。在鰭狀場效電晶體中，主動區域可以是從半導體基板30上的隔離區域之間突出的三維鰭片。半導體基板30可為或可包含塊狀半導體基板、絕緣體上半導體（semiconductor-on-insulator，SOI）基板、或另一種基板。半導體基板30的半導體材料可包含或可為像是矽（例如，像是Si>100>或Si>111>的晶體矽）或鍺的元素半導體、化合物或合金半導體、其類似材料、或前述之組合。半導體基板30的半導體材料可為經摻雜（像是p型或n型摻雜物）或未經摻雜的。也可以使用其他基板，例如多層或梯度基板。在一些實施例中，半導體基板的半導體材料可包含像是矽（Si）和鍺（Ge）的元素半導體；包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦的化合物半導體；包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP的合金半導體；或前述之組合。
閘極堆疊32可為類似於前閘極（gate-first）製程中的操作閘極堆疊，或者可為類似於替代閘極製程（replacement gate process）中的虛設閘極堆疊。在替代閘極製程中，每一個閘極堆疊32可包括位於主動區域之上的介電層、位於介電層之上的閘極層、以及（在一些情況下）位於閘極層之上的罩幕層，所述閘極堆疊32隨後被替換為可包含高介電常數（high-k）介電材料的金屬閘極結構。高介電常數介電材料可具有大於約7.0的介電常數（k）值，並且可包含鉿（Hf）、鋁（Al）、鋯（Zr）、鑭（La）、鎂（Mg）、鋇（Ba）、鈦（Ti）、鉛（Pb）的金屬氧化物或金屬矽酸鹽、前述之多層、或前述之組合。閘極層（例如，閘極電極）可包含或可為矽（例如，經摻雜或未經摻雜的多晶矽）、含金屬的材料（像是鈦、鎢、鋁、釕、TiN、TaN、TaC、Co、前述之組合（像是可隨後形成的矽化物）、或前述之多層）。罩幕層可包含或可為氮化矽、氮氧化矽、碳氮化矽、其類似材料、或前述之組合。用以形成或沉積介電層、閘極層、和罩幕層的製程包含熱及/或化學成長、化學氣相沉積（Chemical Vapor Deposition，CVD）、電漿增強化學氣相沉積（Plasma-Enhanced CVD，PECVD）、分子束沉積（Molecular-Beam Deposition，MBD）、原子層沉積（Atomic Layer Deposition，ALD）、物理氣相沉積（Physical Vapor Deposition，PVD）、和另一種沉積技術。然後，可將用於閘極堆疊32的層圖案化為閘極堆疊32，例如使用微影和一個或多個蝕刻製程。舉例而言，可透過使用像是旋轉塗佈將光阻形成於罩幕層（或例如閘極層，如果沒有形成罩幕層時）上，且可透過使用合適的光罩使光阻暴露於光底下以將其圖案化。接著，可根據所使用的是正型或負型光阻來移除光阻的暴露或未暴露的部分。然後，可利用像是一個或多個合適的蝕刻製程來將光阻的圖案轉移到閘極堆疊32的層。所述一個或多個蝕刻製程可包含反應性離子蝕刻（reactive ion etch，RIE）、中性粒子束蝕刻（neutral beam etch，NBE）、其類似方法、或前述之組合。蝕刻可為異向性（anisotropic）的。隨後，舉例而言，在灰化或濕式剝離製程中將光阻移除。
閘極間隔物34沿著閘極堆疊32的側壁形成並形成於半導體基板30上的主動區域之上。舉例而言，可透過共形沉積用於閘極間隔物34的一層或多層並異向性蝕刻所述一層或多層來形成閘極間隔物34。閘極間隔物34可包含或可為氮化矽、氮氧化矽、碳氮化矽、其類似材料、前述之多層、或前述之組合。
源/汲極區域36形成於閘極堆疊32相對兩側上的主動區域中。在一些示例中，透過使用閘極堆疊32和閘極間隔物34做為罩幕，將摻雜物植入主動區域中來形成源/汲極區域36。因此，可透過在每一個閘極堆疊32的相對兩側上進行佈植（implantation）來形成源/汲極區域36。在其他示例中，可使用閘極堆疊32和閘極間隔物34做為罩幕來使主動區域凹陷，且可在凹陷中磊晶成長磊晶的源/汲極區域36。磊晶的源/汲極區域36可相對於主動區域升高。可透過磊晶成長期間的原位摻雜及/或在磊晶成長後的佈植而使磊晶的源/汲極區域36經摻雜。磊晶的源/汲極區域36可包含或可為矽鍺、碳化矽、矽磷、矽碳磷（silicon carbon phosphorus）、鍺、III-V族化合物半導體、II-VI族化合物半導體、或其類似材料。可透過合適的磊晶成長或沈積製程在凹陷中形成磊晶的源/汲極區域36。在一些示例中，磊晶的源/汲極區域36可具有刻面（facets），所述刻面可對應於基板30的晶面。因此，可透過磊晶成長及可能的佈植，在每一個閘極堆疊32的相對兩側上形成源/汲極區域36。
第一層間介電質（interlayer dielectric，ILD）38形成於閘極堆疊32之間和半導體基板30之上。第一層間介電質38沉積於主動區域、閘極堆疊32、和閘極間隔物34之上。在一些示例中，蝕刻停止層（未繪示）可共形地沉積於主動區域、閘極堆疊32、和閘極間隔物34之上。通常，蝕刻停止層可在形成例如接觸或導孔時提供停止蝕刻製程的機制。蝕刻停止層可由具有與相鄰層（例如，第一層間介電質38）不同的蝕刻選擇性之介電材料形成。蝕刻停止層可包括或可為氮化矽、碳氮化矽、碳氧化矽、碳氮化物、其類似材料、或前述之組合，且可透過化學氣相沈積（CVD）、電漿增強化學氣相沈積（PECVD）、原子層沉積（ALD）、或另一種沉積技術來形成蝕刻停止層。第一層間介電質38可包括或可為二氧化矽、低介電常數（low-k）介電材料（例如，介電常數低於二氧化矽的介電常數之材料）、氮氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、硼磷矽玻璃（borophosphosilicate glass，BPSG）、未經摻雜的矽酸鹽玻璃（undoped silicate glass，USG）、氟化矽酸鹽玻璃（fluorinated silicate glass，FSG）、有機矽酸鹽玻璃（organosilicate glasses，OSG）、SiOx Cy 、旋塗玻璃、旋塗聚合物、矽碳材料、前述之化合物、前述之複合物、其類似材料、或前述之組合。可透過旋轉塗佈、化學氣相沈積（CVD）、流動式化學氣相沈積（Flowable CVD，FCVD）、電漿增強化學氣相沈積（PECVD）、物理氣相沈積（PVD）、或另一種沈積技術來形成第一層間介電質38。可在沉積第一層間介電質38後將其平坦化。可進行像是化學機械研磨（Chemical Mechanical Polish，CMP）的平坦化製程以將第一層間介電質38平坦化。
第二層間介電質（ILD）40形成於第一層間介電質38之上，如第3圖所示。第二層間介電質40沉積於第一層間介電質38之上。第二層間介電質40是由類似於用以形成第一層間介電質38的材料所組成。在沉積第二層間介電質40之後，可透過例如化學機械研磨（CMP）將其平坦化。第一層間介電質38和第二層間介電質40的厚度可介於約50 nm至約1200 nm的範圍內。第一層間介電質38和第二層間介電質40的組合厚度可介於約100 nm至約2400 nm的範圍內。
再參照第1圖所描繪的製程100，於操作106進行圖案化製程以形成穿過第二層間介電質40和第一層間介電質38的開口42、44、和46，如第4圖所示。開口42(又稱為第一開口)暴露出閘極堆疊32和相鄰的（adjoining）源/汲極區域36。因此，第一開口42用以在暴露的閘極堆疊32和相鄰的源/汲極區域36之間形成對接的（butted）導電部件。開口44(又稱為第二開口)暴露出源/汲極區域36，因此第二開口44用以形成暴露的源/汲極區域36之導電部件。開口46(又稱為第三開口)暴露出閘極堆疊32，因此第三開口46用以形成暴露的閘極堆疊32之導電部件。可使用例如合適的微影和蝕刻製程來形成開口42、44、和46。
於操作108，在開口42、44、和46中形成焊接層50，接著共形地形成第一障壁層52於其上。在一些實施例中，焊接層50也稱為潤濕層（wetting layer）或黏膠層（glue layer）。為了後續的退火製程，將焊接層50圖案化以使焊接層50形成於開口42、44、46的側壁上，並同時暴露出下方的源/汲極區域36，如第5圖所示。隨後，第一障壁層52共形地形成於開口42、44、和46中的焊接層50上，並共形地形成於暴露的源/汲極區域36、暴露的閘極堆疊32、第二層間介電質40的側壁上、和第二層間介電質40的頂表面上，如第6圖所示。在一些實施例中，視需要，第一障壁層52也稱為黏附層或抗反射塗層（anti-reflection coating，ARC）。
在一示例中，焊接層50可為或可包括含矽的介電材料，像是氧化矽、氮化矽、碳化矽、碳氧化矽、氮氧化矽、其類似材料、或前述之多層。可透過電漿增強化學氣相沉積（PECVD）、低壓化學氣相沉積（low pressure CVD，LPCVD）、流動式化學氣相沉積（FCVD）、原子層沉積（ALD）、或另一種沈積技術來形成焊接層50。據信由焊接層50提供的介電材料可以在層間介電質38、40和第一障壁層52之間提供具有良好的界面黏附性和整合性的良好界面接合（bonding），這將在下文進一步討論。來自焊接層50的介電材料可包含矽元素和其他元素，像是氮、氧、及/或碳元素。因此，來自焊接層50的矽元素可具有用以接合在第一層間介電質38和第二層間介電質40上的鍵結能（bonding energy），其中所述第一層間介電質38和第二層間介電質40也可具有矽元素。因此，透過利用包括矽的介電材料之焊接層50，可以獲得良好的界面黏附性和整合性。
此外，由於此處選擇的焊接層50為介電材料，所以將焊接層50圖案化以暴露出下方的源/汲極區域36。因此，稍後形成於暴露出的源/汲極區域36上的第一障壁層52可與源/汲極區域36接觸。結果，在隨後的退火製程期間，可透過第一障壁層52和源/汲極區域36之間的化學反應使源/汲極區域36轉換為矽化物材料。
在一些實施例中，第5圖中所形成的焊接層50是氮化矽材料，其厚度介於約0.5 nm至約10 nm的範圍內。
第一障壁層52可為或可包括含金屬的材料，例如鈦、鈷、鎳、其類似材料、或前述之組合，且可透過原子層沉積（ALD）、化學氣相沈積（CVD）、或另一種沉積技術來沉積所述第一障壁層52。第一障壁層52可為或可包括氮化鈦、氧化鈦、氮化鉭、氧化鉭、其類似材料、或前述之組合，且可透過原子層沉積（ALD）、化學氣相沈積（CVD）、或另一種沉積技術來沉積所述第一障壁層52。
於操作110，可進行退火製程以促進源/汲極區域36與第一障壁層52的反應以在源/汲極區域36上形成矽化物區域55，所述矽化物區域55例如為具有與半導體材料（例如，Si及/或Ge）反應之含金屬材料的矽化物區域，如第7圖所示。在一些示例中，當第一障壁層52為一層鈦層或氮化鈦層時，矽化物區域55為矽化鈦材料。雖然第7圖僅顯示出形成於源/汲極區域36上的矽化物區域55，但應注意的是，矽化物區域55可形成於其他位置/地方，像是閘極堆疊32上方或基板30上其他所需的位置。
於操作112，在形成矽化物區域55之後，可將形成於基板30上的第一障壁層52移除，如第8圖所示。可透過合適的蝕刻技術將第一障壁層52從基板30移除，所述蝕刻技術像是反應性離子蝕刻（RIE）、中性粒子束蝕刻（NBE）、濕式蝕刻、或另一種蝕刻製程。在一些示例中，焊接層50留在基板30上以作為界面保護。
於操作114，在焊接層50、暴露的矽化物區域55、暴露的第二層間介電質40、和基板30的其他暴露區域上形成第二障壁層58，如第9圖所示。第二障壁層58可類似於共形沉積在焊接層50和基板30上的第一障壁層52。第二障壁層58可為或可包括氮化鈦、氧化鈦、氮化鉭、氧化鉭、其類似材料、或前述之組合，且可透過原子層沉積（ALD）、化學氣相沈積（CVD）、或另一種沉積技術來沈積第二障壁層58。在一些示例中，第二障壁層58的厚度介於約5 nm至約80 nm的範圍內。
在一示例中，第二障壁層58選自與焊接層50具有類似元素的材料，使得焊接層50和第二障壁層58之間的界面黏附性（interface adhesion）得以增強。舉例而言，當焊接層50包含矽元素和其他元素（例如氮、氧、及/或碳元素）時，矽元素可具有用以結合在第一層間介電質38和第二層間介電質40上的鍵結能，其中所述第一層間介電質38和第二層間介電質40也可具有矽元素。同時，來自焊接層50的其他元素（例如，氮、氧、及/或碳元素）結合至第二障壁層58，第二障壁層58的材料選擇為至少具有氮、氧、或碳元素。因此，良好地選擇焊接層50和第二障壁層58的材料可以增強界面整合和它們之間的黏附性，從而改善整個裝置結構的完整性和性能。因此，透過使用包含矽的介電材料作為焊接層50的材料，且焊接層50的材料也使用包含類似於第二障壁層58內之元素的其他元素，可以獲得良好的界面黏附性和整合性。
於操作116，進行回拉（pull-back）製程以從基板30移除第二障壁層58的一部分和焊接層50的一部分，如第10圖所示。回拉製程是一種包含乾式蝕刻製程或濕式蝕刻製程的蝕刻製程。
在一些實施例中，此處所述用以蝕刻第二障壁層58的回拉製程是濕式蝕刻製程，將靠近開口42、44、和46的角落之第二障壁層58的上部分從基板30移除。回拉過程包含移除第二障壁層58至第二層間介電質40的頂表面67下方的深度88，這移除了可能累積在開口42、44、和46的角落59之多餘的第二障壁層。第二障壁層58的頂表面位於第二層間介電質40的頂表面67下方和焊接層50的頂表面下方。透過移除位於開口42、44、和46較高區域（例如，角落59）之第二障壁層58的上部分，相較於在焊接層50之位置的較短寬度81以及在第二障壁層58之位置的更短寬度82，不將焊接層50和第二障壁層58包含在內的開口42、44、46具有較寬的寬度80。應注意的是，焊接層50的一部分也在回拉製程期間被移除，這有助於為了後續的製程而加寬開口42、44、46的寬度80。開口42、44、46的較寬寬度80和寬度81可為後續形成於其中的導電金屬填充層提供更寬的製程容許範圍(process window)，而且空隙或接縫（seams）形成於其中的可能性較小。在一些示例中，較短寬度81小於較寬寬度80的量介於較寬寬度80之約5%至約15%的範圍內，且更短寬度82小於較寬寬度80的量介於較寬寬度80之約8%至約30%的範圍內。
在一些示例中，回拉製程是濕式蝕刻製程。濕式蝕刻製程可包含將基板30浸入包括去離子（deionized，DI）水和合適化學物質的溶液中。前述之溶液和第二障壁層58之間的化學反應顯著地蝕刻第二障壁層58和一部分的焊接層50，直到達到預定的製程時間段或是在開口42、44、46中達到期望的深度88為止，如第10圖所示。包含在去離子水中的化學物質之合適示例包含：過氧化氫（H2 O2 ）、氫氧化銨（NH4 OH）、HNO3 、H2 SO4 、HCl、稀釋HF、及其類似物質。在一些示例中，去離子水中用於蝕刻第二障壁層58的化學物質包含H2 O2 。據信去離子水中的H2 O2 可與第二障壁層58中的Ti/Ta元素進行反應，從而將第二障壁層58的一部分從基板30移除。
去離子水中的化學物質之濃度可介於0.1%至50%。在浸沒（immersion）期間，溶液的溫度可介於約20℃至約90℃的範圍內。可將基板30持續浸在溶液中約5秒至約120秒以形成1 nm至50 nm範圍內的深度。在將基板30浸沒於溶液中之後，可選擇性地（optionally）在異丙醇（isopropyl alcohol，IPA）中潤洗半導體基板30以乾燥基板30。
在一些示例中，回蝕刻（例如，回拉）第二障壁層58以暴露出開口42、44、46中焊接層50的頂部54。焊接層50被第二障壁層58暴露出來的頂部54之深度60介於約15 nm至約25 nm之間。如上述討論的，形成於開口42、44、46的角落59處之多餘的第二障壁層58可能潛在地增加開口42、44、46在後續沉積製程中早期閉合（early closure）之可能性。然而，第二障壁層58可使後續填充在其中之金屬導電填充材料66的金屬材料成核及生長。因此，可調節所形成之第二障壁層58的厚度，以在隨後的金屬導電填充材料66得以生長並防止開口42、44、46的阻塞之間取得平衡。因此，透過回拉第二障壁層58以暴露下方焊接層50的一部分，可將形成於角落59處的第二障壁層58移除，並且也可加寬開口42、44、46的頂部，這有助於填充金屬導電填充材料66於其中而不產生早期閉合以防止產生空隙。當仍有一些第二障壁層58保留在開口42、44、46中時，成核位置和黏附表面也被保留下來並可允許金屬元素在隨後的沉積過程中黏附於其上。在一些示例中，第二障壁層58暴露出焊接層50的深度60，如第10圖所示。在一些示例中，深度60介於約15 nm至約25 nm的範圍內。
在使用乾式蝕刻製程於回拉製程的示例中，乾式蝕刻製程可包含反應性離子蝕刻（RIE）、中性粒子束蝕刻（NBE）、感應耦合電漿（inductively coupled plasma，ICP）蝕刻、其類似製程、或前述之組合。可用於電漿蝕刻製程的示例蝕刻劑氣體包括含鹵素的氣體或另一種蝕刻劑氣體。電漿蝕刻製程的蝕刻劑氣體流速可介於約10 sccm至約100 sccm的範圍內。電漿蝕刻製程可實現約10 kV至約500 kV的直流（DC）基板偏壓。電漿蝕刻製程的功率可介於約200 W至約2000 W的範圍內。電漿蝕刻製程的壓力可介於約5 mTorr至約50 mTorr的範圍內。透過用於回拉之蝕刻過程的持續時間可控制回拉的深度88。在一些示例中，電漿蝕刻製程的持續時間可介於約10秒至約600秒的範圍內以實現介於約15 nm至約35 nm範圍內的深度88。
於操作118，形成金屬導電填充材料66於開口42、44、和46中以及第二障壁層58上和焊接層50的頂部54上，如第11圖所示。金屬導電填充材料66可為或可包括金屬，像是鈷、鎢、銅、鋁、金、銀、前述之合金、其類似材料、或前述之組合，且可透過化學氣相沈積（CVD）、原子層沉積（ALD）、物理氣相沈積（PVD）、或另一種沈積技術來沉積金屬導電填充材料66。第二障壁層58的回拉可允許開口42、44、和46在上部分處或者比起開口42、44、和46中具有較短寬度82的下部分具有較大的尺寸（例如，寬度80、81）。因此，在開口42、44、46上部分處的較大尺寸可在開口42、44、和46中的金屬導電填充材料66內沒有空隙形成的情況下，允許金屬導電填充材料66填充開口42、44、和46。
在一些示例中，可將多餘的金屬導電填充材料66移除，如第12圖所示。在沉積金屬導電填充材料66之後，舉例而言，可透過使用像是化學機械研磨（CMP）的平坦化製程來移除第二層間介電質40的頂表面67之上多餘的金屬導電填充材料66。平坦化製程可將多餘的金屬導電填充材料66從第二層間介電質40的頂表面67上方移除。這在開口42、44、和46中分別形成包括金屬導電填充材料66的導電部件70、72、74。導電部件70、72、74和第二層間介電質40的頂表面可為共平面的。因此，可將包含金屬導電填充材料66、第二障壁層58、和焊接層50（以及可能的矽化物區域55）的導電部件70、72、74形成至對應的閘極堆疊32及/或源/汲極區域36。從第12圖可以明顯看出，透過回拉第二障壁層58和焊接層50，可以增加金屬導電填充材料66在導電部件70、72、和74之頂表面處的寬度，這可以增加各個後續導電部件可接觸的表面積。
如前所述，一些實施例的觀點或層面可應用於產線前段（FEOL）和產線中段（MEOL）的製程中。導電部件70、72、和74，包含形成導電部件70、72、和74的製程，可以實現產線前段（FEOL）及/或產線中段（MEOL）中各實施例的各個觀點或層面。在產線前段及/或產線中段製程中形成的其他導電部件可類似地合併一些實施例的觀點或層面。舉例而言，可根據一些實施例形成替代閘極堆疊。對於替代閘極堆疊，舉例而言，可根據上述顯示之相同或類似的製程，沉積並回拉形成於虛設閘極堆疊被移除處的共形層，像是介電層及/或功函數調整層。在其他示例中，前述之各個觀點或層面可併入產線後端（BEOL）製程中形成於金屬間介電質（intermetallization dielectrics，IMDs）內的導電部件中。
一些實施例可以達到優勢。透過移除位於開口或凹陷上部分處的一部分障壁層，可更容易地在不於開口或凹陷內形成空隙的前提下，在開口或凹陷中沈積將形成導電部件的導電材料。特別是當導電部件的尺寸很小時，導電部件中的空隙會導致導電部件具有較高的電阻或導致導電部件完全失效，像是不能建立電性接觸。因此，減少空隙的形成係具有優勢的，特別是在小的技術節點中，例如具有小尺寸的先進技術。此外，可基於不同的製程控制和裝置性能需求來調整導電部件中焊接層和障壁層的高度。
在一實施例中，提供一種半導體結構的形成方法，包含：沿著介電層中的開口之側壁形成介電焊接層、於所述介電焊接層上形成障壁層、回蝕刻所述障壁層的一部分以暴露出介電焊接層的上部分之側表面、以及於所述介電焊接層的上部分之側表面上和障壁層上形成導電材料。在一實施例中，利用包括H2 O2 、H2 SO4 、HNO3 、NH4 OH、或前述之組合的至少一種的溶液濕式蝕刻所述障壁層。在一實施例中，導電材料的一部分與介電焊接層的上部分之側表面直接接觸。在一實施例中，障壁層包括氮化鈦、氧化鈦、氮化鉭、和氧化鉭的至少一種。在一實施例中，介電焊接層為含矽的介電材料。在一實施例中，介電焊接層包括氧化矽、氮化矽、碳化矽、碳氧化矽、和氮氧化矽的至少一種。在一實施例中，由回蝕刻障壁層的所述部分所暴露出來之介電焊接層的上部分之側表面，其被暴露出的深度在約15 nm至約25 nm的範圍內。在一實施例中，障壁層的頂表面低於在介電層的開口的側壁上之介電焊接層的頂表面。
在另一實施例中，提供一種半導體結構，包含：具有側壁的介電層，所述介電層位於基板之上；沿著所述側壁的介電焊接層，所述介電焊接層暴露出側壁的上部分；沿著所述介電焊接層的障壁層，所述障壁層暴露出介電焊接層的上部分；以及沿著所述障壁層、所述側壁的所述上部分和所述介電焊接層的所述上部分之導電材料。在一實施例中，導電材料與介電焊接層接觸的頂部寬度大於與障壁層接觸的底部寬度。在一實施例中，導電材料與介電焊接層的上部分直接接觸。在一實施例中，在介電焊接層和障壁層各自的頂表面之間定義一深度，其中所述深度介於約15 nm至約25 nm。在一實施例中，障壁層的頂表面位於介電焊接層的頂表面下方。在一實施例中，導電材料包括鈷、鎢、銅、鋁、金、和銀的至少一種。在一實施例中，矽化區域沿著導電材料之下的障壁層之底部形成。在一實施例中，介電焊接層為含矽的介電材料。在一實施例中，介電焊接層包含氧化矽、氮化矽、碳化矽、碳氧化矽、和氮氧化矽的至少一種。在一實施例中，障壁層包含氮化鈦、氧化鈦、氮化鉭、和氧化鉭的至少一種。
又在另一實施例中，提供一種半導體結構，包含：介電層；導電材料，形成於所述介電層中並由障壁層側向地連接；以及介電焊接層，側向地位於所述障壁層和所述介電層之間，其中所述障壁層和所述介電焊接層沿著所述介電層的側壁具有不一致的高度。在一實施例中，所述不一致的高度定義介於約15 nm至25 nm範圍內的一階梯高度。
前述內文概述了許多實施例的部件，以使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的精神與範圍。在不背離本發明的精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
30:基板 32:閘極堆疊 34:閘極間隔物 36:源/汲極區域 38、40:層間介電質 42、44、46:開口 50:焊接層 52:第一障壁層 54:頂部 55:矽化物區域 58:第二障壁層 59:角落 60、88:深度 66:金屬導電填充材料 67:頂表面 70、72、74:導電部件 80、81、82:寬度 100:製程 106、108、110、112、114、116、118:操作
本發明實施例可配合以下圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準慣例，各個部件（feature）並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個部件的尺寸。 第1圖根據一些實施例顯示形成導電部件之示例方法的流程圖。 第2~12圖根據一些實施例顯示在形成導電部件的示例方法期間各個中間結構的剖面圖。
無。
30:基板
32:閘極堆疊
34:閘極間隔物
36:源/汲極區域
38、40:層間介電質
42、44、46:開口
50:焊接層
55:矽化物區域
58:第二障壁層
66:金屬導電填充材料
67:頂表面
70、72、74:導電部件
80、81:寬度

Claims (13)

  1. 一種半導體結構的形成方法，包括：沿著一介電層中的一開口之一側壁形成一介電焊接層；於該介電焊接層上形成一障壁層；回蝕刻該障壁層的一部分以暴露出該介電焊接層的一上部分之一側表面；以及於該介電焊接層的該上部分之該側表面上和該障壁層上形成一導電材料。
  2. 如申請專利範圍第1項所述之半導體結構的形成方法，其中回蝕刻該障壁層的該部分包括：利用一溶液對該障壁層進行濕式蝕刻，該溶液包括H2O2、H2SO4、HNO3、NH4OH、或前述之組合的至少一種。
  3. 如申請專利範圍第1或2項所述之半導體結構的形成方法，其中該導電材料的一部分與該介電焊接層的該上部分之該側表面直接接觸。
  4. 如申請專利範圍第1或2項所述之半導體結構的形成方法，其中該障壁層的頂表面低於在該介電層的該開口的該側壁上之該介電焊接層的頂表面。
  5. 一種半導體結構，包括：一介電層，具有一側壁，該介電層位於一基板之上；一介電焊接層，沿著該側壁，該介電焊接層暴露出該側壁的一上部分；一障壁層，沿著該介電焊接層，該障壁層暴露出該介電焊接層的一上部分其中該障壁層的一頂表面位於該介電焊接層的一頂表面下方；以及一導電材料，沿著該障壁層、該側壁的該上部分和該介電焊接層的該上部分。
  6. 如申請專利範圍第5項所述之半導體結構，其中該導電材料與該 介電焊接層接觸的一頂部寬度大於與該障壁層接觸的一底部寬度。
  7. 如申請專利範圍第5或6項所述之半導體結構，其中該導電材料與該介電焊接層的該上部分直接接觸。
  8. 如申請專利範圍第5或6項所述之半導體結構，更包括：一矽化區域，沿著該導電材料之下的該障壁層之一底部。
  9. 如申請專利範圍第5或6項所述之半導體結構，其中該介電焊接層為含矽的介電材料。
  10. 如申請專利範圍第9項所述之半導體結構，其中該介電焊接層為氧化矽、氮化矽、碳化矽、碳氧化矽、氮氧化矽、或前述之多層。
  11. 如申請專利範圍第5或6項所述之半導體結構，其中該障壁層為氮化鈦、氧化鈦、氮化鉭、氧化鉭、或前述之組合。
  12. 一種半導體結構，包括：一介電層；一導電材料，形成於該介電層中並側向地以一障壁層為邊界；以及一介電焊接層，側向地位於該障壁層和該介電層之間，其中該障壁層和該介電焊接層沿著該介電層的一側壁具有不一致的高度，且該障壁層的一頂表面位於該介電焊接層的一頂表面下方。
  13. 如申請專利範圍第12項所述之半導體結構，其中該不一致的高度定義介於約15nm至約25nm範圍內的一階梯高度。
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