TWI721040B - 帶有具有化合物半導體裝置整合在封裝體組織上的高頻通訊模組之微電子裝置 - Google Patents
帶有具有化合物半導體裝置整合在封裝體組織上的高頻通訊模組之微電子裝置 Download PDFInfo
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Abstract
本發明之實施例包括一微電子裝置其包括使用以矽為主的基體形成的一第一晶粒及耦合至該第一晶粒的一第二晶粒。該第二晶粒係以化合物半導體材料於一不同基體(例如,化合物半導體基體、III-V族基體)形成。一天線單元係耦合至該第二晶粒。該天線單元於約4GHz或更高的一頻率發射及接收通訊。
Description
發明領域
本發明之實施例大致上係有關於半導體裝置之製造。更明確言之,本發明之實施例係有關於帶有具有化合物半導體裝置整合在封裝體組織上的高頻通訊模組之微電子裝置。
發明背景
未來的無線產品係鎖定目標於比較目前運用的較低GHz範圍遠更高的頻率操作。例如,5G(第五代行動網路或第五代無線系統)通訊係預期於大於或等於15GHz的頻率操作。再者,目前WiGig(無線十億位元聯盟)產品於約60GHz操作。包括汽車雷達及醫療成像的其它應用將無線通訊技術利用於毫米波頻率(例如,30GHz-300GHz)。
用於此等無線應用,設計RF(射頻)電路需要高品質匹配被動網路,以便因應預先界定的頻帶(於該處進行通訊)的發射以及需要高效功率放大器及低損耗功率組合器/開關。
依據本發明之一實施例,係特地提出一種微電子裝置,其包含:使用一以矽為主的基體所形成的一第一晶粒;被耦接至該第一晶粒的一第二晶粒,該第二晶粒係以化合物半導體材料於一不同基體中被形成;及被耦接至該第二晶粒的一天線單元,該天線單元用於約4GHz或更高的一頻率發射及接收通訊。
100、200、300:微電子裝置、封裝組織架構
110、210、310:CMOS電路、晶粒
112:厚度
120、130、220、230、322-324、331-333、430、432:電路、晶粒
121、131、223、226、327、328:通孔
122、132、151-153、224、225、251-253、450:傳導層
140、240、324、420-423:整合被動裝置(IPD)
150、250、350:天線單元
160、260、360:封裝件或基體
222:貫穿通孔
320、330、400:覆蓋成形組件
338:路由或重新分配層
440:級間匹配IPD
700:計算裝置
702:板
704:處理器
706:通訊晶片
710、711:DRAM
712:ROM
714:晶片組
715:功率放大器
716:圖形處理器
720:天線單元
722:觸控螢幕控制器
724:羅盤
726:全球定位系統(GPS)裝置
728:揚聲器
730:觸控螢幕顯示器
732:電池
740:感測裝置
750:相機
圖1例示依據一個實施例於一微電子裝置(例如,封裝組織架構)中共同整合不同組件。
圖2例示依據另一個實施例於一微電子裝置(例如,封裝組織架構)中共同整合不同組件。
圖3例示依據另一個實施例於一微電子裝置(例如,封裝組織架構)中共同整合不同組件。
圖4例示依據一個實施例於封裝組織架構的塑模中之一功能電路。
圖5例示依據一個實施例一計算裝置700。
較佳實施例之詳細說明
本文描述者為具有化合物半導體裝置整合至一封裝組織上之帶有高頻通訊模組的微電子裝置。於後文描述
中,具體實施例的各種面向將使用熟諳技藝人士將其工作本質傳遞給熟諳技藝的其它人士常用的術語描述。然而,熟諳技藝人士顯然易知本發明可只以所描述面向中之部分實施。為了解說目的,陳述特定數字、材料及組態以供徹底瞭解例示實施例。然而,熟諳技藝人士顯然易知,本發明之實施例可無特定細節而予實施。於其它情況下,眾所周知的特徵經刪除或簡化以免遮掩了例示實施例。
各種操作將描述為多個分開操作,轉而以最有助於瞭解本發明之實施例之方式描述,但描述順序不應解譯為暗示此等操作必然為順序相依性。更明確言之,此等操作無需以呈現的順序進行。用於高頻(例如,5G、WiGig)無線應用,設計的RF電路(例如,低雜訊放大器、混合器、功率放大器等)需要高品質被動匹配網路,以便因應於進行通訊的,以及需要高效率功率放大器及低損耗功率組合器/開關等的經預先界定的頻帶之發射。可利用於大於30GHz操作的CMOS技術,但帶有功率放大器的效率減低及帶有低品質被動元件,主要原因在於採用典型有損耗的矽基體故。如此不僅導致較低系統效能,同時也因產生過量熱而導致熱要求增加。於一個實例中,高熱散逸的原因在於下述事實,於相位陣列排列中必須利用多個功率放大器以達成期望的輸出功率及發射範圍。此點於5G系統上甚至更苛刻,原因在於細胞式網路(例如,4G、LTE、LTE-Adv)的典型發射範圍係比連接性(例如,WiFi、WiGig)要求的範圍大數倍故。
本設計利用非CMOS技術(例如,非矽基體)於通訊系統的關鍵部件(例如,GaAs、GaN、玻璃上被動元件等)。藉由最佳系統分區,可以另一項技術製造要求高效率及高品質因數的關鍵部件。此等部件可在裝置層級(例如,GaN/GaAs上電晶體)上或在電路層級(例如,III-V晶粒整合功率放大器、低雜訊放大器等)上。如於本發明之實施例中討論,完整通訊系統將以封裝組織方式形成。
本設計技術允許共同整合晶粒及/或裝置,其係以不同技術製造及/或製造於相同封裝件上的基體上以獲得效能提升及熱要求的鬆弛。本設計包括封裝件,其事包括用與其它無線系統通訊的天線。行動與無線通訊的先前及目前世代(例如,2G、3G、4G)沒有天線共同整合在封裝件上,原因在於此點並非面積有效故。
於一個實施例中,本設計為具有以非CMOS為基礎的收發器積木塊(諸如以III-V族為基礎的裝置或晶粒)的5G(第五代行動網路或第五代無線系統)架構,其係與低頻電路及整合被動裝置(IPD)共同整合於相同封裝件上用於提升效能與熱要求鬆弛。於本配置中,各個組件係直接組裝於封裝件內。封裝件可具有直接整合其上的天線。5G架構以高頻(例如,至少20GHz、至少28GHz、至少30GHz等)操作及也可具有1-10每秒十億位元(Gbps)連結至端點。於另一個實例中,本設計於低頻(例如,至少4GHz,約4GHz)操作。
於一個實施例中,此種5G架構的設計導致
成本降低,原因在於收發器組件之功能測試係與需將其初步組裝於封裝件上解耦。此外,包含RFIC有或無封裝件上天線的無線5G模組可經設計為分開模組及出售。本設計也藉利用整合被動裝置或晶粒(IPD)提供較高品質被動元件。功能塊諸如阻抗匹配電路、調諧濾波器、耦合器、功率組合器/除法器等可以IPD實施。IPD通常使用晶圓製造技術(例如,薄膜沈積、蝕刻、微影術製程)製造。
分區5G收發器有效地允許此種架構達成更高功率放大器效率(例如,使用III-V族技術),改良的被動元件(例如,利用IPD及更有效的功率組合器或開關),原因在於在非CMOS基體上製造被動元件之故。本架構使其有能力將全部此等不同的分開組件連同天線整合於封裝件上以產生完整5G收發器。此等組件可在裝置層級(例如,分開電晶體)上或在電路層級(例如,功率放大器、低雜訊放大器)上。
圖1例示依據一個實施例於一微電子裝置(例如,封裝組織架構)中共同整合不同組件。微電子裝置100(例如,封裝組織架構100)包括一晶粒110的互補金氧半導體(CMOS)電路(例如,以矽為主的基體形成的具有至少一個基頻單元及至少一個收發器單元之CMOS電路、CMOS晶粒),以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒120之電路或裝置(例如,個別電晶體、電晶體組群),以化合物半導體材料(例如,III-V族材料、
砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒130之電路或裝置(例如,個別電晶體、電晶體組群),IPD 140,及具有用於發射與接收高頻通訊的至少一個天線之天線單元150。額外組件諸如傳統表面黏貼被動元件也可被安裝至封裝件。此外,圖1之組件可被覆蓋成形(overmolded)及以一外部屏蔽所覆蓋。模塑材料可以是低損耗非傳導性介電材料,及屏蔽可由傳導材料形成。天線單元150包括傳導層151-153。於本實例中,通孔121及傳導層122耦合電路120至CMOS電路110用於此等組件間之電氣連結。通孔132及傳導層131耦合IPD 140及晶粒130至晶粒之CMOS電路110用於此等組件間之電氣連結。微電子裝置100包括具有多個介電層的基體160用於傳導層與組件間之絕緣。
於一個實施例中,CMOS晶粒110係覆晶於微電子裝置(例如,封裝組織架構)的一側上。於一個實例中,在微電子裝置的一側(例如,下表面)上的CMOS晶粒110具有約10-300微米(例如,約50微米)的厚度112,而形成於晶粒120及130中之高功率高效率III-V族功率放大器係位在微電子裝置(例如,封裝組織架構)的第二側(例如,上表面)上。於一個實例中,化合物半導體材料(例如,GaN、GaAs)具有比較矽材顯著更高的電子遷移率其允許更快速操作。化合物半導體材料也具有較寬的帶隙,比較矽材,其允許功率裝置於較高溫操作,及對功率裝置於室溫給予較低熱雜訊。化合物半導體材料也具有直接帶隙,
其比較矽的間接帶隙,提供了更有利的光電子性質。被動匹配網路需要的數個被動元件(例如,解耦電容器、電感器)係整合入IPD 140;或者被動功率組合器、濾波器、或分路器可被組裝於微電子裝置(例如,封裝組織架構)上。於一個實例中,天線單元150係位在微電子裝置(例如,封裝組織架構)上儘可能地接近晶粒120及130的功率放大器。取決於特定架構,該等組件可約略按比例繪製或可不必照比例繪製。於一個實例中,針對約30GHz的頻率,天線單元150具有約2.5毫米x2.5毫米的維度,而電路120及130具有約2.0毫米x2.0毫米的維度。
於另一個實施例中,該等裝置中之任一者可彼此耦合。舉例言之,IPD 140可耦合至晶粒110、120及130中之至少一者。
圖2例示依據另一個實施例於一微電子裝置(例如,封裝組織架構)中共同整合不同組件。微電子裝置200(例如,封裝組織架構100)包括CMOS電路210(例如,以矽為主的基體形成的具有至少一個基頻單元及至少一個收發器單元之CMOS電路、CMOS晶粒),以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)形成的晶粒220之電路或裝置,以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)形成的晶粒230之電路或裝置,IPD 240,及具有用於發射與接收高頻通訊的至少一個天線(例如,5G、WiGig、至少4GHz、
至少15GHz、至少25GHz、至少28GHz、至少30GHz)之天線單元250。天線單元250包括傳導層251-253。於本實例中,通孔226及傳導層224耦合晶粒220及IPD 240至晶粒210用於此等組件間之電氣連結。貫穿通孔222、通孔223、及傳導層224及225耦合天線單元250至IPD 240、晶粒220、晶粒240、及晶粒210用於此等組件間之電氣連結。微電子裝置200包括多個介電層260用於傳導層與組件間之絕緣。
圖2顯示於基於z方向在裝置200中埋設晶粒達成較低高度的裝置200的另一個潛在發展。於圖2中,晶粒220及230及IPD 240埋入裝置200內,且可作為CMOS電路210(例如,CMOS晶粒)與天線單元250間之介面。貫穿通孔可用於III-V晶粒(例如,晶粒220、電路230)直接垂直連結到天線單元250。自被動元件或開關形成的匹配網路也能最終整合於裝置200。
於一個實施例中,CMOS電路210係覆晶於微電子裝置(例如,封裝組織架構)的一側上。於一個實例中,晶粒210具有約10-300微米(例如,約50微米)的厚度212,而形成於晶粒220及230中之高功率高效率III-V族功率放大器埋設於微電子裝置200(例如,封裝組織架構),如圖2中例示。於一個實例中,晶粒220及230的電路或裝置埋設於裝置200的介電層260內部。被動匹配網路需要的被動元件整合於IPD 240中,或被動功率整合器或分路器可組裝於微電子裝置(例如,封裝組織架構)上。天線單元
250係位在微電子裝置(例如,封裝組織架構)上儘可能地接近晶粒220及230的功率放大器。取決於特定架構,該等組件可約略按比例繪製或可不必按比例繪製。
於另一個實施例中,該等裝置中之任一者可彼此耦合。舉例言之,IPD 140可耦合至晶粒210、220及230中之至少一者。
另一個整合技術係在附接到微電子裝置(例如,通訊模組)之前,初步將化合物半導體裝置或晶粒(例如,全部III-V裝置/晶粒)、分開SMT組件及IPD一起模塑於分開的覆蓋成形組件(或模組)。圖3例示依據一個實施例共同整合不同的組件包括覆蓋成形組件於微電子裝置(例如,封裝組織架構)。微電子裝置300(例如,封裝組織架構100)包括CMOS電路310(例如,以矽為主的基體形成的CMOS基頻及收發器電路、CMOS晶粒)及包含晶粒及/或裝置的覆蓋成形組件320。於一個實例中,覆蓋成形組件320包括以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒322之電路或裝置,以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒323之電路或裝置,及IPD 324。晶粒322-324係彼此耦合或耦合封裝件或基體360上的其它組件。第二覆蓋成形組件330包括以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒
331之電路或裝置,以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒333之電路或裝置,IPD 332、及用於將此等組件的晶粒330與其它組件、電路、或裝置的晶粒300耦合的路由或重新分配層338。晶粒331-333係彼此耦合,或使用路由或重新分配層338與其它組件耦合及也在封裝件或基體360上。具有至少一個天線之天線單元350發射與接收高頻通訊(例如,5G、WiGig、至少4GHz、至少15GHz、至少25GHz、至少28GHz、至少30GHz)。天線單元350包括傳導層351-353。於本實例中,通孔327及328及傳導層325及326耦合晶粒322及323及IPD 324至CMOS電路310用於此等組件間之電氣連結。天線單元350經由連結(未顯示於圖中)耦合至裝置300的電路及晶粒。微電子裝置300包括一基體360具有用於傳導層與裝置300的組件間絕緣的多個介電層。
圖3例示依據一個實施例,如圖4中顯示,可組合分開裝置以產生功能電路於塑模中的架構。覆蓋成形組件的電路可首先測試功能,及然後若電路有功能則組裝於微電子裝置或模組上。藉此方式,如果電路或裝置中之一者故障,覆蓋成形組件可達成成本降低。覆蓋成形組件的一體成型電路可使用將在裝置間進行路由的塑模上的路由或重新分配層實施,或路由可直接設計於微電子裝置(例如,封裝件)上。覆蓋成形組件400包括以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、
化合物半導體晶粒等)或有機材料形成的晶粒430之電路或裝置,以化合物半導體材料(例如,III-V族材料、砷化鎵(GaAs)、氮化鎵(GaN)、化合物半導體晶粒等)或有機材料形成的晶粒432之電路或裝置,IPD 420-423,及級間匹配IPD 440。組件400包括用於經由電氣連結耦合晶粒及IPD的一或多個傳導層450。於一個實例中,級間匹配IPD耦合至晶粒430及432。
於一個實施例中,帶有覆蓋成形晶粒及CMOS SoC的5G封裝組織架構係與天線單元組裝於相同雙面封裝件上。於圖3中,覆蓋成形組件320已經於封裝件上安排路徑,而組件330包括路由層(RDL)。模塑組件可以是獨立電路,其包括連同被動匹配網路製造在不同基體上的裝置層級組件用於匹配或解耦。該等裝置間之路由可以在封裝件上或在塑模上的路由層上。
一體成型電路減低成本,原因在於在組裝之前能夠與基體的其餘部分分開地測試一體成型電路。本設計產生可分開製造與出售的獨立5G模組。
須瞭解於單晶片系統實施例中,晶粒可包括處理器、記憶體、通訊電路等。雖然圖中例示單一晶粒,但在晶圓的相同區域可沒有、有一個或數個晶粒。
於一個實施例中,微電子裝置可以是使用塊狀矽或絕緣體上矽基體形成的結晶基體。於其它實施例中,微電子裝置可使用其它材料形成,其可以或可不組合矽,其包括但非僅限於鍺、銻化銦、碲化鉛、砷化銦、磷
化銦、砷化鎵、砷化銦鎵、銻化鎵、或III-V族或IV族材料的其它組合。雖然本文描述可形成基體的材料之數個實例,但可作為於其上建立半導體裝置的基礎的任何材料皆係落入於本發明之實施例的範圍內。
圖5例示依據本發明之一個實施例的一計算裝置700。計算裝置700罩住一板702。板702可包括多個組件,包括但非僅限於至少一個處理器704及至少一個通訊晶片706。至少一個處理器704係實體上及電氣上耦合至板702。於若干實施例中,至少一個通訊晶片706也實體上及電氣上耦合至板702。於進一步實施例中,通訊晶片706為處理器704的部分。於一個實例中,通訊晶片706(例如,微電子裝置100、200、300等)包括天線單元720(例如,天線單元150、250、350等)。
取決於其應用,計算裝置700可包括可以或可不實體式及電氣式耦合至板702的其它組件。此等其它組件包括,但非限制性,依電性記憶體(例如,DRAM 710、711)、非依電性記憶體(例如,ROM 712)、快閃記憶體、圖形處理器716、數位信號處理器、密碼處理器、晶片組714、天線單元720、顯示器、觸控螢幕顯示器730、觸控螢幕控制器722、電池732、音訊編解碼器、視訊編解碼器、功率放大器715、全球定位系統(GPS)裝置726、羅盤724、感測裝置740(例如,加速度計)、迴轉儀、揚聲器、相機750、及大容量儲存裝置(例如,硬碟驅動裝置、光碟(CD)、數位影音碟(DVD)及其類)。
通訊晶片706使得無線通訊能傳輸資料至及自計算裝置700。術語「無線」及其衍生詞可被使用來描述電路、裝置、系統、方法、技術、通訊通道等,其可透過非固體媒體經由調諧電磁輻射的使用而通訊資料。該術語並非暗示相關聯的裝置不含任何導線,但於若干實施例中其可能不含。通訊晶片706可實施多種無線標準或協定中之任一者,包括但非僅限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、WiGig、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生協定,以及標示為3G、4G、5G及其後的任何其它無線協定。計算裝置700可包括多個通訊晶片706。例如,第一通訊晶片706可專用於短程無線通訊諸如Wi-Fi、WiGig、及藍牙;及第二通訊晶片706可專用於長程無線通訊諸如GPS、EDGE、GPRS、CDM、WiMAX、LTE、Ev-DO、5G及其它。
計算裝置700的至少一個處理器704包括封裝於至少一個處理器704內部的積體電路晶粒。於本發明之實施例的若干具體實施中,處理器的積體電路晶粒包括一或多個裝置,諸如依據本發明之實施例的具體實施的微電子裝置(例如,微電子裝置100、200、300等)。術語「處理器」可指處理得自暫存器及/或記憶體的電子資料的任何裝置或裝置部分,用以將該電子資料變換成可儲存於暫存器及/或記憶體中的電子資料。
通訊晶片706也包括封裝於通訊晶片706內部的積體電路晶粒。依據本發明之實施例的另一個具體實施,通訊晶片的積體電路晶粒包括一或多個微電子裝置(例如,微電子裝置100、200、300等)。
下列實例係有關於進一步實施例。實例1為一種微電子裝置其包括使用一以矽為主的基體所形成的一第一晶粒,被耦接至該第一晶粒的一第二晶粒。該第二晶粒係以化合物半導體材料於一不同基體中被(例如,化合物半導體基體、III-V族基體)形成。一天線單元係耦接至該第二晶粒。該天線單元用於約4GHz或更高(例如,至少4GHz、至少15GHz、至少25GHz、至少30GHz等)的一頻率發射及接收通訊。
於實例2中,實例1之主旨可選擇性地包括被耦接到至少一個晶粒的一整合被動晶粒(IPD)。該IPD包括用於被動匹配網路的被動元件。
於實例3中,實例1-2中任一者之主旨可選擇性地包括該第一晶粒具有一互補金氧半導體(CMOS)基頻單元及收發器單元。該第一晶粒係覆晶於該微電子裝置的一第一側的一表面上。
於實例4中,實例1-3中任一者之主旨可選擇性地包括該第二晶粒包含被附接於該微電子裝置的一第二側的一表面上以III-V族材料所形成的功率放大器。該微電子裝置的該第一側係與該微電子裝置的該第二側相對。
於實例5中,實例1-4中任一者之主旨可選
擇性地包括該微電子裝置進一步具有被耦接到至少一個晶粒的一第三晶粒。該第三晶粒具有以化合物半導體材料於一不同基體(例如,化合物半導體基體、III-V族基體)所形成的裝置或電路。
於實例6中,實例1-5中任一者之主旨可選擇性地包括該微電子裝置具有用於5G通訊的一5G封裝架構。
於實例7中,一種通訊模組(或晶片)包含使用一以矽為主的基體所形成的一第一晶粒及被耦接至該第一晶粒的一第二晶粒。該第二晶粒係以化合物半導體材料於一不同基體中被形成,該基體係嵌入該通訊模組內部。一天線單元係耦接至該等第一及第二晶粒中之至少一者。該天線單元用於約15GHz或更高(例如,至少15GHz、至少25GHz、至少30GHz等)的一頻率發射及接收通訊。
於實例8中,實例7之主旨可選擇性地包括該通訊模組具有被耦接到至少一個晶粒的一整合被動晶粒(IPD)。該IPD係嵌入於該通訊模組內部。
於實例9中,實例7-8中任一者之主旨可選擇性地包括該第一晶粒具有一互補金氧半導體(CMOS)基頻及收發器電路。該第一晶粒係覆晶於該通訊模組的一第一側上。該第二晶粒包含被嵌入於該通訊模組內部以III-V族材料所形成的功率放大器。
於實例10中,實例7-9中任一者之主旨可選擇性地包括被耦接到至少一個晶粒的一第三晶粒。該第
三晶粒具有以化合物半導體材料所形成的裝置或電路。該第三晶粒係嵌入於該通訊模組內部。
於實例11中,實例7-10中任一者之主旨可選擇性地包括該通訊模組包含用於5G通訊的一5G封裝架構。
於實例12中,一種計算裝置包括至少一個處理器用以處理資料及被耦接至該至少一個處理器的一通訊模組或晶片。該通訊模組或晶片包含使用一以矽為主的基體所形成的一第一晶粒及具有被耦接至該第一晶粒的一第二晶粒的一第一覆蓋成形組件。該第二晶粒具有使用化合物半導體材料於一不同基體中所形成的裝置或電路。該通訊模組或晶片也包括被耦接至該第二晶粒的一天線單元。該天線單元用於約15GHz或更高(例如,至少15GHz、至少25GHz、至少30GHz等)的一頻率發射及接收通訊。
於實例13中,實例12之主旨可選擇性地包括該第一覆蓋成形組件具有被耦接到至少一個晶粒的一整合被動晶粒(IPD)。該IPD包括用於被動匹配網路的被動元件。
於實例14中,實例12-13中任一者之主旨可選擇性地包括該第一晶粒具有一互補金氧半導體(CMOS)基頻及收發器電路。該第一晶粒係覆晶於該通訊模組或晶片的一第一側上。
於實例15中,實例12-14中任一者之主旨
可選擇性地包括該第二電路具有以III-V族材料所形成的功率放大器。
於實例16中,實例12-15中任一者之主旨可選擇性地包括該第一覆蓋成形組件係附接於該通訊模組或晶片的一第二側的一表面上。
於實例17中,實例12-16中任一者之主旨可選擇性地包括該第一覆蓋成形組件具有被耦接到至少一個晶粒的一第三晶粒。該第三晶粒具有以化合物半導體材料所形成的裝置。
於實例18中,實例12-17中任一者之主旨可選擇性地包括該第二覆蓋成形組件具有被耦接到至少一個晶粒的一第四晶粒。該第四晶粒具有以化合物半導體材料於一基體中所形成的裝置或電路。
於實例19中,實例12-18中任一者之主旨可選擇性地包括該通訊模組或晶片其為用於5G通訊的一5G封裝架構。
於實例20中,實例12-19中任一者之主旨可選擇性地包括該計算裝置進一步包含括一記憶體,一顯示模組,及一輸入模組。該記憶體、顯示模組及輸入模組係在一晶片晶片組平台上及係彼此呈操作通訊。
100:微電子裝置、封裝組織架構
110:CMOS電路或晶粒
112:厚度
120、130:電路或晶粒
121、132:通孔
122、131、151-153:傳導層
140:IPD
150:天線單元
160:基體
Claims (19)
- 一種微電子裝置,其包含:使用一以矽為主的基體所形成的一第一晶粒,其形成於該微電子裝置之一第一側之一表面上;複數個外部連接,其在該微電子裝置之該第一側之該表面上,其中該第一晶粒係側向相鄰於該等複數個外部連接;被耦接至該第一晶粒的一第二晶粒,該第二晶粒係以化合物半導體材料於一不同基體中被形成;及被耦接至該第二晶粒的一天線單元,該天線單元用於約4GHz或更高的一頻率發射及接收通訊。
- 如請求項1之微電子裝置,其進一步包含:被耦接到該第一及該第二晶粒之至少一個晶粒的一整合被動晶粒(IPD),該IPD包括用於被動匹配網路的被動裝置。
- 如請求項2之微電子裝置,其中該第一晶粒包含一互補金氧半導體(CMOS)基頻單元及收發器單元其被覆晶於該微電子裝置的該第一側的該表面上。
- 如請求項3之微電子裝置,其中該第二晶粒包含被附接於該微電子裝置的一第二側的一表面上以III-V族材料所形成的功率放大器。
- 如請求項4之微電子裝置,其中該微電子裝置的該第一側係與該微電子裝置的該第二側相對。
- 如請求項1之微電子裝置,其進一步包含: 被耦接到該第一及該第二晶粒之至少一個晶粒的一第三晶粒,該第三晶粒具有以化合物半導體材料所形成的裝置或電路。
- 如請求項1之微電子裝置,其中該微電子裝置包含用於5G通訊的一5G封裝架構。
- 一種通訊模組,其包含:使用一以矽為主的基體所形成的一第一晶粒,其形成於該通訊模組之一第一側之一表面上;複數個外部連接,其在該通訊模組之該第一側之該表面上,其中該第一晶粒係側向相鄰於該等複數個外部連接;被耦接至該第一晶粒的一第二晶粒,該第二晶粒係以化合物半導體材料於一不同基體中被形成,其係嵌入該通訊模組內部;及被耦接至該等第一及第二晶粒中之至少一者的一天線單元,該天線單元用於約15GHz或更高的一頻率發射及接收通訊。
- 如請求項8之通訊模組,其進一步包含:被耦接到至少一個晶粒的一整合被動晶粒(IPD),該IPD係嵌入於該通訊模組內部。
- 如請求項9之通訊模組,其中該第一晶粒包含一互補金氧半導體(CMOS)基頻及收發器電路,其被覆晶於該通訊模組的該第一側上。
- 如請求項10之通訊模組,其中該第二晶粒包含被嵌入於該通訊模組內部以III-V族材料所形成的功 率放大器、低雜訊放大器、開關及其它電路中之至少一者。
- 如請求項8之通訊模組,其進一步包含:被耦接到該第一及該第二晶粒之至少一個晶粒的一第三晶粒,該第三晶粒具有以化合物半導體材料所形成的裝置或電路。
- 如請求項12之通訊模組,其中該第三晶粒係嵌入於該通訊模組內部。
- 如請求項8之通訊模組,其中該通訊模組包含用於5G通訊的一5G封裝架構。
- 一種微電子裝置,其包含:一第一晶粒,其係以一矽為主的基體所形成,其中該第一晶粒包含一互補金氧半導體(CMOS)基頻單元及收發器單元,其被覆晶於該微電子裝置之一第一側之一第一表面上;一第二晶粒,其耦接至該第一晶粒,該第二晶粒係以化合物半導體材料於一不同基體中被形成;一天線單元,其耦接至該第二晶粒,該天線單元用於約4GHz或更高的一頻率發射及接收通訊;以及一整合被動晶粒(IPD),其耦接至該第一及該第二晶粒之至少一晶粒,該IPD包括用於被動匹配網路的被動裝置。
- 如請求項15之微電子裝置,其中該第二晶粒包含被附接於該微電子裝置的一第二側的一表面上以III-V族材料所形成的功率放大器。
- 如請求項16之微電子裝置,其中該微電子裝置的該第一側係與該微電子裝置的該第二側相對。
- 一種通訊模組,其包含:一第一晶粒,其係以一矽為主的基體所形成,其中該第一晶粒包含一互補金氧半導體(CMOS)基頻及收發器電路,其被覆晶於該通訊模組之一第一側之第一表面上;一第二晶粒,其耦接至該第一晶粒,該第二晶粒係以化合物半導體材料於一不同基體之中所形成,其係嵌入該通訊模組內部;一天線單元,其耦接至該第一及該第二晶粒之至少一者,該天線單元用於在約15GHz或更高的一頻率發射及接收通訊;以及一整合被動晶粒(IPD),其耦接至至少一晶粒,該IPD被嵌入於該通訊模組中。
- 如請求項18之通訊模組,其中該第二晶粒包含被嵌入於該通訊模組內部以III-V族材料所形成的功率放大器、低雜訊放大器、開關及其他電路之至少一者。
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Also Published As
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CN108292650A (zh) | 2018-07-17 |
US10629551B2 (en) | 2020-04-21 |
US20180342472A1 (en) | 2018-11-29 |
TW201733042A (zh) | 2017-09-16 |
US20200227366A1 (en) | 2020-07-16 |
WO2017111975A1 (en) | 2017-06-29 |
US11387200B2 (en) | 2022-07-12 |
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