TWI710220B - 使用硬選取硬解碼模式下的解碼器產生軟資訊的方法 - Google Patents
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Abstract
一種用於解碼架構切換情境下減少位元翻轉演算法進行解碼的迭代次數的方法,其中當自一第一解碼架構切換至一第二解碼架構時,該方法執行以下步驟:產生一查找表,其中該查找表用以將失敗校驗節點的數量與對數相似比值進行對照;使用操作於該第一解碼架構下的一解碼器來針對操作於另一解碼架構下的另一解碼器產生軟資訊;於該解碼器的第一次迭代中,輸入失敗校驗節點的一數量至該查找表以產生一對數相似比值;以及將該對數相似比值輸出至該另一解碼器。
Description
本發明係關於一種用於低密度奇偶校驗(low-density parity check,LDPC)解碼器的位元翻轉演算法,尤指透過在解碼器進行硬選取硬解碼期間提供軟資訊給另一解碼器,以降低位元翻轉演算法的迭代次數的方法。
低密度奇偶校驗解碼器係使用具有奇偶位元(parity bit)的線性錯誤校正碼來進行解碼,其中奇偶位元會提供用以驗證接收到的碼字(codeword)的奇偶方程式給解碼器。舉例來說,低密度奇偶校驗可為一具有固定長度的二進位碼,其中所有的符元(symbol)相加會等於零。
在編碼過程中,所有的資料位元會被重複執行並且被傳送至對應的編碼器,其中每個編碼器會產生一奇偶符元(parity symbol)。碼字係由k個訊息位元(information digit)以及r個校驗位元(check digit)所組成。如果碼字總共有n位元,則k=n-r。上述碼字可用一奇偶校驗矩陣來表示,其中該奇偶校驗矩陣具有r列(表示方程式的數量)以及n行(表示位元數),如第1圖所示。這些碼之所以被稱為「低密度」是因為相較於奇偶校驗矩陣中位元0的數量而言,位元1的數量相對的少。在解碼過程中,每次的奇偶校驗皆可視為一奇偶校驗碼,並
隨後與其他奇偶校驗碼一起進行交互校驗(cross-check),其中解碼會在校驗節點(check node)進行,而交互校驗會在變數節點(variable node)進行。
LDPC解碼器支持三種模式:硬判定硬解碼(硬選取hard decoding)、軟判定硬解碼(soft decision hard decoding),以及軟判定軟解碼(soft decision hard decoding)。第1圖係為奇偶校驗矩陣H(第1圖的上半部份)以及Tanner Graph(第1圖的下半部份)的示意圖,其中Tanner Graph係為另一種表示碼字的方式,並且可用於解釋當使用一位元翻轉(bit flipping)演算法時,LDPC解碼器的一些關於硬判定軟解碼的操作。
在Tunner Graph中,方形(C1~C4)所表示的校驗節點(check node)代表奇偶位元(parity bit)的數量,且圓形(V1~V7)所表示的變數節點(variable node)係為一碼字中位元的數量。如果一特定方程式與碼符元(code symbol)有關,則對應的校驗節點與變數節點之間會以連線來表示。被估測的消息會沿著這些連線來傳遞,並且於節點上以不同的方式組合。一開始時,變數節點將發送一估測至所有連線上的校驗節點,其中這些連線包含被認為是正確的位元。接著,每個校驗節點會依據對所有其他的連接的估測(connected estimate)來針對每一變數節點進行新的估測,並且將新的估測傳回至變數節點。新的估測係基於:奇偶校驗方程式迫使所有的變數節點連接至一特定校驗節點,以使總和為零。
這些變數節點會接收新的資訊以及使用一多數規則(majority rule)(亦即硬判定),來判斷所傳送的原始位元之值是否正確,若不正確,該原始位元會被翻轉(flipped)。該位元接著會被傳回至該些校驗節點,且上述步驟會被
迭代地執行一預定次數,直到符合這些校驗節點的奇偶校驗方程式。若有符合這些奇偶校驗方程式(亦即校驗節點所計算之值符合接收自變數節點之值),則可啟用提前終止(early termination),這會使得系統在最大迭代次數達到之前就結束解碼程序。
若目前使用的解碼模式無法在達到最大迭代次數之前就完成解碼,則需要切換為另一種解碼模式。基於硬選取硬解碼是最省電的一種模式,切換順序通常是:硬選取硬解碼→硬選取軟解碼→軟選取軟解碼,其中後兩個模式需要一些基於置信度傳播演算法而建立的軟資訊。節點所接收到的每一則訊息(message)皆為一條件機率(conditional probability),即接收到的位元係為0或1。在運行LDPC解碼器之前就已事先得知的機率稱為後驗機率(a posteriori probability,APP),其可藉由對該解碼器進行一定次數的迭代來得知。因此,當從一硬選取硬解碼架構切換至一硬選取軟解碼架構時,該LDPC解碼器必須先執行一定次數的迭代來取得所需的後驗機率。
本發明的一目的在於,當自一第一解碼架構切換至一第二解碼架構時,使用一位元翻轉演算法來減少迭代的次數。
本發明的一實施例揭示一種用於解碼架構切換情境下減少位元翻轉(bit flipping)演算法進行解碼的迭代次數的方法,其中當自一第一解碼架構切換至一第二解碼架構時,該方法執行以下步驟:產生一查找表,其中該查找表用以將失敗校驗節點(failed check node)的數量與對數相似比值(log-likelihood ratio,LLR)進行對照;使用操作於該第一解碼架構下的一解碼器來針對操作於
一該第二解碼架構下的另一解碼器產生軟資訊;於該解碼器的第一次迭代中,輸入失敗校驗節點的一數量至該查找表以產生一對數相似比值;以及將該對數相似比值輸出至該另一解碼器。
H:奇偶校驗矩陣
C1~C4:校驗節點
V1~V7:變數節點
第1圖係為根據先前技術的用於進行低密度奇偶校驗解碼的一奇偶校驗矩陣以及Tanner Graph的示意圖。
如以上相關技術所示,軟資訊用以表示變數節點的碼字的可信賴程度。舉例來說,軟資訊可為一對數相似比值(log-likelihood ratio,LLR),其被硬選取軟解碼以及軟選取軟解碼中的變數節點所使用。對數相似比值係由後驗機率來決定,並且關聯於有多少個校驗節點是失敗的(亦即變數節點的碼字的可信程度)以及系統中錯誤位元的數量。表1以及表2列舉了失敗校驗節點、錯誤位元以及對數相似比值之間的關係。
其中上述對數相似比值係依據以下方程式計算:LLR_i=Max LLR * ((column_weight+1-i)/column_weight+1)
在上述方程式中,i代表失敗校驗節點的數量,LLR_i代表對應失
敗校驗節點數量i的對數相似比值,且Max LLR代表最大對數相似比值。透過使用表1以及表2,可據以產生一查找表(look-up table),其中所述查找表直接地將失敗校驗節點的數量鍊結(link)於該些對數相似比值,且所述查找表可如表3所示:
因此,即使當LDPC解碼器正操作於硬選取硬解碼模式,仍可藉由使用所述查找表來產生軟資訊。
在本發明的一實施例中,在硬選取硬解碼模式中使用一位元翻轉演算法的一第一解碼器會藉由決定失敗校驗節點的數量並且將此資訊輸入至所述查找表以輸出一對數相似比值,以於第一次迭代中產生多個對數相似比值。該第一解碼器接著會將該些對數相似比值傳給操作於硬選取軟解碼模式的一N2解碼器。
因此,在位元翻轉解碼器的第一次迭代中,資訊也將被提供給軟解碼以及硬解碼使用。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
H:奇偶校驗矩陣
C1~C4:校驗節點
V1~V7:變數節點
Claims (4)
- 一種用於解碼架構切換情境下減少位元翻轉(bit flipping)演算法進行解碼的迭代次數的方法,其中當自一第一解碼架構切換至一第二解碼架構時,該方法執行以下步驟:產生一查找表,其中該查找表用以將失敗校驗節點(failed check node)的數量與對數相似比值(log-likelihood ratio,LLR)進行對照,並且該查找表將該失敗校驗節點的數量鍊結(link)至該對數相似比值;使用操作於該第一解碼架構下的一解碼器來針對操作於一該第二解碼架構下的另一解碼器產生軟資訊;於該解碼器的第一次迭代中,輸入失敗校驗節點的一數量至該查找表以產生一對數相似比值;以及將該對數相似比值輸出至該另一解碼器。
- 如請求項1所述的方法,其中該第一解碼架構係採用一硬選取硬解碼(hard decision hard decoding)模式,且該第二解碼架構係採用一硬選取軟解碼(hard decision soft decoding)模式。
- 如請求項1所述的方法,其中該解碼器以及該另一解碼器皆使用一位元翻轉(bit flipping)演算法來進行解碼。
- 如請求項1所述的方法,其中該查找表係根據以下方程式來進行操作:LLR_i=Max LLR * ((column_weight+1-i)/column_weight+1)其中i代表失敗校驗節點的數量,LLR_i代表對應失敗校驗節點數量i的對數 相似比值,且Max LLR代表最大對數相似比值。
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10340951B2 (en) * | 2017-09-13 | 2019-07-02 | Toshiba Memory Corporation | Soft decision LDPC decoder with improved LLR from neighboring bits |
US10511326B2 (en) * | 2017-11-14 | 2019-12-17 | Nyquist Semiconductor Limited | Systems and methods for decoding error correcting codes |
US10491244B2 (en) * | 2017-11-14 | 2019-11-26 | Nyquist Semiconductor Limited | Systems and methods for decoding error correcting codes |
CN110275796B (zh) * | 2018-03-16 | 2023-08-08 | 爱思开海力士有限公司 | 具有混合解码方案的存储器系统及其操作方法 |
US10884858B2 (en) | 2018-03-16 | 2021-01-05 | SK Hynix Inc. | LDPC decoding device, memory system including the same and method thereof |
US11005503B2 (en) | 2018-03-16 | 2021-05-11 | SK Hynix Inc. | Memory system with hybrid decoding scheme and method of operating such memory system |
CN108650029B (zh) * | 2018-05-16 | 2020-07-31 | 清华大学 | 一种适用于量子安全直接通信的纠错编译码方法 |
CN108762977A (zh) * | 2018-05-30 | 2018-11-06 | 郑州云海信息技术有限公司 | 一种固态盘中纠错算法的优化方法及系统 |
US10715182B2 (en) * | 2018-07-27 | 2020-07-14 | Innogrit Technologies Co., Ltd. | Systems and methods for decoding error correcting codes with self-generated LLR |
US10872013B2 (en) | 2019-03-15 | 2020-12-22 | Toshiba Memory Corporation | Non volatile memory controller device and method for adjustment |
US11086716B2 (en) * | 2019-07-24 | 2021-08-10 | Microchip Technology Inc. | Memory controller and method for decoding memory devices with early hard-decode exit |
JP2021044750A (ja) * | 2019-09-12 | 2021-03-18 | キオクシア株式会社 | メモリシステム |
CN113131947B (zh) * | 2019-12-30 | 2023-11-10 | 华为技术有限公司 | 译码方法、译码器和译码装置 |
CN111541517B (zh) * | 2020-04-17 | 2022-03-25 | 北京交通大学 | 一种列表极化码传播译码方法 |
CN111865335B (zh) * | 2020-09-24 | 2021-01-22 | 浙江三维通信科技有限公司 | 一种分组纠错码的译码方法、装置、存储介质和电子装置 |
CN112422135B (zh) * | 2020-11-27 | 2024-04-16 | 中国计量大学 | 基于子矩阵校验的scan-bf提前翻转译码器 |
DE112022001547T5 (de) | 2021-06-01 | 2024-01-11 | Microchip Technology Inc. | Speicheradressenschutz |
CN117480732A (zh) | 2021-09-28 | 2024-01-30 | 微芯片技术股份有限公司 | 具有陷阱块管理的ldpc解码 |
US12107603B1 (en) * | 2021-10-26 | 2024-10-01 | Marvell Asia Pte Ltd | Adaptive read recovery for NAND flash memory devices |
US12052033B2 (en) | 2022-07-13 | 2024-07-30 | Apple Inc. | Scheduling of iterative decoding depending on soft inputs |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8051363B1 (en) * | 2007-01-16 | 2011-11-01 | Marvell International Ltd. | Absorb decode algorithm for 10GBase-T LDPC decoder |
US9021332B2 (en) * | 2012-12-11 | 2015-04-28 | Seagate Technology Llc | Flash memory read error recovery with soft-decision decode |
US20160027521A1 (en) * | 2014-07-22 | 2016-01-28 | NXGN Data, Inc. | Method of flash channel calibration with multiple luts for adaptive multiple-read |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7783952B2 (en) * | 2006-09-08 | 2010-08-24 | Motorola, Inc. | Method and apparatus for decoding data |
CN100517981C (zh) * | 2007-01-05 | 2009-07-22 | 东南大学 | 低密度奇偶校验码的并行加权比特翻转解码方法 |
US7978793B2 (en) * | 2008-02-06 | 2011-07-12 | Freescale Semiconductor, Inc. | Method for generating soft decision signal from hard decision signal in a receiver system |
JP5506828B2 (ja) * | 2009-03-05 | 2014-05-28 | エルエスアイ コーポレーション | 繰り返し復号器のための改良ターボ等化方法 |
US8429498B1 (en) * | 2009-03-25 | 2013-04-23 | Apple Inc. | Dual ECC decoder |
US8700970B2 (en) * | 2010-02-28 | 2014-04-15 | Densbits Technologies Ltd. | System and method for multi-dimensional decoding |
KR101751497B1 (ko) | 2010-06-11 | 2017-06-27 | 삼성전자주식회사 | 행렬 네트워크 코딩을 사용하는 장치 및 방법 |
US8458555B2 (en) * | 2010-06-30 | 2013-06-04 | Lsi Corporation | Breaking trapping sets using targeted bit adjustment |
US8467438B2 (en) * | 2010-08-02 | 2013-06-18 | Bassel F. Beidas | System and method for iterative nonlinear compensation for intermodulation distortion in multicarrier communication systems |
CN101902302B (zh) * | 2010-08-17 | 2012-11-07 | 北京邮电大学 | 针对分组码的复杂度固定的联合列表检测译码方法 |
JP2012244305A (ja) * | 2011-05-17 | 2012-12-10 | Toshiba Corp | メモリコントローラ、半導体メモリ装置、および復号方法 |
US8707123B2 (en) * | 2011-12-30 | 2014-04-22 | Lsi Corporation | Variable barrel shifter |
CN103199874B (zh) * | 2012-01-05 | 2017-02-15 | 国民技术股份有限公司 | 一种低密度奇偶校验码译码方法 |
US20130332790A1 (en) * | 2012-06-07 | 2013-12-12 | Lsi Corporation | LDPC Decision Driven Equalizer Adaptation |
US8719682B2 (en) * | 2012-06-15 | 2014-05-06 | Lsi Corporation | Adaptive calibration of noise predictive finite impulse response filter |
US9612903B2 (en) * | 2012-10-11 | 2017-04-04 | Micron Technology, Inc. | Updating reliability data with a variable node and check nodes |
US9048870B2 (en) * | 2012-11-19 | 2015-06-02 | Lsi Corporation | Low density parity check decoder with flexible saturation |
US9235488B2 (en) * | 2013-03-15 | 2016-01-12 | Pmc-Sierra Us, Inc. | System and method for random noise generation |
US9235467B2 (en) * | 2013-03-15 | 2016-01-12 | Pmc-Sierra Us, Inc. | System and method with reference voltage partitioning for low density parity check decoding |
US9252817B2 (en) * | 2014-01-10 | 2016-02-02 | SanDisk Technologies, Inc. | Dynamic log-likelihood ratio mapping for error correcting code decoding |
US10298263B2 (en) * | 2014-02-18 | 2019-05-21 | Seagate Technology Llc | Refresh, run, aggregate decoder recovery |
US9317365B2 (en) * | 2014-03-06 | 2016-04-19 | Seagate Technology Llc | Soft decoding of polar codes |
CN104464822B (zh) * | 2014-11-21 | 2016-04-20 | 湖南大学 | 一种基于闪存错误区间的ldpc纠错编码方法 |
-
2016
- 2016-03-30 US US15/086,006 patent/US10164656B2/en active Active
-
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-
2018
- 2018-11-18 US US16/194,374 patent/US10630316B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8051363B1 (en) * | 2007-01-16 | 2011-11-01 | Marvell International Ltd. | Absorb decode algorithm for 10GBase-T LDPC decoder |
US9021332B2 (en) * | 2012-12-11 | 2015-04-28 | Seagate Technology Llc | Flash memory read error recovery with soft-decision decode |
US20160027521A1 (en) * | 2014-07-22 | 2016-01-28 | NXGN Data, Inc. | Method of flash channel calibration with multiple luts for adaptive multiple-read |
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