TWI708305B - Improved method of mass sampling test for wafer process yield analysis - Google Patents

Abstract

An improved method for mass sampling testing of wafer process yield analysis is to set up an addressable device array to be tested on a semiconductor wafer, and set up an addressing signal circuit on a probe card, and then use an automatic test machine to follow appropriate Operation program, output control signal to control the address signal circuit to generate multi-bit parallel address signal, and then manipulate the addressable DUT array on the semiconductor wafer to switch and select the DUT, and then use the automatic test machine to wait For the test of the test component, a large number of sampling tests can be completed by repeating these steps of switching and selecting and testing components. The invention can assist in using the limited resources of the automatic testing machine to perform more efficient testing, so as to reduce the time cost and equipment cost of a large number of sampling tests.

Description

Improved method of mass sampling test for wafer process yield analysis

The present invention is an improved method for mass sampling test of wafer process yield analysis. By setting address signal circuit on the probe card, it can assist in using the limited resources of automatic tester to more efficiently perform addressable components under test Array testing to reduce the time cost and equipment cost of a large number of sampling tests.

As the semiconductor industry technology continues to advance, the number of transistors and wires in the chip circuit is also increasing. Therefore, in the field of wafer electrical parameter testing in the semiconductor industry, especially the statistical analysis of wafer process yield, in order to For a more substantial statistical analysis of wafer process yield, it is necessary to obtain a larger amount of test data. Therefore, the industry has developed some methods to support this technical demand over the past years, for example: on semiconductor wafers Set up a test circuit of the "addressable device under test array" so that a limited number of test probe pins can be used to test more devices under test, and in this way, the test efficiency can be improved to avoid testing caused by a large number of sampling tests A heavy burden on production capacity.

If the conventional technology wants to use the limited hardware resources of the automatic test machine to perform a large number of sampling tests for the statistical analysis of the wafer process yield, a typical method is to directly integrate all the related circuits of the "device under test" and the "address logic" Set on the wafer, and often use the "sequential logic circuit" design to cope with the limited number of probe pins. Although such a scheme is feasible in terms of engineering technology, it has great contradictions in practical terms. Because in the new generation and a half During the development of the conductor process technology, the new process technology is in an immature and stable state. If all address-related logic circuits are installed on the wafer, the address-related circuits may be very sensitive to the variability of the semiconductor process. Too stable, so it is easy to derive many test problems, even if a large amount of test data is obtained, it is difficult to perform reliable statistical analysis of the process yield.

In order to solve the above-mentioned problems, the conventional technology usually adopts two typical solutions. One is to add some inspection mechanisms to the address circuit on the semiconductor wafer or the array of components under test to perform the error detection of the address circuit, actively detect and Filter out possible wrong data. The second is to try to simplify the design of the addressable device under test array, especially to avoid using "sequential logic circuits"; try to use relatively simple "combination logic circuits", such as "decoder circuits" or "solutions". Multiplexer circuit" to reduce the probability of occurrence of abnormal state of the addressing circuit.

However, if the "sequential logic circuit" is not used, and the "combinational logic circuit" is used to design the addressing circuit of the DUT array on the semiconductor wafer, it will require a lot of probe pins on the wafer to achieve comparison. The addressing function of the large array of devices under test causes two shortcomings. One is that the probe pins consume a lot of available area on the wafer; the other is that it will increase the threshold of hardware resource requirements for automatic testers, thus causing automatic The cost of test equipment increases.

Therefore, after active thinking, prototype testing and continuous improvement, the inventor finally developed a simple and practical improvement plan, especially to solve the second shortcoming mentioned above.

The present invention discloses an improved method for mass sampling test of wafer process yield analysis, including:

a. At least one array of addressable devices to be tested is arranged on a semiconductor wafer, and the array of addressable devices to be tested has multiple addressing signal input terminals;

b. Set up at least a certain address signal circuit on a probe card. The address signal circuit has multiple input terminals for receiving power and control signals output by an automatic tester. The address signal circuit has multiple address signal output terminals. Used to output a multi-bit parallel address signal;

c. During the execution of the test task of the automatic tester, by the electrical connection path established by the probe card, each of the addressing signal output ends of the addressing signal circuit is electrically connected to the addressable component under test on the semiconductor wafer Each address signal input terminal corresponding to the array;

d. The automatic test machine outputs control signals to the input terminals of the address signal circuit on the probe card, so that the address signal circuit generates the multi-bit parallel address signal at the address signal output terminals, thereby controlling The array of addressable devices to be tested on the semiconductor wafer is switched to select at least one device to be tested;

e. The automatic test machine uses its test resources to measure the selected component under test;

f. Repeat step d and step e continuously to complete the test of the addressable device under test array.

With the above method, by setting the addressing signal circuit on the probe card, the limited resources of the automatic test machine can be used to more efficiently perform the test of the addressable device under test array, thereby reducing the amount of sampling and testing. Time cost and equipment cost.

S1: Step a

S2: Step b

S3: Step c

S4: Step d

S5: Step e

S6: Step f

10: Semiconductor wafer

12: Addressable array of components to be tested

121: Addressing signal input terminal

20: Probe card

201: Voltage divider circuit

202: resistor

203: Relay

22: Addressing signal circuit

221: Input

222: Addressing signal output terminal

223: Multi-bit parallel address signal

24: Reset signal pin

30: Diode

32: capacitor

40: automatic testing machine

50: component under test

[Figure 1] is a flowchart of the method of the present invention

[Figure 2] is a schematic diagram of the first embodiment of the present invention

[Figure 3] is a schematic diagram of the second embodiment of the present invention

[Figure 4] is a schematic diagram of the AC and DC voltage signal of the second embodiment of the present invention

[Figure 5] is a schematic diagram of the third embodiment of the present invention

[Figure 6] is a schematic diagram of the fourth embodiment of the present invention

[Figure 7] is a schematic diagram of the fifth embodiment of the present invention

Referring to FIG. 1, the present invention discloses an improved method for mass sampling test for wafer process yield analysis, including:

Step aS1. At least one addressable device under test array 12 is set on a semiconductor wafer 10, and the addressable device under test array 12 has a plurality of address signal input terminals 121.

Step bS2. At least a certain address signal circuit 22 is provided on a probe card 20. The address signal circuit 22 has a plurality of input terminals 221 for receiving power and control signals output by an automatic tester 40. The address signal circuit 22 has The complex address signal output terminal 222 can output a multi-bit parallel address signal 223. The address signal circuit 22 is set up to be controlled by the automatic tester 40 to generate the multi-bit parallel address signal 223, so it is a kind of The addressing signal generator provided on the probe card 20 is not a signal shunt of the automatic tester 40.

Step cS3. During the execution of the test task by the automatic tester 40, the address signal output terminals 222 of the address signal circuit 22 are electrically connected to the semiconductor wafer 10 through the electrical connection path established by the probe card 20 Each of the addressable signal input terminals 121 corresponding to the addressable device array 12 under test.

Step dS4. The automatic testing machine 40 outputs a control signal to the addressing signal circuit 22 on the probe card 20, so that the addressing signal circuit 22 generates the multi-bit parallel addressing signal 223 at the addressing signal output terminals 222, by This controls the addressable to be tested on the semiconductor wafer 10 The component array 12 is switched to select at least one component 50 to be tested.

Step eS5. The automatic test machine 40 uses its test resources to measure the selected component under test 50.

Step fS6. Repeat step d and step e continuously to complete the test of the addressable DUT array 12.

Through the above-mentioned methods and steps, especially the addressing signal circuit 22 is provided on the probe card 20, it is possible to assist in generating the multi-bit parallel addressing that must be provided by the test resources of the automatic test machine 40 itself. The signal 223 enables the automatic test machine 40 to be upgraded and expanded by adding an "addressed signal generator", and becomes more capable of supporting the application of a large number of sampling tests of the array 12 of addressable devices under test.

In order to more clearly describe an improved method of mass sampling test for wafer process yield analysis proposed by the present invention, the following will describe the embodiments of the present invention in detail with the drawings.

For the first embodiment, please refer to Fig. 2 in conjunction with Fig. 1. The automatic test machine 40 has only 8 Source Measurement Units, which can output or input voltage and current signals for voltage and current measurement. There is also a reference Ground Unit, the probe card 20 has at least 16 probes, and the addressing signal circuit 22 provided on the probe card 20 adopts a 10-bit counter circuit, which is a sequential logic circuit. The signal circuit 22 has a power input terminal (Vcc), a power reference ground (Gnd), a control terminal (CLK), a reset signal pin 24 (RST) and a complex address signal output terminal 222 (Q1~Q10). The automatic tester 40 uses three power measurement units and the reference ground unit to control the operation of the address signal circuit 22. In this embodiment, the addressable device under test array 12 provided on the semiconductor wafer 10 has a demultiplexer circuit and 1024 waiting devices 50, each of which is a three-terminal device. , Need to configure three power measurement units (VHF, VHS, VL) for measurement. First, the automatic tester 40 supplies the working voltages Vcc and Vcc2 of the logic circuit, and before step dS4, outputs a voltage signal to the reset signal pin 24 (RST) of the address signal circuit 22, and the status of the counter circuit Return to zero to complete the state initialization of the address signal circuit 22; then, the automatic test machine 40 outputs a pulse signal to the control terminal (CLK) of the address signal circuit 22, and controls the address signal circuit 22 to perform the address signal The output terminal 222 (Q1~Q10) generates the multi-bit parallel address signal 223, and then uses the multi-bit parallel address signal 223 to control the demultiplexer circuit on the semiconductor wafer 10 to test the endpoints (VHF, VHS, VL) switch to connect to at least one DUT 50 in the addressable DUT array 12, and then wait for the circuit to stabilize, the automatic test machine 40 can test the DUT through the above-mentioned test terminal 50. After that, the automatic tester 40 only needs to continue to repeat the steps of "output control signal", "wait for the circuit to stabilize", and "test each component under test 50 selected" to finally complete the addressable component under test. A large number of sampling test tasks for the array 12.

For the second embodiment, please refer to FIGS. 3 and 4 in conjunction with FIG. 1. The automatic test machine 40 only has 8 Source Measurement Units and one Ground Unit. In order to save these very limited hardware Physical resources, two additional auxiliary improvements can be made:

1. A higher working voltage can be used to generate a lower working voltage. For example: if the working voltage (Vcc2) of the addressable device under test array 12 is less than the working voltage (Vcc) of the addressing signal circuit 22 on the probe card 20, a voltage divider can be set on the probe card 20 The circuit 201 (voltage divider) allows the automatic testing machine 40 to provide a higher working voltage (Vcc), and then with the help of the voltage divider circuit 201 to generate a lower working voltage (Vcc2), thereby Way to save the resource usage of the automatic testing machine 40.

2. It can be on the electrical connection path of the power pin Vcc of the address signal circuit 22 A diode 30 is connected in series, and then a capacitor 32 is connected in parallel to the power reference ground pin (Gnd) for rectification and stabilization, so that a hardware resource of the automatic test machine 40 can be used to output AC and DC voltage signals. In order to provide the operating voltage (Vcc) required by the addressing signal circuit 22 and the control signal (CLK) required by switching to select any component under test 50; the specific form of the AC and DC voltage signal can be seen in the example shown in FIG. 4.

Through the above-mentioned two auxiliary improvements, the automatic test machine 40 can have another two remaining power measurement units which can be applied to more flexible addressing array circuit design or to provide more types of the waiting test components 50 to perform A large number of sampling tests.

For the third embodiment, please refer to FIG. 5 in conjunction with FIG. 1. The automatic testing machine 40 has only 8 Source Measurement Units and one Ground Unit. If it is limited by software and hardware or other factors As a result, the automatic testing machine 40 can only output current signals as the control signal source of the addressing signal circuit 22 on the probe card 20, which can be between the control signal pin (CLK) and the power reference ground pin (Gnd) A resistor 202 is provided, so that the current signal output by the automatic testing machine 40 can be converted into a voltage signal.

The fourth embodiment is a continuation of the second embodiment. Please refer to FIG. 6 in conjunction with FIG. 1. This embodiment also adopts a voltage stabilization design to save the hardware resources of the automatic test machine 40, but in addition, it is specially considered to avoid this Some sensitive measurement functions of the automatic tester 40 are interfered by the address signal circuit 22, so at least one relay 203 can be provided on the probe card 20, and the relay 203 can provide the necessary circuit isolation function of the probe card 20 , Isolate the input terminal 221 pins of the address signal circuit 22 and the address signal output terminal 222 pins. Therefore, at least one power measuring unit can be used to supply the driving voltage Vpp required by each of the relays 203. In the schematic diagram of this embodiment, only each of the relays 203 is marked, and the power supply lines required for the actual operation of each of the relays 203 are not depicted. Way to avoid overly complicated graphic content. From this embodiment, it can be known that if it is necessary to exclude that the addressing signal circuit 22 may interfere with some sensitive measurement functions of the automatic test machine 40, the relays 203 can be used to solve this concern. With the new method of the present invention, the automatic test machine 40 with such a simple configuration can be used to perform a large number of sampling tests, even if the circuit isolation function needs to be considered.

For the fifth embodiment, please refer to FIG. 7 in conjunction with FIG. 1. This embodiment uses a relatively new type of automatic test machine 40. The automatic test machine 40 has at least 25 Source Measurement Units, and the probe A 12-bit counter circuit is provided on the pin card 20 to implement the addressing signal circuit 22 to control a larger array of addressable devices under test 12 provided on the semiconductor wafer 10. The array structure consists of 6 The array of components to be tested is assembled together to share multiple addressing signal input terminals 121 (A1~A12). The total number of components to be tested 50 arranged in the array of addressable components to be tested 12 is 24,576, each of which is to be tested The components 50 are all four-terminal components, so the number of samples is very considerable. The automatic test machine 40 is equipped with 4 power measurement units to control the operation of the addressing signal circuit 22, and the remaining 21 power measurement units are used for the circuit power supply of the addressable DUT array 12 and each of the waiting devices selected for measurement.测Component 50. During the execution of the test task of the automatic test machine 40, the probe card 20 establishes the necessary electrical connection path between the automatic test machine 40 and the addressable device under test array 12, and then the automatic test machine 40 can pass the RST The two pins and CLK are used to reset and control the address signal circuit 22 to generate the multi-bit parallel address signal 223 at the address signal output terminals 222, thereby simultaneously controlling 6 of the addressable DUT array 12 In this way, the six selected components 50 to be tested can be synchronously switched and selected, and then the six selected components 50 to be tested are synchronously tested in parallel by the automatic testing machine 40. By repeating the above steps of switching, selecting and testing each of the components under test 50, the semiconductor wafer 10 can be completed A large number of sampling tests required by the statistical analysis of the advanced process yield.

In the above-mentioned embodiment, the address signal circuit 22 provided on the probe card 20 is a simple counter logic circuit, which switches and selects the DUT 50 in a sequential addressing manner. The control signal output by the automatic tester 40 to the address signal circuit 22 is an analog pulse signal, which can be in the form of a voltage pulse signal or a current pulse signal.

In the above, the address signal circuit 22 provided on the probe card 20 can also be implemented by a more complicated digital function circuit, so that the control signal output from the automatic test machine 40 to the address signal circuit 22 can be a digital signal. , To support more flexible random address switching capabilities.

Summarizing the above description, the method of the present invention can help overcome the shortcomings faced by the conventional technology. It has the above-mentioned numerous advantages and practical values. In the description of the specification, in order to enable the reader to have a more complete understanding of the present invention, many specific Details; however, the present invention may still be implemented under the premise of omitting some or all of these characteristic details; but those familiar with this technology can make changes and modifications to the present invention without departing from the spirit and principle of the present invention, and these Changes and modifications shall be covered in the scope defined by the scope of the following patent applications.

S1: Step a

S2: Step b

S3: Step c

S4: Step d

S5: Step e

S6: Step f

10: Semiconductor wafer

12: Addressable array of components to be tested

121: Addressing signal input terminal

20: Probe card

22: Addressing signal circuit

221: Input

222: Addressing signal output terminal

223: Multi-bit parallel address signal

40: automatic testing machine

50: component under test

Claims (9)

An improved method for mass sampling test for wafer process yield analysis, including: a. At least one array of addressable devices to be tested is arranged on a semiconductor wafer, and the array of addressable devices to be tested has multiple addressing signal input terminals; b. Set up at least a certain address signal circuit on a probe card. The address signal circuit has multiple input terminals for receiving power and control signals output by an automatic tester. The address signal circuit has multiple address signal output terminals. To output a multi-bit parallel address signal; c. During the execution of the test of the automatic tester, through the electrical connection path established by the probe card, each of the addressing signal output terminals is electrically connected to each corresponding to the addressable device under test array on the semiconductor wafer The addressing signal input terminal; d. The automatic test machine outputs control signals to the input terminals of the address signal circuit on the probe card, so that the address signal circuit generates the multi-bit parallel address signal at the address signal output terminals, thereby controlling The array of addressable devices to be tested on the semiconductor wafer is switched to select at least one device to be tested; e. The automatic test machine uses its test resources to measure the selected component under test; f. Repeat step d and step e continuously to complete the test of the addressable device under test array. For example, the improved method of mass sampling test for wafer process yield analysis of claim 1, wherein a reset signal pin is provided on the address signal circuit, and the automatic tester can output a voltage signal to the repeater before step d Set the signal pin to initialize the state of the address signal circuit. For example, the improved method for mass sampling test of wafer process yield analysis of claim 1, wherein a voltage divider circuit is provided on the probe card to supply the circuit operation of the addressable device under test array on the semiconductor wafer Required operating voltage. For example, the improved method of mass sampling test for wafer process yield analysis of claim 1, wherein the electrical connection line of the power pin of the addressing signal circuit is provided with a diode and a capacitor to provide rectification and voltage stabilization, so that the The power pin and the control signal pin of the address signal circuit can share the output of the same hardware resource of the automatic tester. For example, the improved method for mass sampling test of wafer process yield analysis of claim 1, wherein at least one relay is provided on the probe card to isolate the address signal circuit in a timely manner. For example, the improvement method of mass sampling test for wafer process yield analysis of claim 1 Method, wherein a resistor is arranged on the probe card to convert the current signal into a voltage signal. For example, the improved method for mass sampling test of wafer process yield analysis of claim 1, wherein the address signal circuit provided on the probe card is a simple counter logic circuit. For example, the improved method of mass sampling test for wafer process yield analysis of claim 1, wherein the control signal output by the automatic tester to the addressing signal circuit is a voltage pulse signal or a current pulse signal, which supports sequential addressing Switch to select the component under test. For example, the improved method of mass sampling test for wafer process yield analysis of claim 1, wherein the automatic test machine can use digital signals to control the operation of the address signal circuit, and switch to select the component under test by supporting random addressing .

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