CN116955031A - Method for improving number of chips simultaneously tested by tester - Google Patents
Method for improving number of chips simultaneously tested by tester Download PDFInfo
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- CN116955031A CN116955031A CN202310798041.9A CN202310798041A CN116955031A CN 116955031 A CN116955031 A CN 116955031A CN 202310798041 A CN202310798041 A CN 202310798041A CN 116955031 A CN116955031 A CN 116955031A
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- 238000012360 testing method Methods 0.000 claims abstract description 79
- 230000008054 signal transmission Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 3
- 238000005086 pumping Methods 0.000 claims description 3
- 239000013256 coordination polymer Substances 0.000 abstract 1
- 230000006870 function Effects 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 4
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- 238000010998 test method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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Abstract
The application provides a method for improving the number of chips simultaneously tested by a tester, which comprises the following steps: providing a tester, wherein the tester comprises a plurality of digital IO channels; providing a plurality of chips to be tested, wherein the chips comprise a signal IO pin, two digital IO channels are distributed to the signal IO pin of each chip, the first digital IO channel is directly connected to the signal IO pin, and the second digital IO channel is connected to the signal IO pin in series with a resistor; using the first digital IO channel to perform output driving and input comparison test; and testing input and output signals of the chip through different states by using a second digital IO channel, wherein the output signals comprise current load capacity. The second digital IO channel is connected in series with a resistor and connected to the signal IO pin, and the second digital IO channel plays a role of load current through different states. In the channels contained in the tester, under the working condition that not all channels have the current load testing function, the simultaneous testing capability of the chip CP test is improved.
Description
Technical Field
The application belongs to the technical field of integrated circuit testing, and particularly relates to a method for improving the number of chips tested by a tester.
Background
A conventional memory chip Pin (PAD) includes: a power pin, a ground pin, and for example, four signal pins. The four signal pins are respectively a clock signal pin, a reset signal pin, an analog signal pin and an IO (input output) signal pin, and the four signal pins of a conventional memory chip are used for configuring four digital IO channels. Only IO signal pins in the four signal pipes are special, and output signals in the IO signals comprise current load capacity, so that a digital IO channel self-contained current load test module distributed to the IO signal pins by a tester is required, namely the channel has a programmable current load function; and three digital IO channels which are distributed by the tester and are distributed by the other three signal pins except the IO signal pin of a conventional memory chip do not need to have a programmable current load function.
Only one signal pin needs to be provided with a programmable current load function for a digital IO channel corresponding to the tester based on four signal pins of a conventional memory chip. Therefore, the digital IO channels are greatly increased, and meanwhile, in order to save cost, the performances of the digital IO channels are simplified, for example, the important function 'programmable current load' of the digital IO channels is changed, each digital IO channel in the N digital IO channels is provided with a programmable current load function, and the number of the digital IO channels is reduced to be only N/4 digital IO channels with programmable current loads.
However, with the improvement of the memory chip, the number of signal pins of the improved memory chip is reduced, and the simplified tester has the problem of lower number of simultaneous test chips when testing the improved memory chip.
Disclosure of Invention
The application aims to provide a method for improving the number of chips simultaneously tested by a tester, wherein a resistor is connected to a signal IO pin in series with a second digital IO channel, and the second digital IO channel plays a role of load current through different states. In the channels contained in the tester, under the working condition that not all channels have the current load testing function, the simultaneous testing capability of the chip CP test is improved.
The application provides a method for improving the number of chips simultaneously tested by a tester, which comprises the following steps:
providing a tester, wherein the tester comprises a plurality of digital IO channels;
providing a plurality of chips to be tested, wherein the chips comprise a signal IO pin, two digital IO channels are distributed to the signal IO pin of each chip, and the two digital IO channels are named as a first digital IO channel and a second digital IO channel respectively; the first digital IO channel is directly connected to the signal IO pin, and the second digital IO channel is connected to the signal IO pin in series with a resistor;
using the first digital IO channel to perform output driving and input comparison test; and testing input and output signals of the chip through different states by using the second digital IO channel, wherein the output signals comprise current load capacity.
Further, the voltage between the resistor and the second digital IO channel is defined as an output driving voltage, and the different states include:
first state: when the output driving voltage is a power supply voltage, a filling current is generated for the signal IO pin, and the function of a pull-up resistor is achieved;
second state: when the output driving voltage is ground potential, a pumping current is generated for the signal IO pin, and the effect of a pull-down resistor is achieved;
third state: the output drive is disconnected, and the signal IO pin is in a no-current load state.
Further, the chip has only three pins including a power pin, a ground pin and the signal IO pin, and is defined as a single signal pin chip.
Further, the tester includes an even number of the digital IO channels, and the number of the chips measured by the tester is half of the total number of the digital IO channels.
Further, the first digital IO channel is used for signal transmission and reception; the first digital IO channel performs output driving and input comparison test, and the method comprises the following steps: test clock signal, reset signal and analog signal.
Further, the resistance of the resistor is determined according to the working voltage and the driving capability of the signal IO pin of the chip.
Further, the resistance value of the resistor ranges from 500 ohms to 10 Kohms.
Further, the number of channels of the self-powered load test module of the tester is less than half of the total number of the digital IO channels.
Further, the current load test function of the channel of the self-powered load test module is not enabled, and the channel is uniformly used as a digital IO channel without the current load test function, wherein half of the total number of the digital IO channels are used as the first digital IO channel, and the other half of the total number of the digital IO channels are used as the second digital IO channel.
Further, the signal IO pin of the chip can be used as a digital pin or an analog pin;
when the signal IO pin is used as a digital pin, the second digital IO channel is disconnected with the resistor in an input instruction period, and the first digital IO channel sends an instruction waveform;
in the output instruction period, the second digital IO channel outputs power supply voltage, plays a role of a pull-up resistor for the signal IO pin, and the first digital IO channel receives an output waveform;
when the signal IO pin is used as an analog pin, the second digital IO channel is disconnected with the resistor, and the first digital IO channel measures analog parameters on the signal IO pin by using a self-contained voltage/current meter.
Compared with the prior art, the application has the following beneficial effects:
the application provides a method for improving the number of chips simultaneously tested by a tester, which comprises the following steps: providing a tester, wherein the tester comprises a plurality of digital IO channels; providing a plurality of chips to be tested, wherein the chips comprise a signal IO pin, two digital IO channels are distributed to the signal IO pin of each chip, and the two digital IO channels are named as a first digital IO channel and a second digital IO channel respectively; the first digital IO channel is directly connected to the signal IO pin, and the second digital IO channel is connected to the signal IO pin in series with a resistor; using the first digital IO channel to perform output driving and input comparison test; and testing input and output signals of the chip through different states by using the second digital IO channel, wherein the output signals comprise current load capacity. According to the application, the second digital IO channel is connected in series with a resistor to be connected to a signal IO pin, and the second digital IO channel plays a role of load current through different states. In the channels contained in the tester, under the working condition that not all channels have the current load testing function, the simultaneous testing capability of the chip CP test is improved.
Drawings
FIG. 1 is a flow chart of a method for increasing the number of chips tested by a tester according to an embodiment of the application.
FIG. 2 is a schematic diagram illustrating a method for increasing the number of chips tested by a tester according to an embodiment of the present application.
Wherein, the reference numerals are as follows:
10-chip; 21-a first digital IO channel; 22-a second digital IO channel; 30-resistance.
Detailed Description
As described in the background art, the number of signal pins of the improved memory chip is reduced, and the simplified tester has the problem of lower number of simultaneous test chips when testing the improved memory chip.
Specifically, the number of signal pins of the improved memory chip is reduced, for example, only 1 signal IO pin is provided, and the number of the improved memory chip pins is only three, including a power supply pin (power PAD), a ground pin (ground PAD) and a signal IO pin (IO PAD), and the chip is called a single signal pin (OnePin) chip. For a single signal pin chip, a digital IO channel without a programmable current load cannot be used for signal IO pin testing, and only the digital IO channel with the programmable current load can be used for signal IO pin testing.
The single signal pin (OnePin) chip occupies less tester resources, 1 single signal pin chip only needs to be configured with one digital IO channel with a programmable current load function, for example, the simplified tester shares N (N is equal to 1024) digital IO channels, and only N/4 channels, namely 256 channels, have dynamic current load capacity (programmable current load function), so that the number of the single signal pin chips can only reach 1/N of the total number of the digital IO channels by using the simplified tester, namely 3N/4 channels cannot be used because the simplified tester does not have the programmable current load function, and therefore, the number of the single signal pin (OnePin) chips tested by the simplified tester is lower.
Based on the above research, the application provides a method for improving the number of chips tested by a tester. The application is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the application.
For ease of description, some embodiments of the application may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
The embodiment of the application provides a method for improving the number of chips simultaneously tested by a tester, as shown in fig. 1 and 2, comprising the following steps:
step S1, providing a tester, wherein the tester comprises a plurality of digital IO channels;
step S2, providing a plurality of chips 10 to be tested, wherein the chips 10 comprise a signal IO pin (IO PAD), two digital IO channels are distributed to the signal IO pin of each chip 10, and the two digital IO channels are named as a first digital IO channel 21 and a second digital IO channel 22 respectively; wherein, the first digital IO channel 21 is directly connected to the signal IO pin, and the second digital IO channel 22 is connected in series with a resistor 30 to the signal IO pin;
step S3, performing output driving and input comparison test by using the first digital IO channel 21; the second digital IO channel 22 is used to test the input and output signals of the chip 10, including current loading capability, by different states.
Specifically, in an example, the chip to be tested is a memory chip, and the tester is a memory tester.
The chips 10 to be tested may be chips on the same wafer or chips on different wafers. The chip CP (chip probing) test is to test the wafer chips which are not packaged yet, screen qualified chips, determine whether to package, and the basic principle is that probes are excited to Pins (PADs) by signals, and then test the function to verify whether each chip meets the chip specification.
In one example, the pins of the chip 10 are only three, including: a power supply pin (power PAD), a ground pin (ground PAD) and a signal IO pin (IO PAD), wherein the chip is defined as a single signal pin (OnePin) chip; i.e. there is only one signal pin. Various tests are performed through the unique signal IO pin, including, for example: clock signal testing, reset signal testing, analog signal testing, input Output (IO) signal testing, various tests multiplex (share) unique signal IO pins.
A single signal pin (OnePin) chip is a chip which can realize that each module inside the chip can be tested by only one signal pin through a specific DFT (Design For Test) circuit. The chip has the advantages that: only three PAD (power PAD, IO PAD and ground PAD) probes are needed to be pricked by each chip, and one digital IO channel is occupied. The DFT circuit is used for inserting various hardware logics for improving the testability (including controllability and observability) of the chip in the stage of the original design of the chip, and generating test vectors through the logics so as to achieve the aim of testing the large-scale chip.
The first digital IO channel 21 serves as signal transmission and reception; the first digital IO channel 21 performs output driving and input comparison tests including, for example: test clock signal, reset signal and analog signal.
The voltage between resistor 30 and second digital IO channel 22 is defined as the output drive voltage (voltage at a), and the current load capability of chip 10 is tested by using the second digital IO channel 22 through different states, specifically including: first state: when the output driving voltage (voltage at A) is the power supply voltage, a filling current is generated on a signal IO pin (IO PAD) to play a role of a pull-up resistor. Specifically, the tester sends an instruction to the chip 10, the chip 10 responds to the output signal from the signal IO pin, the output signal at this time is weaker, the second digital IO channel 22 outputs a driving voltage, the output driving voltage is a power supply voltage (for example, 1.8V-5V), and the pull-up resistor acts on the signal IO pin. Second state: when the output driving voltage is ground potential, a pumping current is generated for the signal IO pin, and the effect of a pull-down resistor is achieved. Third state: the output drive is off (i.e., off at a), and the signal IO pin is in a no-current load state.
The signal IO pin of the chip 10 may be used as either a digital pin or an analog pin. When the signal IO pin is used as a digital pin, the second digital IO channel 22 is disconnected from the resistor 30 during the input command period, and the first digital IO channel 21 transmits a command waveform. In the output command period, the second digital IO channel 22 outputs the power supply voltage, acts as a pull-up resistor for the signal IO pin, and the first digital IO channel 21 receives the output waveform. When the signal IO pin is used as an analog pin, the second digital IO channel 22 is disconnected from the resistor 30, and the first digital IO channel 21 measures the analog parameter on the signal IO pin using the self-contained voltage/current meter.
The resistance of the resistor 30 is determined according to the working voltage and the driving capability of the signal IO pin of the chip. The resistance value of the resistor is in the range of 500 ohms to 10K ohms, for example.
The number of channels of the tester self-powered load test module is less than half of the total number of digital IO channels. The channels of the self-current load test module have the current load test function not enabled, and are uniformly used as digital IO channels with no current load test function, wherein half of the total number of the digital IO channels are used as first digital IO channels 21, and the other half of the total number of the digital IO channels are used as second digital IO channels 22. The first digital IO channel 21 is used for signal transmission and reception, and the second digital IO channel 22 is used as a power supply of a resistor. The tester comprises an even number of digital IO channels, and the number of the tester co-testing chips is half of the total number of the digital IO channels.
The embodiment of the application can improve the simultaneous testing capability of the chip CP test under the working condition that not all channels in the channels contained in the tester have the current load testing function. For example, the tester has 1024 digital IO channels, only 1/4 channel, namely 256 channels, has dynamic current load capacity, the conventional case OnePi chip CP test can only make 256 simultaneous tests, and after the application is adopted, the OnePi chip can improve the simultaneous test number of the CP test to 512 simultaneous tests, thereby greatly improving the simultaneous test number, reducing the test time of a single wafer and improving the test efficiency. After the scheme of the embodiment is adopted, the dynamic current load capacity of 256 channels is not started, and the 256 channels are uniformly used as digital IO channels with no current load test function. Then 1024 channels, one half of the 512 channels are used as the first digital IO channel for signal transmission and reception, the other half of the second digital IO channels are used as the power supply of the series resistor, and the corresponding same-test number is 512. In practical application, the scheme of the self-powered load test function of the tester is adopted, and the same test number is 256. Or the same measurement is raised to 512 using only the series resistance scheme of the present application. The two schemes cannot be mixed due to the differences in the processing of the test procedure.
In summary, the present application provides a method for increasing the number of chips tested by a tester, comprising: providing a tester, wherein the tester comprises a plurality of digital IO channels; providing a plurality of chips to be tested, wherein the chips comprise a signal IO pin, two digital IO channels are distributed to the signal IO pin of each chip, and the two digital IO channels are respectively named as a first digital IO channel and a second digital IO channel; the first digital IO channel is directly connected to the signal IO pin, and the second digital IO channel is connected with a resistor in series and is connected to the signal IO pin; using the first digital IO channel to perform output driving and input comparison test; and testing input and output signals of the chip through different states by using a second digital IO channel, wherein the output signals comprise current load capacity. According to the application, the second digital IO channel is connected in series with a resistor to be connected to a signal IO pin, and the second digital IO channel plays a role of load current through different states. In the channels contained in the tester, under the working condition that not all channels have the current load testing function, the simultaneous testing capability of the chip CP test is improved.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present application using the method and technical content disclosed above without departing from the spirit and scope of the application, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present application fall within the scope of the technical solution of the present application.
Claims (10)
1. A method for increasing the number of chips simultaneously tested by a tester, comprising:
providing a tester, wherein the tester comprises a plurality of digital IO channels;
providing a plurality of chips to be tested, wherein the chips comprise a signal IO pin, two digital IO channels are distributed to the signal IO pin of each chip, and the two digital IO channels are named as a first digital IO channel and a second digital IO channel respectively; the first digital IO channel is directly connected to the signal IO pin, and the second digital IO channel is connected to the signal IO pin in series with a resistor;
using the first digital IO channel to perform output driving and input comparison test; and testing input and output signals of the chip through different states by using the second digital IO channel, wherein the output signals comprise current load capacity.
2. The method of increasing the number of chips tested by a tester of claim 1, wherein the voltage between the resistor and the second digital IO channel is defined as an output drive voltage, and wherein the different states include:
first state: when the output driving voltage is a power supply voltage, a filling current is generated for the signal IO pin, and the function of a pull-up resistor is achieved;
second state: when the output driving voltage is ground potential, a pumping current is generated for the signal IO pin, and the effect of a pull-down resistor is achieved;
third state: the output drive is disconnected, and the signal IO pin is in a no-current load state.
3. The method of claim 1, wherein the number of pins of the chip includes three, including a power pin, a ground pin and the signal IO pin, and the chip is defined as a single signal pin chip.
4. The method of increasing the number of chips tested together in a tester of claim 3, wherein said tester includes an even number of said digital IO channels, said tester testing together a number of said chips that is half the total number of said digital IO channels.
5. The method for increasing the number of chips simultaneously tested by a tester according to claim 1, wherein the first digital IO channel is used for signal transmission and reception; the first digital IO channel performs output driving and input comparison test, and the method comprises the following steps: test clock signal, reset signal and analog signal.
6. The method of claim 1, wherein the resistance of the resistor is determined according to the signal IO pin operating voltage and the driving capability of the chip.
7. The method for increasing the number of chips simultaneously tested by a tester according to claim 6,
the resistance value of the resistor ranges from 500 ohms to 10 Kohms.
8. The method of increasing the number of simultaneous chips of a tester according to claim 1, wherein the number of channels of the tester self-contained electrical load test module is less than half of the total number of digital IO channels.
9. The method for increasing the number of chips tested by a tester according to claim 8, wherein the channels of the self-contained electric load test module have an electric load test function which is not enabled and are uniformly used as digital IO channels with no electric load test function, half of the total number of the digital IO channels are used as the first digital IO channels, and the other half of the total number of the digital IO channels are used as the second digital IO channels.
10. The method for increasing the number of chips simultaneously tested by a tester according to claim 1, wherein the signal IO pins of the chips can be used as digital pins or analog pins;
when the signal IO pin is used as a digital pin, the second digital IO channel is disconnected with the resistor in an input instruction period, and the first digital IO channel sends an instruction waveform;
in the output instruction period, the second digital IO channel outputs power supply voltage, plays a role of a pull-up resistor for the signal IO pin, and the first digital IO channel receives an output waveform;
when the signal IO pin is used as an analog pin, the second digital IO channel is disconnected with the resistor, and the first digital IO channel measures analog parameters on the signal IO pin by using a self-contained voltage/current meter.
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| CN202310798041.9A CN116955031A (en) | 2023-06-30 | 2023-06-30 | Method for improving number of chips simultaneously tested by tester |
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| CN202310798041.9A CN116955031A (en) | 2023-06-30 | 2023-06-30 | Method for improving number of chips simultaneously tested by tester |
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