TWI704395B - Display apparatus - Google Patents
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本發明是有關於一種電子裝置,且特別是有關於一種顯示裝置。The present invention relates to an electronic device, and more particularly to a display device.
隨著顯示科技的進步,顯示裝置已廣泛應用在日常生活中,舉凡家用的視聽娛樂、公共場合的資訊顯示看板、電競用的顯示器及可攜式電子產品都可見其蹤跡。With the advancement of display technology, display devices have been widely used in daily life, such as home audio-visual entertainment, information display billboards in public places, monitors for e-sports, and portable electronic products.
一般而言,顯示裝置包括畫素陣列基板、對向基板以及設置於畫素陣列基板與對向基板之間的顯示介質。畫素陣列基板具有多個畫素。欲提升顯示裝置的解析度時,須在單位面積中設置數量更多的畫素。也就是說,畫素之畫素電極及資料線的距離會更短。畫素電極及資料線的距離短時,畫素電極及資料線的耦合電容大,進而造成垂直串音(vertical cross-talk)現象。Generally speaking, the display device includes a pixel array substrate, a counter substrate, and a display medium disposed between the pixel array substrate and the counter substrate. The pixel array substrate has a plurality of pixels. To increase the resolution of the display device, more pixels must be set in the unit area. In other words, the distance between the pixel electrode of the pixel and the data line will be shorter. When the distance between the pixel electrode and the data line is short, the coupling capacitance of the pixel electrode and the data line is large, which in turn causes the phenomenon of vertical cross-talk.
本發明提供一種顯示裝置,性能佳。The invention provides a display device with good performance.
本發明一實施例的顯示裝置包括基板、設置於基板上的多個畫素及閘極驅動電路。每一畫素包括掃描線、資料線、第一開關元件及第一畫素電極。第一開關元件具有第一端、第二端及控制端。第一開關元件的第一端電性連接至資料線。第一開關元件的控制端電性連接至掃描線。第一畫素電極電性連接至第一開關元件的第二端。多個畫素包括依序排列的N個畫素,N為大於或等於2的正整數,N個畫素包括第p個畫素及第q個畫素,p為小於或等於N的奇數且為正整數,q為小於或等於N的偶數且為正整數。閘極驅動電路與第p個畫素的一掃描線電性連接,其中於一圖框區間的第一子圖框區間內,閘極驅動電路接收第一啟始訊號,以產生第一閘極脈衝訊號。閘極驅動電路與第q個畫素的一掃描線電性連接,其中於第一子圖框區間之後的同一圖框區間的第二子圖框區間,閘極驅動電路接收第二啟始訊號,以產生第二閘極脈衝訊號。第一閘極脈衝訊號具有第一致能時間寬度,第二閘極脈衝訊號具有第二致能時間寬度,且第一致能時間寬度與第二致能時間寬度不同。A display device according to an embodiment of the present invention includes a substrate, a plurality of pixels arranged on the substrate, and a gate driving circuit. Each pixel includes a scan line, a data line, a first switch element and a first pixel electrode. The first switch element has a first end, a second end and a control end. The first terminal of the first switch element is electrically connected to the data line. The control terminal of the first switch element is electrically connected to the scan line. The first pixel electrode is electrically connected to the second end of the first switch element. Multiple pixels include N pixels arranged in sequence, N is a positive integer greater than or equal to 2, N pixels include p-th pixel and q-th pixel, p is an odd number less than or equal to N and Is a positive integer, q is an even number less than or equal to N and is a positive integer. The gate driving circuit is electrically connected to a scan line of the p-th pixel. In the first sub-frame interval of a frame interval, the gate driving circuit receives the first start signal to generate the first gate Pulse signal. The gate driving circuit is electrically connected to a scan line of the q-th pixel, wherein the gate driving circuit receives the second start signal in the second sub-frame interval of the same frame interval after the first sub-frame interval , To generate the second gate pulse signal. The first gate pulse signal has a first enabling time width, the second gate pulse signal has a second enabling time width, and the first enabling time width is different from the second enabling time width.
本發明一實施例的顯示裝置包括基板、設置於基板上的多個畫素及閘極驅動電路。每一畫素包括掃描線、資料線、第一開關元件、第一畫素電極、第二開關元件、第二畫素電極、第三開關元件、控制線及充電更新電容器。第一開關元件具有第一端、第二端及控制端,其中第一開關元件的第一端電性連接至資料線,且第一開關元件的控制端電性連接至掃描線。第一畫素電極電性連接至第一開關元件的第二端。第二開關元件具有第一端、第二端及控制端。第二開關元件的第一端電性連接至資料線。第二開關元件的控制端電性連接至掃描線。第二開關元件的第二端電性連接至第二畫素電極。第三開關元件具有第一端、第二端及控制端。第三開關元件的第一端電性連接至第二開關元件的第二端。第三開關元件的控制端電性連接至控制線。第三開關元件的第二端電性連接至充電更新電容器。多個畫素包括依序排列的N個畫素,N為大於或等於2的正整數,N個畫素包括第p個畫素及第q個畫素,p為小於或等於N的奇數且為正整數,q為小於或等於N的偶數且為正整數。閘極驅動電路與第p個畫素的一掃描線電性連接,其中於一圖框區間的第一子圖框區間內,閘極驅動電路接收第一啟始訊號,以產生第一閘極脈衝訊號。閘極驅動電路與第q個畫素的一掃描線電性連接,其中於第一子圖框區間之後的同一圖框區間的第二子圖框區間,閘極驅動電路接收第二啟始訊號,以產生第二閘極脈衝訊號。A display device according to an embodiment of the present invention includes a substrate, a plurality of pixels arranged on the substrate, and a gate driving circuit. Each pixel includes a scan line, a data line, a first switch element, a first pixel electrode, a second switch element, a second pixel electrode, a third switch element, a control line, and a charge refresh capacitor. The first switch element has a first terminal, a second terminal and a control terminal. The first terminal of the first switch element is electrically connected to the data line, and the control terminal of the first switch element is electrically connected to the scan line. The first pixel electrode is electrically connected to the second end of the first switch element. The second switch element has a first end, a second end and a control end. The first end of the second switch element is electrically connected to the data line. The control terminal of the second switch element is electrically connected to the scan line. The second end of the second switch element is electrically connected to the second pixel electrode. The third switch element has a first end, a second end and a control end. The first end of the third switch element is electrically connected to the second end of the second switch element. The control terminal of the third switch element is electrically connected to the control line. The second terminal of the third switching element is electrically connected to the charging refresh capacitor. Multiple pixels include N pixels arranged in sequence, N is a positive integer greater than or equal to 2, N pixels include p-th pixel and q-th pixel, p is an odd number less than or equal to N and Is a positive integer, q is an even number less than or equal to N and is a positive integer. The gate driving circuit is electrically connected to a scan line of the p-th pixel. In the first sub-frame interval of a frame interval, the gate driving circuit receives the first start signal to generate the first gate Pulse signal. The gate driving circuit is electrically connected to a scan line of the q-th pixel, wherein the gate driving circuit receives the second start signal in the second sub-frame interval of the same frame interval after the first sub-frame interval , To generate the second gate pulse signal.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and descriptions to indicate the same or similar parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”係可為二元件間存在其它元件。It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within the acceptable deviation range of the specific value determined by a person of ordinary skill in the art, taking into account the measurement in question and the The specific amount of measurement-related error (ie, the limitation of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the "about", "approximately" or "substantially" used herein can select a more acceptable range of deviation or standard deviation based on optical properties, etching properties, or other properties, instead of using one standard deviation for all properties .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.
圖1為本發明一實施例之顯示裝置的示意圖。FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention.
圖2示出本發明一實施例之第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7、第二閘極脈衝訊號Vg2、Vg4、Vg6、極性訊號Vpol、第一啟始訊號Vst1、第二啟始訊號Vst2、第一資料訊號Vdl1、第二資料訊號Vdl2及畫素電極的訊號Vpx。FIG. 2 shows the first gate pulse signals Vg1, Vg3, Vg5, Vg7, the second gate pulse signals Vg2, Vg4, Vg6, the polarity signal Vpol, the first start signal Vst1, the second start signal according to an embodiment of the present invention. The start signal Vst2, the first data signal Vdl1, the second data signal Vdl2, and the pixel electrode signal Vpx.
圖3為本發明一實施例之畫素PX的佈局(layout)示意圖。圖1省略圖3之基板110的繪示。FIG. 3 is a schematic diagram of the layout of the pixel PX according to an embodiment of the present invention. 1 omits the illustration of the
圖4為本發明一實施例之顯示裝置的剖面示意圖。圖4之畫素陣列基板1的剖面對應圖3的剖線A-A’及B-B’。4 is a schematic cross-sectional view of a display device according to an embodiment of the invention. The cross-section of the
請參照圖1、圖3及圖4,顯示裝置10包括畫素陣列基板1、相對於畫素陣列基板1的對向基板2以及設置於畫素陣列基板1與對向基板2之間的顯示介質3。1, 3 and 4, the
在本實施例中,對向基板2可選擇性地包括基板210、擋光圖案230及彩色濾光層220。擋光圖案230即俗稱黑矩陣(Black Matrix)。擋光圖案230設置於基板210上,且具有多個開口232。彩色濾光層220設置於基板210上,且與擋光圖案230的多個開口232重疊。然而,本發明不限於此,根據其它實施例,彩色濾光層220及/或擋光圖案230也可設置於畫素陣列基板1的基板110上,而形成彩色濾光器在陣列上(color filter on array;COA)及/或黑矩陣在陣列上(Black matrix on Array;BOA)的結構。In this embodiment, the
在本實施例中,顯示介質3可以是非自發光材料,例如但不限於:液晶。然而,本發明不限於此,根據其它實施例,顯示介質3也可以是自發光材料,例如但不限於:有機電致發光材料、微型發光二極體(µLED)等。In this embodiment, the
畫素陣列基板1包括基板110及設置於基板110上的多個畫素PX。每一畫素PX包括掃描線SL、資料線DL、開關元件T及畫素電極130。資料線DL在第一方向d1上延伸,掃描線SL在第二方向d2上延伸,其中第一方向d1與第二方向d2交錯。開關元件T包括控制端Tc、閘絕緣層GI、半導體圖案Td、第一端Ta及第二端Tb。閘絕緣層GI設置於控制端Tc與半導體圖案Td之間。第一端Ta及第二端Tb分別電性連接至半導體圖案Td的不同兩區。開關元件T的第一端Ta電性連接至資料線DL。開關元件T的控制端Tc電性連接至掃描線SL。畫素電極130電性連接至開關元件T的第二端Tb。The
請參照圖3,在本實施例中,至少一畫素PX包括遮光導電圖案120。遮光導電圖案120設置於畫素PX的資料線DL與畫素PX的畫素電極130之間。也就是說,遮光導電圖案120於基板110上之垂直投影的至少一部分位於資料線DL於基板110上的垂直投影與畫素電極130於基板110上的垂直投影之間。Please refer to FIG. 3, in this embodiment, at least one pixel PX includes a light-shielding
舉例而言,在本實施例中,遮光導電圖案120可包括第一遮光導電部120a及第二遮光導電部120b,第一遮光導電部120a設置於同一畫素PX1的資料線DL與畫素電極130之間,第二遮光導電部120b設置於一畫素PX1的畫素電極130與另一畫素PX2的資料線DL之間。在本實施例中,第一遮光導電部120a及第二遮光導電部120b在第一方向d1上延伸。也就是說,在本實施例中,第一遮光導電部120a、第二遮光導電部120b與資料線DL大致上可平行設置,但本發明不以為限。For example, in this embodiment, the light-shielding
在本實施例中,第一遮光導電部120a與畫素電極130可部分地(partially)重疊,且第二遮光導電部120b與畫素電極130可部分地(partially)重疊。然而,本發明不限於此,根據其它實施例,第一遮光導電部120a及/或第二遮光導電部120b與畫素電極130也可不重疊。In this embodiment, the first light-shielding
請參照圖3及圖4,在本實施例中,遮光導電圖案120與掃描線SL可一起製作。也就是說,遮光導電圖案120與掃描線SL可形成於同一導電層,而遮光導電圖案120的材質與掃描線SL的材質可相同。3 and 4, in this embodiment, the light-shielding
基於導電性的考量,掃描線SL一般是使用金屬材料。但本發明不限於此,根據其他實施例,掃描線SL也可以使用其他導電材料,例如:合金、金屬材料的氮化物、金屬材料的氧化物、金屬材料的氮氧化物、或是金屬材料與其它導電材料的堆疊層。Based on the consideration of conductivity, the scan line SL generally uses a metal material. However, the present invention is not limited to this. According to other embodiments, the scan line SL may also use other conductive materials, such as alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or metallic materials and Stacked layers of other conductive materials.
在本實施例中,遮光導電圖案120具有一預定電位,包括固定電位(例如:0V、接地或浮置(floating)電位)或可調整的非零電位。In this embodiment, the light-shielding
在本實施例中,畫素PX更包括共用電極240(繪於圖4)。共用電極240與畫素電極130之間的電位差用以驅動顯示介質3。In this embodiment, the pixel PX further includes a common electrode 240 (shown in FIG. 4). The potential difference between the
舉例而言,在本實施例中,顯示裝置10可以是多域垂直配向(multi-domain vertical alignment;MVA)型的液晶顯示器,畫素電極130包括第一主幹部130a(繪於圖3)、與第一主幹部130a交錯的第二主幹部130b(繪於圖3)以及連接至第一主幹部130a和第二主幹部130b的多個分支部130c(繪於圖3),且畫素電極130及共用電極240可分別設置於相對的兩基板110、210。然而,本發明不以此為限,根據其它實施例,畫素電極130也可以是其它形狀,及/或畫素電極130與共用電極240也可設置於同一基板。For example, in this embodiment, the
在本實施例中,畫素PX可選擇性地包括遮光電極140(繪於圖3)。遮光電極140與畫素電極130的第一主幹部130a及第二主幹部130b重疊。在本實施例中,遮光電極140與遮光導電圖案120可形成於同一導電層,且遮光電極140可連接於第一遮光導電部120a與第二遮光導電部120b之間,但本發明不以此為限。In this embodiment, the pixel PX may optionally include a light shielding electrode 140 (shown in FIG. 3). The light-shielding
請參照圖1,顯示裝置10還包括用以驅動多個畫素PX的驅動系統。所述驅動系統可包括時序控制電路4、閘極驅動電路5及資料驅動電路6。時序控制電路4與閘極驅動電路5及資料驅動電路6電性連接。閘極驅動電路5與多個畫素PX的掃描線SL電性連接。資料驅動電路6與多個畫素PX的資料線DL電性連接。Please refer to FIG. 1, the
多個畫素PX排成一畫素陣列。在圖1的實施例中,閘極驅動電路5可選擇性地設置於畫素陣列的單側。然而,本發明不限於此,根據其它實施例,閘極驅動電路5也可設置於畫素陣列的相對兩側。Multiple pixels PX are arranged in a pixel array. In the embodiment of FIG. 1, the
多個畫素PX包括沿第一方向d1依序排列的N個畫素PX。N為大於或等於2的正整數。N個畫素PX包括第p個畫素PX及第q個畫素PX,p為小於或等於N的奇數且為正整數,q為小於或等於N的偶數且為正整數。簡言之,沿第一方向d1依序排列的N個畫素PX包括奇數畫素PX與偶數畫素PX。The plurality of pixels PX includes N pixels PX arranged in sequence along the first direction d1. N is a positive integer greater than or equal to 2. The N pixels PX include the p-th pixel PX and the q-th pixel PX, p is an odd number less than or equal to N and a positive integer, and q is an even number less than or equal to N and a positive integer. In short, the N pixels PX arranged in sequence along the first direction d1 include odd-numbered pixels PX and even-numbered pixels PX.
舉例而言,沿第一方向d1依序排列的多個畫素PX包括第1、3、5、7…個畫素PX及第2、4、6…個畫素PX,其中第1、3、5、7…個畫素PX分別包括掃描線SL1、SL3、SL5、SL7…,且第2、4、6個畫素PX分別包括掃描線SL2、SL4、SL6…。For example, the plurality of pixels PX arranged in sequence along the first direction d1 include
請參照圖1及圖2,於一圖框區間t的第一子圖框區間t1內,閘極驅動電路5接收來自於時序控制電路4的第一啟始訊號Vst1,以產生多個第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7…。於第一子圖框區間t1內,多個第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7…依時序傳遞至奇數畫素PX的多條掃描線SL1、SL3、SL5、SL7…。1 and 2, in the first sub-frame interval t1 of a frame interval t, the
於第一子圖框區間t1後之同一圖框區間t的第二子圖框區間t2,閘極驅動電路5接收第二啟始訊號Vst2,以產生多個第二閘極脈衝訊號Vg2、Vg4、Vg6…,其中多個第二閘極脈衝訊號Vg2、Vg4、Vg6…依時序傳遞至偶數畫素PX的多條掃描線SL2、SL4、SL6…。In the second sub-frame interval t2 of the same frame interval t after the first sub-frame interval t1, the
於第一子圖框區間t1及第二子圖框區間t2,時序控制電路4輸出一極性訊號Vpol至資料驅動電路6。於奇數畫素PX的多條掃描線SL1、SL3、SL5、SL7…接收第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7…之後及偶數畫素PX的多條掃描線SL2、SL4、SL6…接收第二閘極脈衝訊號Vg2、Vg4、Vg6…之前,極性訊號Vpol由第一電壓準位切換至第二電壓準位。In the first sub-frame interval t1 and the second sub-frame interval t2, the
資料驅動電路6接收極性訊號Vpol,以於第一子圖框區間t1及第二子圖框區間t2分別輸出第一資料訊號Vdl1及第二資料訊號Vdl2至同一條資料線DL,其中第一資料訊號Vdl1的極性與第二資料訊號Vdl2的極性相反。舉例而言,在本實施例中,畫素陣列包括在一第二方向d2上排列的多個畫素行R1、R2,每一畫素行R1、R2的多個畫素PX在第一方向d1上依序排列;多個畫素行R1、R2包括在第二方向d2上交替排列的多個奇數畫素行R1及多個偶數畫素行R2;於第一子圖框區間t1,奇數畫素行R1的奇數畫素PX具有第一極性(例如:正極性),偶數畫素行R2的奇數畫素PX具有第二極性(例如:負極性);於第二子圖框區間t2,奇數畫素行R1的偶數畫素PX具有第二極性(例如:負極性),偶數畫素行R2的偶數畫素PX具有第一極性(例如:正極性);但本發明不以此為限。The data driving circuit 6 receives the polarity signal Vpol to output the first data signal Vdl1 and the second data signal Vdl2 to the same data line DL in the first sub-frame interval t1 and the second sub-frame interval t2, respectively. The polarity of the signal Vdl1 is opposite to the polarity of the second data signal Vdl2. For example, in this embodiment, the pixel array includes a plurality of pixel rows R1, R2 arranged in a second direction d2, and the plurality of pixels PX of each pixel row R1, R2 are in the first direction d1 Arranged in order; the plurality of pixel rows R1 and R2 include a plurality of odd pixel rows R1 and a plurality of even pixel rows R2 alternately arranged in the second direction d2; in the first subframe interval t1, the odd pixel rows R1 The pixel PX has a first polarity (for example: positive polarity), and the odd pixel PX in the even-numbered pixel row R2 has a second polarity (for example: negative polarity); in the second subframe interval t2, the even-numbered picture in the odd-numbered pixel row R1 The pixel PX has the second polarity (for example: negative polarity), and the even pixel PX of the even pixel row R2 has the first polarity (for example: positive polarity); but the present invention is not limited to this.
藉此,畫素電極130於第一子圖框區間t1及第二子圖框區間t2分別與極性相反的資料線DL耦合。因資料線DL與畫素電極130的電容耦合而分別於第一子圖框區間t1及第二子圖框區間t2造成之畫素電極130之訊號Vpx的電壓差
及電壓差
可互相補償,進而改善垂直串音(vertical cross-talk)現象。
Thereby, the
值得注意的是,第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7…具有第一致能時間寬度W1,第一致能時間寬度W1係指第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7…具有閘極開啟電位的時間長度,第二閘極脈衝訊號Vg2、Vg4、Vg6…具有第二致能時間寬度W2,第二致能時間寬度W2係指第二閘極脈衝訊號Vg2、Vg4、Vg6…具有閘極開啟電位的時間長度,且第一致能時間寬度W1與第二致能時間寬度W2不同。It is worth noting that the first gate pulse signals Vg1, Vg3, Vg5, Vg7... have a first enable time width W1, and the first enable time width W1 refers to the first gate pulse signals Vg1, Vg3, Vg5, Vg7 ...Has the time length of the gate opening potential, the second gate pulse signal Vg2, Vg4, Vg6...has the second enable time width W2, the second enable time width W2 refers to the second gate pulse signal Vg2, Vg4, Vg6...has the time length of the gate on potential, and the first enabling time width W1 is different from the second enabling time width W2.
也就是說,每一畫素PX的畫素電極130、共用電極240及顯示介質3可形成顯示電容,奇數畫素PX的顯示電容與偶數畫素PX的顯示電容分別於第一子圖框區間t1及接續第一子圖框區間t1的第二子圖框區間t2被充電,而奇數畫素PX之顯示電容被充電的時間與偶數畫素PX之顯示電容被充電的時間不同。藉此,能避免因開關元件T漏電所造成的顯示不良。In other words, the
舉例而言,在本實施例中, 。具體而言,第一致能時間寬度W1及/或第二致能時間寬度W2可介於12微秒(µs)~14微秒,但本發明不以此為限。 For example, in this embodiment, . Specifically, the first enabling time width W1 and/or the second enabling time width W2 may be between 12 microseconds (µs) to 14 microseconds, but the invention is not limited thereto.
圖5為本發明另一實施例之畫素PXA的佈局(layout)示意圖。圖5的畫素PXA與圖3的畫素PX類似,兩者的差異在於:圖5的畫素PXA不包括圖3之畫素PX的遮光導電圖案120。也就是說,在圖5的實施例中,資料線DL與畫素電極130之間無設置在第一方向d1上延伸的任何遮光導電圖案。FIG. 5 is a schematic diagram of the layout of a pixel PXA according to another embodiment of the present invention. The pixel PXA in FIG. 5 is similar to the pixel PX in FIG. 3. The difference between the two is that the pixel PXA in FIG. 5 does not include the light-shielding
圖5的畫素PXA可用以取代圖1的畫素PX,而形成另一顯示裝置10A。包括多個畫素PXA的顯示裝置10A也可用前述的驅動系統驅動之。特別是,畫素PXA不包括遮光導電圖案120而顯示裝置10A具有高開口率,搭配前述的驅動系統顯示裝置10A能在具有高開口率的前提下,改善垂直串音(vertical cross-talk)現象。The pixel PXA in FIG. 5 can be used to replace the pixel PX in FIG. 1 to form another
圖6A為本發明又一實施例之畫素PXB的電路示意圖。圖6B為本發明又一實施例之畫素PXB的佈局(layout)示意圖。圖6A及圖6B的畫素PXB與圖3的畫素PX類似,說明兩者的差異如下。6A is a schematic circuit diagram of a pixel PXB according to another embodiment of the invention. FIG. 6B is a schematic diagram of the layout of the pixel PXB according to another embodiment of the present invention. The pixel PXB in FIGS. 6A and 6B is similar to the pixel PX in FIG. 3, and the differences between the two are explained as follows.
請參照圖6A及圖6B,在本實施例中,每一畫素PXB包括掃描線SL、資料線DL、控制線CL、開關元件T及畫素電極130。開關元件T包括第一開關元件T1、第二開關元件T2、第三開關元件T3,而畫素電極130包括第一畫素電極131及第二畫素電極132。6A and 6B, in this embodiment, each pixel PXB includes a scan line SL, a data line DL, a control line CL, a switching element T, and a
第一開關元件T1包括控制端Tc、第一端Ta及第二端Tb。第一開關元件T1的第一端Ta電性連接至資料線DL。第一開關元件T1的控制端Tc電性連接至掃描線SL。第一畫素電極131電性連接至第一開關元件T1的第二端Tb。The first switching element T1 includes a control terminal Tc, a first terminal Ta, and a second terminal Tb. The first terminal Ta of the first switching element T1 is electrically connected to the data line DL. The control terminal Tc of the first switching element T1 is electrically connected to the scan line SL. The
第二開關元件T2具有第一端Ta、第二端Tb及控制端Tc。第二開關元件T2的第一端Ta電性連接至資料線DL。第二開關元件T2的控制端Tc電性連接至掃描線SL。第二開關元件T2的第二端Tb電性連接至第二畫素電極132。The second switching element T2 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the second switching element T2 is electrically connected to the data line DL. The control terminal Tc of the second switch element T2 is electrically connected to the scan line SL. The second terminal Tb of the second switching element T2 is electrically connected to the
第三開關元件T3具有第一端Ta、第二端Tb及控制端Tc。第三開關元件T3的第一端Ta電性連接至第二開關元件T2的第二端Tb。第三開關元件T3的控制端Tc電性連接至控制線CL。在本實施例中,控制線CL可在第二方向d2上延伸,控制線CL與掃描線SL大致上可平行設置,但本發明不以此為限。The third switching element T3 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the third switching element T3 is electrically connected to the second terminal Tb of the second switching element T2. The control terminal Tc of the third switch element T3 is electrically connected to the control line CL. In this embodiment, the control line CL can extend in the second direction d2, and the control line CL and the scan line SL can be arranged substantially in parallel, but the invention is not limited to this.
在本實施例中,畫素PXB更包括遮光電極140。遮光電極140包括第一遮光電極141及第二遮光電極142。第一遮光電極141與第一畫素電極131的第一主幹部130a及第二主幹部130b重疊。第二遮光電極142與第二畫素電極132的第一主幹部130a及第二主幹部130b重疊。In this embodiment, the pixel PXB further includes a
第二遮光電極142與第二畫素電極132重疊,而形成一充電更新電容器Cx。第三開關元件T3的第二端Tb電性連接至所述充電更新電容器Cx的一電極(即第二遮光電極142)。The second light-shielding
舉例而言,在本實施例中,畫素PXB更包括一連接圖案150,其中連接圖案150與畫素電極130可形成於同一膜層,而第三開關元件T3的第二端Tb可透過連接圖案150電性連接至第二遮光電極142,但本發明不以此為限。For example, in this embodiment, the pixel PXB further includes a
在本實施例中,畫素PXB包括遮光導電圖案120。遮光導電圖案120設置於畫素PX的資料線DL與畫素PX的第一畫素電極131之間。也就是說,遮光導電圖案120於基板110上之垂直投影的至少一部分位於資料線DL於基板110上的垂直投影與第一畫素電極131於基板110上的垂直投影之間。In this embodiment, the pixel PXB includes a light-shielding
多個畫素PXB包括在第二方向d2上排列且相鄰的畫素PX1及畫素PX2。舉例而言,在本實施例中,遮光導電圖案120可包括第一遮光導電部120a及第二遮光導電部120b,第一遮光導電部120a設置於同一畫素PX1的資料線DL與第一畫素電極131之間,第二遮光導電部120b設置於一畫素PX1的第一畫素電極131與另一畫素PX2的資料線DL之間。The plurality of pixels PXB includes pixels PX1 and PX2 that are arranged in the second direction d2 and are adjacent to each other. For example, in this embodiment, the light-shielding
畫素PXB可用以取代圖1的畫素PX,而形成另一顯示裝置10B。包括多個畫素PXB的顯示裝置10B也可用前述的驅動系統驅動之。搭配前述的驅動系統,包括多個畫素PXB的顯示裝置10B也能改善垂直串音現象。The pixel PXB can be used to replace the pixel PX in FIG. 1 to form another
圖7為本發明再一實施例之畫素PXC的佈局(layout)示意圖。圖7的畫素PXC與圖6A及圖6B的畫素PXB類似,兩者的差異在於:圖7的畫素PXC不包括圖6A及圖6B之畫素PXB的遮光導電圖案120。也就是說,在圖7的實施例中,資料線DL與第一畫素電極131之間無設置在第一方向d1上延伸的任何遮光導電圖案。FIG. 7 is a schematic diagram of the layout of pixel PXC according to another embodiment of the present invention. The pixel PXC in FIG. 7 is similar to the pixel PXB in FIGS. 6A and 6B. The difference between the two is that the pixel PXC in FIG. 7 does not include the light-shielding
圖7的畫素PXC可用以取代圖1的畫素PX,而形成另一顯示裝置10C。包括多個畫素PXC的顯示裝置10C也可用前述的驅動系統驅動之。特別是,畫素PXC不包括遮光導電圖案120而顯示裝置10C具有高開口率,搭配前述的驅動系統顯示裝置10C能在具有高開口率的前提下,改善垂直串音現象。The pixel PXC of FIG. 7 can be used to replace the pixel PX of FIG. 1 to form another
圖8為本發明一實施例之畫素PXD的電路示意圖。圖8的畫素PXD與圖3的畫素PX類似,說明兩者的差異如下。FIG. 8 is a schematic circuit diagram of a pixel PXD according to an embodiment of the invention. The pixel PXD in FIG. 8 is similar to the pixel PX in FIG. 3, and the differences between the two are explained as follows.
請參照圖8,在本實施例中,每一畫素PXD包括掃描線SL、資料線DL、共用線TL、開關元件T及畫素電極130。開關元件T包括第一開關元件T1、第二開關元件T2、第三開關元件T3,而畫素電極130包括第一畫素電極131及第二畫素電極132。Referring to FIG. 8, in this embodiment, each pixel PXD includes a scan line SL, a data line DL, a common line TL, a switching element T, and a
第一開關元件T1包括控制端Tc、第一端Ta及第二端Tb。第一開關元件T1的第一端Ta電性連接至資料線DL。第一開關元件T1的控制端Tc電性連接至掃描線SL。第一畫素電極131電性連接至第一開關元件T1的第二端Tb。The first switching element T1 includes a control terminal Tc, a first terminal Ta, and a second terminal Tb. The first terminal Ta of the first switching element T1 is electrically connected to the data line DL. The control terminal Tc of the first switching element T1 is electrically connected to the scan line SL. The
第二開關元件T2具有第一端Ta、第二端Tb及控制端Tc。第二開關元件T2的第一端Ta電性連接至資料線DL。第二開關元件T2的控制端Tc電性連接至掃描線SL。第二開關元件T2的第二端Tb電性連接至第二畫素電極132。The second switching element T2 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the second switching element T2 is electrically connected to the data line DL. The control terminal Tc of the second switch element T2 is electrically connected to the scan line SL. The second terminal Tb of the second switching element T2 is electrically connected to the
第三開關元件T3具有第一端Ta、第二端Tb及控制端Tc。第三開關元件T3的第一端Ta電性連接至第二開關元件T2的第二端Tb。第三開關元件T3的控制端Tc電性連接至掃描線SL。第三開關元件T3的第二端Tb電性連接至共用線TL。The third switching element T3 has a first terminal Ta, a second terminal Tb, and a control terminal Tc. The first terminal Ta of the third switching element T3 is electrically connected to the second terminal Tb of the second switching element T2. The control terminal Tc of the third switch element T3 is electrically connected to the scan line SL. The second terminal Tb of the third switching element T3 is electrically connected to the common line TL.
在本實施例中,於實際的佈局(layout)上,畫素PXD包括遮光導電圖案(未繪示)。遮光導電圖案設置於畫素PXD的資料線DL與畫素PXD的第一畫素電極131之間。也就是說,遮光導電圖案於基板(未繪示)上之垂直投影的至少一部分位於資料線DL於基板上的垂直投影與第一畫素電極131於基板上的垂直投影之間。In this embodiment, on the actual layout, the pixel PXD includes a light-shielding conductive pattern (not shown). The light-shielding conductive pattern is disposed between the data line DL of the pixel PXD and the
多個畫素PXD包括在第二方向d2上排列且相鄰的畫素PX1及畫素PX2。舉例而言,在本實施例中,於實際的佈局上,遮光導電圖案(未繪示)可包括第一遮光導電部(未繪示)及第二遮光導電部(未繪示),第一遮光導電部設置於同一畫素PX1的資料線DL與第一畫素電極131之間,第二遮光導電部設置於一畫素PX1的第一畫素電極131與另一畫素PX2的資料線DL之間。The plurality of pixels PXD includes pixels PX1 and PX2 that are arranged in the second direction d2 and are adjacent to each other. For example, in this embodiment, in the actual layout, the light-shielding conductive pattern (not shown) may include a first light-shielding conductive portion (not shown) and a second light-shielding conductive portion (not shown), the first The light-shielding conductive part is arranged between the data line DL of the same pixel PX1 and the
圖8的畫素PXD可用以取代圖1的畫素PX,而形成另一顯示裝置10D。包括多個畫素PXD的顯示裝置10D也可用前述的驅動系統驅動之。搭配前述的驅動系統,包括多個畫素PXD的顯示裝置10D也能改善垂直串音現象。The pixel PXD of FIG. 8 can be used to replace the pixel PX of FIG. 1 to form another
圖9為本發明另一實施例之畫素PXE的電路示意圖。圖9的畫素PXE與圖8的畫素PXD類似,兩者的差異在於:圖9的畫素PXE不包括圖8之畫素PXD的遮光導電圖案。也就是說,在圖9的實施例中,資料線DL與第一畫素電極131之間無設置在第一方向d1上延伸的任何遮光導電圖案。FIG. 9 is a circuit diagram of a pixel PXE according to another embodiment of the invention. The pixel PXE in FIG. 9 is similar to the pixel PXD in FIG. 8. The difference between the two is that the pixel PXE in FIG. 9 does not include the light-shielding conductive pattern of the pixel PXD in FIG. 8. That is, in the embodiment of FIG. 9, there is no light-shielding conductive pattern extending in the first direction d1 between the data line DL and the
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
1:畫素陣列基板 2:對向基板 3:顯示介質 4:時序控制電路 5:閘極驅動電路 6:資料驅動電路 10、10A、10B、10C、10D、10E:顯示裝置 110、210:基板 120:遮光導電圖案 120a、120b:遮光導電部 130、131、132:畫素電極 130a、130b:主幹部 130c:分支部 140、141、142:遮光電極 150:連接圖案 220:彩色濾光層 230:擋光圖案 232:開口 240:共用電極 A-A’、B-B’:剖線 CL:控制線 Cx:充電更新電容器 DL:資料線 d1:第一方向 d2:第二方向 GI:閘絕緣層 PX、PXA、PXB、PXC、PXD、PXE:畫素 R1、R2:畫素行 SL、SL1~SL7:掃描線 TL:共用線 T、T1、T2、T3:開關元件 Ta:第一端 Tb:第二端 Tc:控制端 Td:半導體圖案 t:圖框區間 t1、t2:子圖框區間 Vdl1:第一資料訊號 Vdl2:第二資料訊號 Vg1、Vg3、Vg5、Vg7:第一閘極脈衝訊號 Vg2、Vg4、Vg6:第二閘極脈衝訊號 Vpol:極性訊號 Vpx:畫素電極的訊號 Vst1:第一啟始訊號 Vst2:第二啟始訊號 、 :電壓差 W1、W2:致能時間寬度 1: Pixel array substrate 2: Counter substrate 3: Display medium 4: Timing control circuit 5: Gate drive circuit 6: Data drive circuit 10, 10A, 10B, 10C, 10D, 10E: Display device 110, 210: Substrate 120: Light-shielding conductive patterns 120a, 120b: Light-shielding conductive parts 130, 131, 132: Pixel electrodes 130a, 130b: Main part 130c: Branch parts 140, 141, 142: Light-shielding electrode 150: Connection pattern 220: Color filter layer 230 : Light blocking pattern 232: Opening 240: Common electrode A-A', B-B': Section line CL: Control line Cx: Charge update capacitor DL: Data line d1: First direction d2: Second direction GI: Gate insulation Layers PX, PXA, PXB, PXC, PXD, PXE: pixels R1, R2: pixel rows SL, SL1 to SL7: scanning lines TL: common lines T, T1, T2, T3: switching element Ta: first end Tb: Second terminal Tc: control terminal Td: semiconductor pattern t: frame interval t1, t2: sub-frame interval Vdl1: first data signal Vdl2: second data signal Vg1, Vg3, Vg5, Vg7: first gate pulse signal Vg2, Vg4, Vg6: second gate pulse signal Vpol: polarity signal Vpx: pixel electrode signal Vst1: first start signal Vst2: second start signal , :Voltage difference W1, W2: Enable time width
圖1為本發明一實施例之顯示裝置的示意圖。 圖2示出本發明一實施例之第一閘極脈衝訊號Vg1、Vg3、Vg5、Vg7、第二閘極脈衝訊號Vg2、Vg4、Vg6、極性訊號Vpol、第一啟始訊號Vst1、第二啟始訊號Vst2、第一資料訊號Vdl1、第二資料訊號Vdl2及畫素電極的訊號Vpx。 圖3為本發明一實施例之畫素PX的佈局(layout)示意圖。 圖4為本發明一實施例之顯示裝置的剖面示意圖。 圖5為本發明另一實施例之畫素PXA的佈局示意圖。 圖6A為本發明又一實施例之畫素PXB的電路示意圖。 圖6B為本發明又一實施例之畫素PXB的佈局(layout)示意圖。 圖7為本發明再一實施例之畫素PXC的佈局示意圖。 圖8為本發明一實施例之畫素PXD的電路示意圖。 圖9為本發明另一實施例之畫素PXE的電路示意圖。 FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention. FIG. 2 shows the first gate pulse signals Vg1, Vg3, Vg5, Vg7, the second gate pulse signals Vg2, Vg4, Vg6, the polarity signal Vpol, the first start signal Vst1, the second start signal according to an embodiment of the present invention. The start signal Vst2, the first data signal Vdl1, the second data signal Vdl2, and the pixel electrode signal Vpx. FIG. 3 is a schematic diagram of the layout of the pixel PX according to an embodiment of the present invention. 4 is a schematic cross-sectional view of a display device according to an embodiment of the invention. FIG. 5 is a schematic diagram of the layout of pixel PXA according to another embodiment of the present invention. 6A is a schematic circuit diagram of a pixel PXB according to another embodiment of the invention. FIG. 6B is a schematic diagram of the layout of the pixel PXB according to another embodiment of the present invention. FIG. 7 is a schematic diagram of the layout of pixel PXC according to still another embodiment of the present invention. FIG. 8 is a schematic circuit diagram of a pixel PXD according to an embodiment of the invention. FIG. 9 is a circuit diagram of a pixel PXE according to another embodiment of the invention.
4:時序控制電路
5:閘極驅動電路
6:資料驅動電路
10、10A、10B、10C、10D、10E:顯示裝置
DL:資料線
d1:第一方向
d2:第二方向
PX、PXA、PXB、PXC、PXD、PXE:畫素
R1、R2:畫素行
SL、SL1~SL7:掃描線
4: Timing control circuit
5: Gate drive circuit
6: Data drive
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