WO2018054137A1

WO2018054137A1 - Pixel array, display panel, display device

Info

Publication number: WO2018054137A1
Application number: PCT/CN2017/092778
Authority: WO
Inventors: 高玉杰
Original assignee: 京东方科技集团股份有限公司; 北京京东方显示技术有限公司
Priority date: 2016-09-23
Filing date: 2017-07-13
Publication date: 2018-03-29
Also published as: CN106292110A; US20190004383A1; US10571768B2

Abstract

A pixel array, a display panel and a display device. The pixel array comprises a plurality of pixel units (20), data lines (23) and gate lines (24) arranged in an array, each pixel unit (20) comprises four sub-pixel units (R, G, B, W); a first sub-pixel unit group (21) comprises two adjacent sub-pixel units (R, G), a second sub-pixel unit group (22) comprises the remaining two adjacent sub-pixel units (B, W); the first sub-pixel unit group (21) and the second sub-pixel unit group (22) are alternately arranged in the row direction and in the column direction; the data line (Data1) connected to the two sub-pixel units (R, G) comprised in the first sub-pixel unit group (21) is different from the data line (Data2) connected to the two sub-pixel units (B, W) comprised in the second sub-pixel unit group (22). The pixel array ensures consistency among charge states of each pixel, so as to prevent the formation of horizontal fine lines.

Description

Pixel array, display panel, display device

Technical field

Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a pixel array, a display panel, and a display device.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD) is a commonly used flat panel display. The liquid crystal display panel is widely used in modern times due to its small size, low power consumption, no radiation, and high resolution. Digital information equipment. The prior art pixel array adopts a dual gate design, and the source driving signal received by each data line changes continuously. This causes the power consumption of the source driver circuit to rise and the temperature to rise. At the same time, when the source drive signal changes in height, there will be a certain delay, and the effective signal time will be reduced, so that the charging time of the pixel becomes shorter, resulting in a shorter charging time. The problem of insufficient pixel charging causes a horizontal thin line problem due to inconsistent charging states of odd-numbered rows of pixels.

Summary of the invention

Embodiments of the present disclosure provide a pixel array, a display panel, and a display device, which are configured to achieve uniform charging states for a monochrome image and prevent generation of horizontal thin lines.

An embodiment of the present disclosure provides a pixel array including a plurality of arrayed pixel units, a plurality of data lines connected to a source driving circuit, and a plurality of gate lines connected to the gate driving circuit, wherein each of the plurality of gate lines The pixel unit includes four sub-pixel units; in each of the pixel units, four sub-pixel units are divided into a first sub-pixel unit group and a second sub-pixel unit group, and the first sub-pixel unit group includes two phases. a neighboring sub-pixel unit, the second sub-pixel unit group including the remaining two adjacent sub-pixel units; the first sub-pixel unit group and the second sub-pixel unit group in a row direction and a column direction Alternatingly, the first sub-pixel unit group and the second sub-pixel unit group are each connected to a data line extending in a column direction; the first sub-pixel unit group includes two sub-pixel units connected to the same data a second sub-pixel unit group includes two sub-pixel units connected to the same data line, and the first sub-pixel unit group includes two sub-pixel unit connected data lines and the second Different data line connected to two sub-pixel units includes pixel cell group; and the The two sub-pixel units included in the first sub-pixel unit group are respectively connected to different gate lines, and the two sub-pixel units included in the second sub-pixel unit group are respectively connected to different gate lines.

In one example, the gate line includes a first gate line and a second gate line, and the first gate line and the second gate line are both disposed between adjacent two rows of sub-pixel units;

Two sub-pixel units in the first sub-pixel unit group are respectively connected to the first gate line and the second gate line, and two sub-pixel units in the second sub-pixel unit group are respectively connected to the first gate The pole line is connected to the second gate line.

In one example, the gate line includes a first gate line and a second gate line, and the first gate line and the second gate line are respectively located on opposite sides of each row of sub-pixel units;

In one example, among the two first sub-pixel unit groups adjacent in the row direction, one of the first sub-pixel unit groups includes a first sub-pixel unit connected to the first gate line, The second sub-pixel unit is connected to the second gate line; the first sub-pixel unit of the first sub-pixel unit group is connected to the second gate line, including the second One sub-pixel unit is connected to the first gate line; and, among the two second sub-pixel unit groups adjacent in the row direction, one of the second sub-pixel unit groups includes a first sub- a pixel unit is connected to the first gate line, and a second sub-pixel unit is included to be connected to the second gate line; and another second sub-pixel unit group includes a first sub-pixel unit and a The second gate line connection includes a second sub-pixel unit connected to the first gate line.

In one example, the first sub-pixel unit group includes a red sub-pixel unit and a green sub-pixel unit, the second sub-pixel unit group includes a blue sub-pixel unit and a white sub-pixel unit; and the first gate is connected The number of red sub-pixel units of the line is equal to the number of red sub-pixel units connected to the second gate line; the number of green sub-pixel units connected to the first gate line is connected to the second The number of green sub-pixel units of the gate line is equal; the number of blue sub-pixel units connected to the first gate line is equal to the number of blue sub-pixel units connected to the second gate line; The number of white sub-pixel units connected to the first gate line is equal to the number of white sub-pixel units connected to the second gate line.

In one example, the first sub-pixel unit group is connected to an odd-numbered column data line, the second sub- The pixel unit group is connected to the even column data line.

In one example, the first sub-pixel cell group is coupled to an even column data line, and the second sub-pixel cell group is coupled to an odd column data line.

In one example, each of the pixel units includes a red sub-pixel unit, a green sub-pixel unit, a blue sub-pixel unit, and a white sub-pixel unit; or each of the pixel units includes a red sub-pixel unit, a green sub-pixel unit, Blue sub-pixel unit and yellow sub-pixel unit.

In one example, the first sub-pixel unit group includes a red sub-pixel unit and a green sub-pixel unit, and the second sub-pixel unit group includes a blue sub-pixel unit and a white sub-pixel unit.

In one example, the first sub-pixel unit group includes a red sub-pixel unit and a green sub-pixel unit, and the second sub-pixel unit group includes a blue sub-pixel unit and a yellow sub-pixel unit.

Embodiments of the present disclosure also provide a display panel including the above-described pixel array.

Embodiments of the present disclosure also provide a display device including the above display panel.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present disclosure, and are not to limit the disclosure. .

1 is a schematic structural view of a current pixel array;

FIG. 2 is a schematic structural diagram of a pixel array according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of another pixel array according to an embodiment of the present disclosure.

Detailed ways

The technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It is apparent that the described embodiments are part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present disclosure without departing from the scope of the invention are within the scope of the disclosure.

Unless otherwise defined, technical terms or scientific terms used herein shall be taken to mean the ordinary meaning of the ordinary skill in the art to which the invention pertains. The words "first", "second" and similar words used in the specification and claims of the disclosure do not denote any order, Quantity or importance, but only to distinguish between different components. The words "including" or "comprising" or "comprises" or "comprises" or "an" Component or object. The words "connected" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.

FIG. 1 is a pixel array having a dual gate structure. As shown, each pixel unit includes four sub-pixel units of red (R), green (G), blue (B), and white (W), and each gate connected to the gate driving circuit (Gate). The line is connected to the gate of the TFT, and each of the data lines connected to the source driving circuit is connected to the source of the TFT. At the same time, the gate of a row of TFTs is turned on during screen display.

The pixel array of FIG. 1 can adopt 2dot-inversion: under the Y-th frame image, the data polarity of each adjacent two data lines is opposite; the data of the same data line under the Y+1 frame image is The polarity of the Y frame image is opposite, and the polarity of the data on each adjacent two data lines is opposite. The polarity of the source driving signal received by each data line alternates positively and negatively, and the same data line is adjacent. The positive and negative polarities of the two frames of images at the same time are opposite, thereby achieving the purpose of preventing aging of the liquid crystal, wherein Y is an integer greater than or equal to 1.

As shown in FIG. 2 and FIG. 3, an embodiment of the present disclosure provides a pixel array including a plurality of arrayed pixel units 20 and a plurality of data lines 23 connected to a source driving circuit, such as: Data1, Data2, and Data3. , Data4, Data5, Data6, etc., and a plurality of gate lines 24 connected to the gate driving circuit, such as: Gate1, Gate2, Gate3, Gate4, Gate5, Gate6, Gate7, Gate8, etc., wherein each pixel unit 20 includes Four sub-pixel units.

In each pixel unit 20, four sub-pixel units are divided into a first sub-pixel unit group 21 and a second sub-pixel unit group 22, and the first sub-pixel unit group 21 includes two adjacent sub-pixel units, and the second sub-pixel Cell group 22 includes the remaining two adjacent sub-pixel cells.

The first sub-pixel unit group 21 and the second sub-pixel unit group 22 are alternately arranged in the row direction and the column direction, and the first sub-pixel unit group 21 and the second sub-pixel unit group 22 are each connected to a strip. A data line extending in the column direction.

As shown in FIG. 2, the two sub-pixel units 21 of the first sub-pixel unit group 21 are connected to the same data line Data1, and the two sub-pixel units of the second sub-pixel unit group 22 are connected to the same data line Data2. The data line Data1 connected by the two sub-pixel units included in one sub-pixel unit group 21 is different from the data line Data2 connected to the two sub-pixel units included in the second sub-pixel unit group 22.

The two sub-pixel units of the first sub-pixel unit group 21 are respectively connected to different gate lines 24, and the two sub-pixel units of the second sub-pixel unit group 22 are respectively connected to different gate lines 24. For example, as shown in FIG. 2, the two sub-pixel units 21 of the first sub-pixel unit group 21 are respectively connected to the gate lines Gate1 and Gate2; the second sub-pixel unit group 22 includes two sub-pixel units and a gate respectively. Line Gate1 is connected to Gate2.

For example, each pixel unit 20 includes a red (R) sub-pixel unit, a green (G) sub-pixel unit, a blue (B) sub-pixel unit, and a white (W) sub-pixel unit; or, in a specific embodiment of the present disclosure Each pixel unit 20 includes an R sub-pixel unit, a G sub-pixel unit, a B sub-pixel unit, and a yellow (Y) sub-pixel unit. The embodiment of the present disclosure is exemplified by the fact that each pixel unit 20 includes an R sub-pixel unit, a G sub-pixel unit, a B sub-pixel unit, and a W sub-pixel unit. As shown in FIG. 2 and FIG. 3, the transmittance of the RGBW product is compared. High, can reduce backlight costs.

In at least some embodiments, as shown in FIG. 2 and FIG. 3, in the embodiment of the present disclosure, the first sub-pixel unit group 21 includes an R sub-pixel unit and a G sub-pixel unit, and the second sub-pixel unit group 22 includes a B sub-pixel unit. And a W sub-pixel unit; or, in the embodiment of the present disclosure, the first sub-pixel unit group 21 includes an R sub-pixel unit and a G sub-pixel unit, and the second sub-pixel unit group 22 includes a B sub-pixel unit and a Y sub-pixel unit.

In at least some embodiments, as shown in FIG. 2 and FIG. 3, the first sub-pixel unit group 21 of the embodiment of the present disclosure is connected to the odd-numbered column data lines, such as the first sub-pixel unit group 21 and the first embodiment of the present disclosure. The column data line Data1, the third column data line Data3, and the fifth column data line Data5 are connected, and the second sub-pixel unit group 22 is connected to the even-numbered column data lines, such as the second sub-pixel unit group 22 and the second embodiment of the present disclosure. The two columns of data lines Data2, the fourth column data line Data4, and the sixth column data line Data6 are connected. Of course, in a specific design, the first sub-pixel unit group 21 in the embodiment of the present disclosure may also be connected to the even-numbered column data lines, and the second sub-pixel unit group 22 is connected to the odd-numbered column data lines.

When the 2dot-inversion is implemented in the embodiment of the present disclosure, the polarity of the source driving signals received by the adjacent two data lines 23 is opposite for the same frame image, and the same data line 23 is connected to the adjacent two frames of images. The received source drive signals have the same polarity. Compared with the prior art, the polarity of the source driving signal received by each data line in the embodiment of the present disclosure does not need to be alternately positive and negative, that is, the source driving signal is stable, and high and low, high and low constant changes are not required. Therefore, the problem that the power consumption of the source driving circuit is increased and the temperature is increased can be avoided. In addition, since the source driving signal in the embodiment of the present disclosure does not require alternating positive and negative changes, the charging state of each pixel can be realized for a monochrome picture. Consistent, prevent the generation of horizontal thin lines.

Two different wiring examples of the gate lines of the dual gate design in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

As shown in FIG. 2, the gate line 24 in the embodiment of the present disclosure includes a first gate line and a second gate line. In the embodiment of the present disclosure, the gate lines of the odd rows are used as the first gate line, such as: Gate1. , Gate3, Gate5, Gate7, etc. are the first gate lines, and the gate lines of the even rows are used as the second gate lines, such as: Gate2, Gate4, Gate6, Gate8, etc. as the second gate line, the first gate line And the second gate line is respectively located on the opposite side of each row of the sub-pixel unit; the two sub-pixel units in the first sub-pixel unit group 21 in the embodiment of the present disclosure are respectively connected to the first gate line and the second gate line Connected, two sub-pixel units in the second sub-pixel unit group 22 are respectively connected to the first gate line and the second gate line.

For example, in the embodiment of the present disclosure, among the two first sub-pixel unit groups 21 adjacent in the row direction, the first sub-pixel unit included in one of the first sub-pixel unit groups 21 is connected to the first gate line, including The second sub-pixel unit is connected to the second gate line; the other first sub-pixel unit group 21 includes a first sub-pixel unit connected to the second gate line, including the second sub-pixel unit and the a gate line connection; for example, in the first first sub-pixel unit group 21 adjacent to the first row, the first sub-pixel unit group 21 in the first column includes the R sub-pixel unit and the first gate line Gate1 is connected, the G sub-pixel unit is connected to the second gate line Gate2; the R sub-pixel unit included in the first sub-pixel unit group 21 of the third column is connected to the second gate line Gate2, and the G sub-pixel unit is first The gate line Gate1 is connected, so that in the specific wiring design of the pixel array, it is possible to ensure that the resistance value of the entire pixel array wiring is not different, and the power consumption of the pixel array partial region due to the inconsistency of the wiring length is not generated. Large resulting pixel array Often the problem.

For example, in the two second sub-pixel unit groups 22 adjacent in the row direction, one of the second sub-pixel unit groups 22 includes a first sub-pixel unit connected to the first gate line, including the second sub- The pixel unit is connected to the second gate line; the second sub-pixel unit group 22 includes a first sub-pixel unit connected to the second gate line, and the second sub-pixel unit included is connected to the first gate line ;Such as: In the two second sub-pixel unit groups 22 adjacent to the first row, the B sub-pixel units included in the second sub-pixel unit group 22 of the second column are connected to the first gate line Gate1, and the W sub-pixel unit is The second gate line Gate2 is connected; the B sub-pixel unit 22 included in the fourth sub-pixel unit group 22 is connected to the second gate line Gate2, and the W sub-pixel unit is connected to the first gate line Gate1. In the specific wiring design of the pixel array, the resistance value of the entire pixel array wiring can be well ensured, and the power consumption of the pixel array at the wiring position can be well ensured, and the performance of the pixel array can be improved.

In at least some embodiments, as shown in FIG. 2, in all the R sub-pixel units of the embodiment of the present disclosure, the number of R sub-pixel units connected to the first gate line and the R sub-connected to the second gate line The number of pixel units is equal; among all G sub-pixel units, the number of G sub-pixel units connected to the first gate line is equal to the number of G sub-pixel units connected to the second gate line; all B sub- In the pixel unit, the number of B sub-pixel units connected to the first gate line is equal to the number of B sub-pixel units connected to the second gate line; among all the W sub-pixel units, connected to the first gate The number of W sub-pixel units of the line is equal to the number of W sub-pixel units connected to the second gate line.

As shown in FIG. 3, the gate line 24 in the embodiment of the present disclosure includes a first gate line and a second gate line. The embodiment of the present disclosure uses odd-numbered rows of gate lines as the first gate line, such as: Gate1. , Gate3, Gate5, Gate7, etc. are the first gate lines, and the gate lines of the even rows are used as the second gate lines, such as: Gate2, Gate4, Gate6, Gate8, etc. as the second gate line, the first gate line And the second gate line is disposed between adjacent two rows of sub-pixel units. Two sub-pixel units in the first sub-pixel unit group 21 in the embodiment of the present disclosure are respectively connected to the first gate line and the second gate line, and two sub-pixel units in the second sub-pixel unit group 22 are respectively Connected to the first gate line and the second gate line.

Gate1 of Figure 2 is placed above the first row of sub-pixels, and there is only one Gate1, Gate1 in Figure 3 is placed between the first and second rows of sub-pixel units, and no gate is placed above the first row of sub-pixels. line.

The embodiment of the present disclosure further provides a display panel, which includes the above pixel array provided by an embodiment of the present disclosure. The pixel array of the above embodiment can be applied to, for example, an array substrate, a color filter substrate, or a COA substrate.

The embodiment of the present disclosure further provides a display device, which is provided by the embodiment of the present disclosure. The display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, or an organic light emitting diode (OLED). ) panel, OLED display Display device such as OLED TV or electronic paper.

The above description is only an exemplary embodiment of the present disclosure, and is not intended to limit the scope of the disclosure. The scope of the disclosure is determined by the appended claims.

The present application is based on and claims the priority of the Chinese Patent Application No. 201610849268.1 filed on Sep. 23, 2016, the entire disclosure of which is hereby incorporated by reference.

Claims

A pixel array comprising: a plurality of pixel units arranged in an array, a plurality of data lines, and a plurality of gate lines, wherein each of the pixel units comprises four sub-pixel units;

In each of the pixel units, four sub-pixel units are divided into a first sub-pixel unit group and a second sub-pixel unit group, the first sub-pixel unit group includes two adjacent sub-pixel units, and the second The sub-pixel unit group includes the remaining two adjacent sub-pixel units;

The first sub-pixel unit group and the second sub-pixel unit group are alternately arranged in a row direction and a column direction, and the first sub-pixel unit group and the second sub-pixel unit group are each connected in a column direction. Extended data line;

The first sub-pixel unit group includes two sub-pixel units connected to the same data line, the second sub-pixel unit group includes two sub-pixel units connected to the same data line, and the first sub-pixel unit The data lines connected by the two sub-pixel units included in the group are different from the data lines connected to the two sub-pixel units included in the second sub-pixel unit group;

The two sub-pixel units included in the first sub-pixel unit group are respectively connected to different gate lines, and the two sub-pixel units included in the second sub-pixel unit group are respectively connected to different gate lines.
The pixel array according to claim 1, wherein the gate line comprises a first gate line and a second gate line, and the first gate line and the second gate line are both disposed adjacent to each other Between two rows of sub-pixel units;

Two sub-pixel units in the first sub-pixel unit group are respectively connected to the first gate line and the second gate line, and two sub-pixel units in the second sub-pixel unit group are respectively connected to the first gate The pole line is connected to the second gate line.
The pixel array according to claim 1, wherein the gate line comprises a first gate line and a second gate line, and the first gate line and the second gate line are respectively located in each row The opposite side of the pixel unit;

Two sub-pixel units in the first sub-pixel unit group are respectively connected to the first gate line and the second gate line, and two sub-pixel units in the second sub-pixel unit group are respectively connected to the first gate The pole line is connected to the second gate line.
The pixel array according to claim 2 or 3, wherein among the two first sub-pixel unit groups adjacent in the row direction, one of the first sub-pixel unit groups includes a first sub- a pixel unit is connected to the first gate line, and a second sub-pixel unit is included to be connected to the second gate line; and another first sub-pixel unit includes a first sub-pixel unit and a a second gate line connection, including a second sub-pixel unit connected to the first gate line;

In the two second sub-pixel unit groups adjacent in the row direction, one of the second sub-pixel unit groups includes a first sub-pixel unit connected to the first gate line, including a second Sub-pixel units are connected to the second gate line; another first sub-pixel unit group includes a first sub-pixel unit connected to the second gate line, including a second sub-pixel unit Connected to the first gate line.
The pixel array according to any one of claims 1 to 4, wherein the first sub-pixel unit group includes a red sub-pixel unit and a green sub-pixel unit, and the second sub-pixel unit group includes a blue sub-pixel unit And white sub-pixel units;

The number of red sub-pixel units connected to the first gate line is equal to the number of red sub-pixel units connected to the second gate line;

The number of green sub-pixel units connected to the first gate line is equal to the number of green sub-pixel units connected to the second gate line;

The number of blue sub-pixel units connected to the first gate line is equal to the number of blue sub-pixel units connected to the second gate line;

The number of white sub-pixel units connected to the first gate line is equal to the number of white sub-pixel units connected to the second gate line.
The pixel array according to any one of claims 1 to 5, wherein the first sub-pixel unit group is connected to an odd-numbered column data line, and the second sub-pixel unit group is connected to an even-numbered column data line.
The pixel array according to any one of claims 1 to 5, wherein the first sub-pixel unit group is connected to an even-numbered column data line, and the second sub-pixel unit group is connected to an odd-numbered column data line.
The pixel array according to any one of claims 1 to 7, wherein each of the pixel units comprises a red sub-pixel unit, a green sub-pixel unit, a blue sub-pixel unit, and a white sub-pixel unit; or

Each of the pixel units includes a red sub-pixel unit, a green sub-pixel unit, a blue sub-pixel unit, and a yellow sub-pixel unit.
The pixel array of claim 8, wherein the first sub-pixel unit group comprises a red sub-pixel unit and a green sub-pixel unit, and the second sub-pixel unit group comprises a blue sub-pixel Unit and white sub-pixel unit.
The pixel array of claim 8, wherein the first sub-pixel unit group comprises a red sub-pixel unit and a green sub-pixel unit, and the second sub-pixel unit group comprises a blue sub-pixel unit and a yellow sub-pixel unit .
A display panel comprising the pixel array of any one of claims 1 to 10.
A display device comprising the display panel of claim 11.