TWI703703B - Electrostatic discharge protection device - Google Patents

Abstract

An electrostatic discharge protection device includes a first well region, a second well region, a first doping region, and a first heavy doping region. The first and second well regions are disposed in a semiconductor substrate. The first doping region is disposed in the first and second well regions. The first heavy doping region is disposed in the first doping region in the first well region. The first well region and the first doping region have a first conductivity type, and the second well region and the first heavy doping region have a second conductivity type opposite to the first conductivity type.

Description

Electrostatic discharge protection device

The present invention relates to electrostatic discharge protection devices, and particularly to electrostatic discharge protection devices with low on-resistance.

Electrostatic discharge (ESD) has been one of the important reliability considerations in semiconductor products. There are two types of electrostatic discharge tests that are more familiar to ordinary people, human body model (HBM) and machine model (MM). Generally, commercial integrated circuits must have a certain degree of HBM and MM tolerance before they can be sold. Otherwise, integrated circuits are easily damaged by accidental electrostatic discharge events. Therefore, how to manufacture an efficient electrostatic discharge protection device/component to protect the integrated circuit is also a problem that the industry has been continuously discussing and researching.

Some embodiments of the present invention provide an electrostatic discharge protection device. The electrostatic discharge protection device includes a first well area and a second well area. The first well region and the second well region are arranged in the semiconductor substrate. The first well region has a first conductivity type, and the second well region has a second conductivity type, and the second conductivity type is opposite to the first conductivity type. The electrostatic discharge protection device includes a first doped region. The first doped region is arranged in the first well region and the second well region. The first doped region has a first conductivity type. The electrostatic discharge protection device includes a first heavily doped region. The first heavily doped region is arranged in the first doped region in the first well region. The first heavily doped region has the second conductivity type.

Some embodiments of the present invention provide an electrostatic discharge protection device. The electrostatic discharge protection device includes a first well region. The first well region is arranged in the semiconductor substrate. The electrostatic discharge protection device includes a first doped region. The first doped region has a first part arranged in the first well region and a second part arranged outside the first well region. The electrostatic discharge protection device includes a first heavily doped region. The first heavily doped region is arranged in the second part of the first doped region. The electrostatic discharge protection device includes a second heavily doped region. The second heavily doped region is arranged in the second well region. The first doped region has a first conductivity type, and the first well region, the first heavily doped region, and the second heavily doped region have a second conductivity type, and the second conductivity type is opposite to the first conductivity type.

The following disclosure provides many embodiments or examples for implementing different components of the provided electrostatic discharge protection device (ESD). Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numbers and/or letters in different examples. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

Some changes of the embodiment are described below. In the different drawings and illustrated embodiments, similar component symbols are used to identify similar components. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

An embodiment of the present invention provides an electrostatic discharge protection device, which includes a parasitic bipolar junction transistor (BJT) formed by a heavily doped region, a medium doped region, and a lightly doped well region . When an electrostatic discharge event occurs, the PN junction between the well area and the middle doped area collapses at a lower voltage to generate a reverse current, so that the static electricity is discharged through the two-carrier junction transistor of the electrostatic discharge protection device. It will not pass through the protected semiconductor device. Therefore, the electrostatic discharge protection device protects the semiconductor device from being damaged in an electrostatic discharge event.

FIG. 1A is a schematic cross-sectional view of the electrostatic discharge protection device 100 according to some embodiments of the present invention, and FIG. 1B is an equivalent circuit diagram of the electrostatic discharge protection device 100 in FIG. 1A.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a semiconductor substrate 102. According to some embodiments, the semiconductor substrate 102 includes a silicon (Si) substrate. According to some embodiments, the semiconductor substrate 102 includes elemental semiconductors, such as germanium (Ge); compound semiconductors, such as GaN, SiC, GaAs, GaP, InP, InAs, and/or InSb; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs , GaInAs, GaInP, and/or GaInAsP; or a combination of the foregoing.

According to some embodiments, the semiconductor substrate 102 is doped to have a first conductivity type or a second conductivity type opposite to the first conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In some embodiments, the semiconductor substrate 102 has the first conductivity type (eg, N-type), for example, it may be doped with phosphorus (P) or doped with arsenic (As). In some embodiments, the semiconductor substrate 102 has a second conductivity type (for example, P-type), for example, it may be doped with boron (B).

According to some embodiments, in addition to the ESD protection device 100, other semiconductor devices (not shown) are formed on the semiconductor substrate 102, such as active devices, passive devices (such as resistors or capacitors), or a combination of the foregoing, formed on the semiconductor substrate. On the base 102. In some embodiments, the active device includes a transistor, a metal oxide semiconductor field effect transistor (MOSFET), a metal insulator semiconductor field effect transistor (MISFET), and a junction field. Junction field effect transistor (JFET), insulated gate bipolar transistor (IGBT), or a combination of the foregoing. During an electrostatic discharge event, the electrostatic discharge protection device 100 protects these semiconductor devices.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a first well area 104 and a second well area 106. According to some embodiments, the first well region 104 and the second well region 106 are disposed in the semiconductor substrate 102 and extend downward from the upper surface of the semiconductor substrate 102. According to some embodiments, the first well area 104 is in contact with the second well area 106.

According to some embodiments, the first well region 104 and the second well region 106 have opposite conductivity types. According to some embodiments, the first well region 104 has a first conductivity type (eg, N-type), and the second well region has a second conductivity type (eg, P-type). In some embodiments, the first conductivity type is an N-type dopant, such as phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb) ions, or a combination of the foregoing. In some embodiments, the second conductivity type is a P-type dopant, such as boron (B), gallium (Ga), aluminum (Al), indium (In), or a combination of the foregoing. In some embodiments, the first well region 104 and the second well region 106 can be formed through respective ion implantation processes.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a first doped region 108. According to some embodiments, the first doped region 108 has a first portion 108A disposed in the first well region 104 and a second portion 108B disposed in the second well region 106. According to some embodiments, the boundary between the first well region 104 and the second well region 106 passes through the first doped region 108. According to some embodiments, the first doped region 108 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the first doped region 108 has a first conductivity type (eg, N-type). According to some embodiments, the doping concentration of the first doping region 108 is greater than the doping concentration of the first well region 104. According to some embodiments, the doping concentration of the first doping region 108 is greater than the doping concentration of the second well region 106. According to some embodiments, the first doped region 108 may be formed through an ion implantation process.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a second doped region 110. According to some embodiments, the second doped region 110 is disposed in the second well region 106. According to some embodiments, the second doped region 110 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the second doped region 110 has a second conductivity type (for example, P type). According to some embodiments, the doping concentration of the second doping region 110 is greater than the doping concentration of the second well region 106. In some embodiments, the second doped region 110 may be formed through an ion implantation process.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a first heavily doped region 132. According to some embodiments, the first heavily doped region 132 provides an ohmic contact with an interconnect structure (not shown, such as a contact) formed thereon. According to some embodiments, the first heavily doped region 132 is disposed in the first well region 104. According to some embodiments, a part of the first heavily doped region 132 is disposed in the first doped region 108. According to some embodiments, the first heavily doped region 132 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the first heavily doped region 132 has a first conductivity type (eg, N-type). According to some embodiments, the doping concentration of the first heavily doped region 132 is greater than the doping concentration of the first well region 104 and the doping concentration of the first doping region 108. According to some embodiments, the first heavily doped region 132 may be formed through an ion implantation process.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a second heavily doped region 134. According to some embodiments, the second heavily doped region 134 provides ohmic contact with interconnection structures (not shown, such as contacts) formed thereon. According to some embodiments, the second heavily doped region 134 is provided in the first portion 108A of the first doped region 108. According to some embodiments, all of the second heavily doped regions 134 are provided in the first portion 108A of the first doped regions 108. According to some embodiments, the first heavily doped region 132 is in contact with the second heavily doped region 134. According to some embodiments, the second heavily doped region 134 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the second heavily doped region 134 has a second conductivity type (eg, P-type). According to some embodiments, the doping concentration of the second heavily doped region 134 is greater than the doping concentration of the first doped region 108. According to some embodiments, the second heavily doped region 134 may be formed through an ion implantation process.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes a third heavily doped region 136. According to some embodiments, the third heavily doped region 136 provides ohmic contact with interconnection structures (not shown, such as contacts) formed thereon. According to some embodiments, the third heavily doped region 136 is disposed in the second well region 106 outside the first doped region 108. According to some embodiments, all the third heavily doped regions 136 are disposed in the second doped regions 110 in the second well region 106. According to some embodiments, the third heavily doped region 136 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the third heavily doped region 136 has the second conductivity type (for example, P type). According to some embodiments, the doping concentration of the third heavily doped region 136 is greater than the doping concentration of the second doped region 110. According to some embodiments, the third heavily doped region 136 may be formed through an ion implantation process.

According to some embodiments, as shown in FIG. 1A, the electrostatic discharge protection device 100 includes an isolation member 121 and an isolation member 123. According to some embodiments, the isolation feature 121 and the isolation feature 123 extend downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the isolation members 121 and 123 define the area where the electrostatic discharge protection device 100 is formed in the semiconductor substrate 102. According to some embodiments, the isolation member 121 is disposed on the side of the first well region 104 away from the second well region 106, and the isolation member 123 is disposed on the side of the second well region 106 away from the first well region 104.

In some embodiments, the isolation features 121 and 123 include field oxide (FOX), local oxide of silicon (LOCOS), or shallow trench isolation (STI) structures. In some embodiments, the isolation members 121 and 123 are formed of silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination of the foregoing. In some embodiments, the isolation members 121 and 123 are formed through a thermal oxidation process. In some embodiments, the isolation features 121 and 123 are formed through an etching process and a deposition process.

According to some embodiments, as shown in FIG. 1A, the first heavily doped region 132 and the second heavily doped region 134 are electrically connected to the power supply line (VDD), and the third heavily doped region 136 is electrically connected to Ground wire (VSS). According to some embodiments, the power supply line (VDD) and the ground line (VSS) provide high potential and low current respectively in the semiconductor device protected by the electrostatic discharge protection device 100.

In some embodiments, by forming an interconnect structure on the semiconductor substrate 102, the first heavily doped region 132 and the second heavily doped region 134 are electrically connected to the power supply line (VDD), and the third heavily doped region The miscellaneous region 136 is electrically connected to the ground line (VSS). In some embodiments, the interconnect structure includes contacts that contact the first heavily doped region 132, the second heavily doped region 134, and the triple doped region 136, respectively. In some embodiments, the interconnect structure further includes wires and vias formed on the contacts.

According to some embodiments, as shown in FIGS. 1A and 1B, there is a PN junction between the second heavily doped region 134 and the first doped region 108, and between the second well region 106 and the first doped region 108 There is a PN junction. Therefore, the second heavily doped region 134, the first doped region 108, and the second well region 106 form a parasitic bipolar junction transistor (BJT). According to some embodiments, the two-carrier junction transistor is a PNP two-carrier junction transistor. According to some embodiments, the third heavily doped region 136 is the collector C of the two-carrier junction transistor, and the first doped region 108 is the base B of the two-carrier junction transistor. And the second heavily doped region 134 is the emitter E of the two-carrier junction transistor.

According to some embodiments, the breakdown voltage of the PN junction between the second well region 106 and the first doped region 108 is lower than the operating voltage of the semiconductor device protected by the electrostatic discharge protection device 100. When an electrostatic discharge event occurs from the power supply line (VDD), because the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, the static electricity will flow from the power supply The line (VDD) is discharged to the ground line (VSS) through the dual carrier junction transistor of the electrostatic discharge protection device 100, and does not pass through the protected semiconductor device. Therefore, the electrostatic discharge protection device 100 protects the semiconductor device from being damaged in an electrostatic discharge event.

Furthermore, once the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage and a reverse current is generated, the emitter E (the second heavily doped region 134) and the base There will be a potential difference (V _EB ) between B (first doped region 108), and a large amount of emitter current (I _E ) will flow to collector C (third heavily doped region 136), thereby reducing electrostatic discharge protection The on-resistance (R _ON ) of the device 100. Therefore, the electrostatic discharge protection device 100 quickly discharges static electricity to the ground line (VSS).

Furthermore, according to some embodiments, the first doped region 108 and the third heavily doped region 136 are separated by a distance D1. If the distance D1 is too small, the breakdown voltage of the PN junction between the second well region 106 and the first doped region 108 will be low. If the distance D1 is too large, the on-resistance (R _ON ) of the electrostatic discharge protection device 100 will increase. According to some embodiments, the second heavily doped region 134 disposed in the first well region 104 is separated from the edge of the first well region 104 by a distance D2.

Furthermore, according to some embodiments, by forming the second doped region 110 in the second well region 106, the on-resistance (R _ON ) of the ESD protection device 100 is further reduced, thereby discharging static electricity to the ground line ( VSS).

Fig. 2A is a schematic cross-sectional view of an ESD protection device 200 according to some embodiments of the present invention, and Fig. 2B is an equivalent circuit diagram of the ESD protection device 200 in Fig. 2A, which is the same as that of Figs. 1A and 1B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 2A and 2B and the embodiment shown in FIGS. 1A and 1B is that the electrostatic discharge protection device 200 includes an isolation member 122.

According to some embodiments, the isolation member 122 is provided in the first well region 104. According to some embodiments, the isolation feature 122 is disposed between the first heavily doped region 132 and the second heavily doped region 134. According to some embodiments, the isolation member 122 extends downward from the upper surface of the semiconductor substrate 102. According to some embodiments, the first heavily doped region 132 is disposed in the first well region 104 outside the first doped region 108A. In some embodiments, the material and forming method of the isolation member 122 may be the same as or similar to the isolation members 121 and 123 in FIG. 1A.

According to some embodiments, as shown in FIGS. 2A and 2B, by forming the isolation feature 122, the first well region 104 provides a resistance R1 between the first heavily doped region 132 and the first doped region 108 (base B) . According to some embodiments, the resistance R1 is adjusted by changing the size D3 of the isolation member 122. For example, the larger the size D3, the larger the resistance R1, and vice versa. If the dimension D3 is too small, the resistance R1 does not increase significantly. If D3 is too large, the layout density of the semiconductor devices on the semiconductor substrate 102 is reduced.

According to some embodiments, once the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, the emitter E (the second heavily doped region 134) and There will be a potential difference (V _EB ) between the base B (first doped region 108). If the resistance R1 of the first well region 104 is larger, the potential difference (V _EB ) between the emitter E and the base B is larger, which further increases the emitter current (I _E ). Therefore, forming the isolation member 122 further reduces the on-resistance (R _ON ) of the electrostatic discharge protection device 200, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 3A is a schematic cross-sectional view of an ESD protection device 300 according to some embodiments of the present invention, and Fig. 3B is an equivalent circuit diagram of the ESD protection device 300 in Fig. 3A, which is the same as that of Figs. 1A and 1B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 3A and 3B and the embodiment shown in FIGS. 1A and 1B is that the electrostatic discharge protection device 300 includes a gate structure 138.

According to some embodiments, as shown in FIG. 3A, the gate structure 138 is disposed on the upper surface of the semiconductor substrate 102. According to some embodiments, the gate structure 138 partially covers the first well region 104, the first doped region 108, the second well region 106, and the second doped region 110. According to some embodiments, the gate structure 138 is disposed between the second heavily doped region 134 and the third heavily doped region 136. According to some embodiments, the gate structure 138 does not cover the second heavily doped region 134 and the third heavily doped region 136.

According to some embodiments, as shown in FIG. 3A, the first heavily doped region 132, the second heavily doped region 134, and the gate structure 138 are electrically connected to the power supply line (VDD), and the third heavily doped region The area 136 is electrically connected to the ground line (VSS).

According to some embodiments, the gate structure 138 includes a gate dielectric layer 140 and a gate electrode 142 formed on the gate dielectric layer 140. In some embodiments, the gate dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, or a high-k (for example, a dielectric constant greater than 3.9) dielectric material. In some embodiments, the high-k dielectric material includes hafnium oxide. In some embodiments, the high-k dielectric material includes LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaTiO ₃ , BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO , LaSiO, AlSiO, BaTiO ₃ , SrTiO ₃ , Al ₂ O ₃ , other suitable high-k dielectric materials, or a combination of the foregoing. In some embodiments, through an oxidation process (for example, a dry oxidation process or a wet oxidation process), a deposition process (for example, a chemical vapor deposition (CVD) process), other suitable processes, or a combination of the foregoing, The gate dielectric layer is formed.

In some embodiments, the gate electrode 142 includes a conductive material, such as polysilicon or metal. In some embodiments, polysilicon may be doped. In some embodiments, the metal includes tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), platinum (Pt), similar metals, or a combination of the foregoing . In some embodiments, through a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an electroplating process, an atomic layer deposition (ALD) process, other appropriate processes, or the foregoing The combination of these forms a conductive material for the gate electrode 142. Next, the electrode material is patterned through a lithography process and an etching process to form the gate electrode 142.

According to some embodiments, when an electrostatic discharge event occurs on the power line (VDD), the gate structure 138 electrically connected to the power line (VDD) opens the channel area below it, which further increases the collector current (I _C ) . Therefore, the formation of the gate structure 138 further reduces the on-resistance (R _ON ) of the ESD protection device 300, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 4A is a schematic cross-sectional view of an ESD protection device 400 according to some embodiments of the present invention, and Fig. 4B is an equivalent circuit diagram of the ESD protection device 400 in Fig. 4A, which is the same as that of Figs. 3A and 3B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 4A and 4B and the embodiment shown in FIGS. 3A and 3B is that the electrostatic discharge protection device 400 includes the isolation member 122 as shown in FIG. 2A.

According to some embodiments, once the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, the emitter E (the second heavily doped region 134) and There will be a potential difference (V _EB ) between the base B (first doped region 108). If the resistance R1 of the first well region 104 is larger, the potential difference (V _EB ) between the emitter E and the base B is larger, which further increases the emitter current (I _E ). Therefore, forming the isolation member 122 further reduces the on-resistance (R _ON ) of the ESD protection device 400, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 5A is a schematic cross-sectional view of an ESD protection device 500 according to some embodiments of the present invention, and Fig. 5B is an equivalent circuit diagram of the ESD protection device 500 in Fig. 5A, which is the same as that of Figs. 1A and 1B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 5A and 5B and the embodiment shown in FIGS. 1A and 1B is that the first conductivity type is P-type and the second conductivity type is N-type.

According to some embodiments, as shown in FIG. 5A, the first heavily doped region 132 and the second heavily doped region 134 are electrically connected to the ground line (VSS), and the third heavily doped region 136 is electrically connected to Power supply line (VDD). According to some embodiments, the power line (VDD) and the ground line (VSS) provide high potential and low power respectively in the semiconductor device protected by the electrostatic discharge protection device 500.

According to some embodiments, as shown in FIGS. 5A and 5B, there is a PN junction between the second heavily doped region 134 and the first doped region 108, and between the second well region 106 and the first doped region 108 There is a PN junction. Therefore, the second heavily doped region 134, the first doped region 108, and the second well region 106 form a parasitic bi-carrier junction transistor (BJT). According to some embodiments, the two-carrier junction transistor is an NPN two-carrier junction transistor. According to some embodiments, the third heavily doped region 136 is the collector C of the two-carrier junction transistor, the first doped region 108 is the base B of the two-carrier junction transistor, and the second heavily doped Region 134 is the emitter E of the bi-carrier junction transistor.

According to some embodiments, the breakdown voltage of the PN junction between the second well region 106 and the first doped region 108 is lower than the operating voltage of the semiconductor device protected by the electrostatic discharge protection device 500. When an electrostatic discharge event occurs from the power supply line (VDD), because the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, the static electricity will flow from the power supply The line (VDD) is discharged to the ground line (VSS) through the dual carrier junction transistor of the electrostatic discharge protection device 500, and does not pass through the protected semiconductor device. Therefore, the electrostatic discharge protection device 500 protects the semiconductor device from being damaged in an electrostatic discharge event.

Furthermore, once the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage and a reverse current is generated, the emitter E (the second heavily doped region 134) and the base There will be a potential difference (V _EB ) between B (first doped region 108), and a large amount of emitter current (I _E ) will flow to collector C (third heavily doped region 136), thereby reducing electrostatic discharge protection The on-resistance (R _ON ) of the device 500. Therefore, the electrostatic discharge protection device 500 quickly discharges static electricity to the ground line (VSS).

Fig. 6A is a schematic cross-sectional view of an ESD protection device 600 according to some embodiments of the present invention, and Fig. 6B is an equivalent circuit diagram of the ESD protection device 600 in Fig. 6A, which is the same as that of Figs. 5A and 5B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 6A and 6B and the embodiment shown in FIGS. 5A and 5B is that the electrostatic discharge protection device 600 includes an isolation member 122 as shown in FIG. 2A.

According to some embodiments, as shown in FIGS. 6A and 6B, by forming the isolation feature 122, the first well region 104 provides a resistance R2 between the first heavily doped region 132 and the first doped region 108 (base B) . According to some embodiments, the resistance R2 is adjusted by changing the size D3 of the isolation member 122. For example, the larger the size D3, the larger the resistance R1, and vice versa.

According to some embodiments, once the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, the emitter E (the second heavily doped region 134) and There will be a potential difference (V _EB ) between the base B (first doped region 108). If the resistance R1 of the first well region 104 is larger, the potential difference (V _EB ) between the emitter E and the base B is larger, which further increases the emitter current (I _E ). Therefore, forming the isolation member 122 further reduces the on-resistance (R _ON ) of the electrostatic discharge protection device 600, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 7A is a schematic cross-sectional view of an ESD protection device 700 according to some embodiments of the present invention, and Fig. 7B is an equivalent circuit diagram of the ESD protection device 700 in Fig. 7A, which is the same as that of Figs. 5A and 5B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 7A and 7B and the embodiment shown in FIGS. 5A and 5B is that the electrostatic discharge protection device 700 includes a gate structure 138 as shown in FIG. 3A.

According to some embodiments, as shown in FIG. 7A, the first heavily doped region 132, the second heavily doped region 134, and the gate structure 138 are electrically connected to the ground line (VSS), and the third heavily doped region The area 136 is electrically connected to the power line (VDD).

According to some embodiments, when an electrostatic discharge event occurs on the power line (VDD), the gate structure 138 electrically connected to the power line (VDD) opens the channel area below it. Therefore, forming the gate structure 138 further reduces the on-resistance (R _ON ) of the ESD protection device 700, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 8A is a schematic cross-sectional view of an ESD protection device 800 according to some embodiments of the present invention, and Fig. 8B is an equivalent circuit diagram of the ESD protection device 800 in Fig. 8A, which is the same as that of Figs. 7A and 7B. The same reference numerals are used for the components of the embodiment, and the description thereof is omitted. The difference between the embodiment shown in FIGS. 8A and 8B and the embodiment shown in FIGS. 7A and 7B is that the electrostatic discharge protection device 800 includes the isolation member 122 as shown in FIG. 6A.

According to some embodiments, once the PN junction between the second well region 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, the emitter E (the second heavily doped region 134) and There will be a potential difference (V _EB ) between the base B (first doped region 108). If the resistance R2 of the first well region 104 is greater, the potential difference (V _EB ) between the emitter E and the base B is greater, which further increases the emitter current (I _E ). Therefore, forming the isolation member 122 further reduces the on-resistance (R _ON ) of the electrostatic discharge protection device 800, thereby discharging static electricity to the ground line (VSS) more quickly.

In summary, the embodiments of the present invention provide an electrostatic discharge protection device, which includes a parasitic bi-carrier junction transistor (BJT) formed by a heavily doped region, a middle doped region, and a lightly doped well region. ). When an electrostatic discharge event occurs, the PN junction of the well area and the intermediate doped area collapses at a lower voltage and a reverse current is generated, so that the static electricity is discharged through the two-carrier junction transistor of the electrostatic discharge protection device. Will pass the protected semiconductor device. Therefore, the electrostatic discharge protection device protects the semiconductor device from being damaged in an electrostatic discharge event.

The foregoing summarizes several embodiments so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions and replacements.

100, 200, 300, 400, 500, 600, 700, 800 ESD protection device 102 semiconductor substrate 104 first well region 106 second well region 108 first doped region 108A first part 108B second part 110 second Doped regions 121, 122, 123 isolation feature 132 first heavily doped region 134 second heavily doped region 136 third heavily doped region 138 gate structure 140 gate dielectric layer 142 gate electrode B base C set Pole D1, D2 Distance D3 Dimension E Emitter VDD Power line VSS Ground line

The embodiments of the present invention can be better understood through the following detailed description and examples in conjunction with the accompanying drawings. In order to make the drawings clearly show, the various elements in the drawings may not be drawn according to scale. Among them: Figure 1A is a cross-sectional schematic diagram of an electrostatic discharge protection device according to some embodiments of the present invention, and Figure 1B is Figure 1A The equivalent circuit diagram of the electrostatic discharge protection device; Figure 2A is a cross-sectional schematic diagram of the electrostatic discharge protection device according to some other embodiments of the present invention, and Figure 2B is the equivalent circuit diagram of the electrostatic discharge protection device in Figure 2A; 3A is a schematic cross-sectional view of an ESD protection device according to some other embodiments of the present invention, and FIG. 3B is an equivalent circuit diagram of the ESD protection device in FIG. 3A; FIG. 4A is a view of some other embodiments according to the present invention Fig. 4B is an equivalent circuit diagram of the ESD protection device in Fig. 4A; Fig. 5A is a cross-sectional schematic diagram of the ESD protection device according to some other embodiments of the present invention, and Fig. 5B is an equivalent circuit diagram of the electrostatic discharge protection device of Fig. 5A; Fig. 6A is a schematic cross-sectional view of the electrostatic discharge protection device according to some other embodiments of the present invention, and Fig. 6B is the ESD protection device of Fig. 6A Figure 7A is a cross-sectional schematic diagram of the electrostatic discharge protection device according to some other embodiments of the present invention, and Figure 7B is the equivalent circuit diagram of the electrostatic discharge protection device in Figure 7A; and Figure 8A is based on The cross-sectional schematic diagram of the electrostatic discharge protection device of some other embodiments of the present invention, and FIG. 8B is an equivalent circuit diagram of the electrostatic discharge protection device of FIG. 8A.

100 ESD protection device 102 semiconductor substrate 104 first well region 106 second well region 108 first doped region 108A first part 108B second part 110 second doped region 121, 123 isolation component 132 first heavily doped Region 134 Second heavily doped region 136 Third heavily doped region D1, D2 Distance from VDD power line VSS ground line

Claims (14)

An electrostatic discharge protection device includes: a first well region arranged in a semiconductor substrate; a first doped region having a first part arranged in the first well region and a first part arranged in the first well region A second part of the outer part; a first heavily doped region, arranged in the second part of the first doped region; a second heavily doped region, arranged in the first well region; wherein the first A doped region has a first conductivity type, and the first well region, the first heavily doped region, and the second heavily doped region have a second conductivity type, and the second conductivity type is the same as the first conductivity type. The conductivity type is opposite; a second well region has the first conductivity type, wherein the second part of the first doped region is disposed in the second well region; and a third heavily doped region is disposed in the In the second well region, the third heavily doped region has the first conductivity type. According to the ESD protection device described in claim 1, wherein the doping concentration of the first doping region is greater than the doping concentration of the second well region and less than the doping concentration of the first heavily doped region. According to the ESD protection device described in claim 1, wherein the doping concentration of the first doping region is greater than the doping concentration of the first well region. According to the ESD protection device described in claim 1, wherein the third heavily doped region and the first heavily doped region are electrically connected to a power line (VDD) or a ground line (VSS). Such as the electrostatic discharge protection device described in item 1 of the scope of patent application, which The first heavily doped region is electrically connected to one of a power line (VDD) and a ground line (VSS), and the second heavily doped region is electrically connected to the power line (VDD) and the The other of the ground lines (VSS). The electrostatic discharge protection device described in item 1 of the scope of patent application further includes: a second doped region disposed in the first well region, wherein the second doped region has the second conductivity type, and the The second heavily doped region is arranged in the second doped region. The electrostatic discharge protection device described in item 6 of the scope of patent application, wherein the concentration of the second doping region is greater than the doping concentration of the first well region and less than the doping concentration of the second heavily doped region. According to the electrostatic discharge protection device described in item 1 of the scope of patent application, the first conductivity type is N-type, and the second conductivity type is P-type. In the electrostatic discharge protection device described in item 1 of the scope of patent application, the first conductivity type is P type and the second conductivity type is N type. The electrostatic discharge protection device described in item 1 of the scope of patent application further includes a gate structure partially covering the first doped region and the first well region. According to the ESD protection device described in claim 10, the gate structure is disposed between the first heavily doped region and the second heavily doped region. The electrostatic discharge protection device described in item 10 of the scope of patent application, wherein the gate structure and the first heavily doped region are electrically connected to one of a power line (VDD) and a ground line (VSS) together , And the second heavily doped region is electrically connected to the other of the power line (VDD) and the ground line (VSS). According to the ESD protection device described in claim 1, wherein the first well region, the first doped region, and the first heavily doped region form a dual carrier junction transistor (BJT). The electrostatic discharge protection device described in item 13 of the scope of patent application, wherein the first heavily doped region is the emitter of the two-carrier junction transistor, and the first doped region is the two-carrier junction transistor The base of the crystal, and the second heavily doped region is the collector of the bi-carrier junction transistor.

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