GB2586599A - Electrically shorted PN junctions and functional semiconductor designs for the same - Google Patents

Electrically shorted PN junctions and functional semiconductor designs for the same Download PDF

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GB2586599A
GB2586599A GB1912236.5A GB201912236A GB2586599A GB 2586599 A GB2586599 A GB 2586599A GB 201912236 A GB201912236 A GB 201912236A GB 2586599 A GB2586599 A GB 2586599A
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layer
main side
conductivity type
layers
highly conductive
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Rahimo Munaf
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MQSemi AG
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MQSemi AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A layer or stack of highly conductive metallic layers (eg metals, silicides, graphene) is used to short circuit a PN junction in a semiconductor device. The metal layer is deposited and patterned on a first type conductivity layer in such a way that it does not fully cover the underlying layer. An additional growth/deposition step is used to form on top of the first and the metallic layer a second layer of a second conductivity type opposite to the first conductivity type. The highly conductive metal layer is embedded at the PN junction interface and effectively shorts the junction. The short circuit structure can be applied to power semiconductor devices (IGBTs, MOSFETs, thyristors, IGCTs, diodes) based on silicon, SiC, GaN, Ga2O3, AlN, diamond, etc. The invention introduces diode functionality in reverse conducting IGBTs or IGCTs and can also be applied to form soft recovery fast power diodes, or to reduce the leakage current in the junction termination areas of power semiconductor devices.

Description

DESCRIPTION
ELECTRICALLY SHORTED PN JUNCTIONS AND FUNCTIONAL SEMICONDUCTOR
DESIGNS FOR THE SAME
FIELD OF THE INVENTION
The invention relates to the field of power semiconductor devices. More specifically, the present disclosure relates to a new PN semiconductor j unction electrical shord ng effect using a buried or embedded highly conductive single layer or a combination/stack of layers (metal, si I i ci des, and or graphene).
TECHNICAL BACKGROUND
Trends in power semiconductor devices have frequently targeted the use of electrical shorts as a mean to control the bipolar injection efficiency in anode regions of bipolar semiconductor devices (such as IG BTs, thyristors, GT Os, or IGCTs), or for enabling integrated diode functionalities such as for Reverse Conducting IG BTs or Reverse Conducting IGCTs. For example, U.S. Pat No. 8,508,016 discloses a method of creating various bipolar semiconductor devices with multiple layers, at least one layer having alternating dopant regions including at least one first region of the first conductivity type and at least one second region of the second conductivity type.
Similarly, the literature reference from A. Kopta and M. Rahimo, "The Field Charge Extraction (FC E) di ode A Novel Technology for Soft Recovery High Voltage Diodes," Proc. ISPSID105, pp 83-86, Santa Barbara California, USA (2005), describes a concept which includes using highly doped P+ regions in an alternating arrangement with the N+ cathode regions of the main diode. T his is required in order to avoid high-frequency oscillation phenomena known in a high-speed recovery diode under severe recovery conditions such as a high DC-link voltage, a high wiring stray inductance (Ls), a low operating temperature, and a low current density. The operating mechanism of this technology is based on the returning electrons during diode reverse recovery, which will flow near the P+N junctions towards the N+ cathode regions. This results in an increased lateral voltage drop at the P+N junctions which will exceed the built-in voltage of the P+N junction, hence causing hole injection from the P+ region. The injected or induced holes will provide charge for soft performance during the latest stages of reverse recovery.
The previously described prior art is based on a manufacturing method comprising providing a substrate of a first conductivity type; implanting or depositing particles of the first conductivity type on the second main side to create a first region; and implanting or depositing particles of a second conductivity type on the second main side to create a second region and at least one of the creation of the first region or the implantation of the second particles being performed through a mask. The method described above suffers from multiple complex photolithography and implantation processing steps and reliance on thermal annealing for dopant activation and dopant compensation of the various dopants.
It is thus desirable to identify simpler and more efficient methods to create electrical ly shorted P N j uncti ons applicable to all type of juncti ons ( homoj uncti ons or heteroj uncti ons) and in all types of semiconductor materials (Silicon, Silicon Carbide, Gallium Nitride, Gallium Oxi de, Diamond, AIuminium Nitride, and others).
DISCLOSURE OF THE INVENTION
It may be an object of the present invention to provide a novel concept for creating an el ectri cal ly shorted PN junction with improved el ectri cal characteristics. F urtherrnore, it may be an object of the present invention to provide embodiments for using such a shorted PN junction concept for novel semiconductor device concepts withstanding, but not limited to: IG BT s and IG CTs with integrated diode functionality, fast diodes with soft reverse recovery, and/or devices with reduced current leakage under blocking conditions.
These objects may be met by the subject matter of the independent claims. Embodiments of the invention are described with respect to the dependent claims.
The inventive method for including an electrically shorted PN junction in any power semiconductor device will have at least two layers of different conductivity types. The layers 30 comprise a first layer of first conductivity type, the first layer being coupled to a first electrode on a first side di rectly or through other intermediate layers, a second layer of second conductivity type, the second layer being coupled to a second electrode on a second side, a third highly conductive layer of a metal, si I ici de or graphene is located precisely at the interface between the first and second layers, the third layer is interrupted along a predefined distance Furthermore, the N-type layers in a general PN junction can perform as the cathode regions, as well as the buffer regions, when suitable for punch-through type power semiconductor devices. The geomeiri cal planes of the different layers can also differ depending on the design and processing requirements.
toThe inventive configuration for an electrically shorted PN junction can subsequently be applied to various power semiconductor devices using such PN junctions within other layers of different conductivity types, which layers can be arranged between a first electrode on a first side (also named emitter in an IGBT, anode in a diode, or cathode in a Thyristor type device) and a second electrode on a second side (also named collector in an IG BT, cathode in a diode, or anode in a T hyristor type device), which is arranged opposite to the first side.
The layers can comprise: a first layer of a first conductivity type, which is arranged between the first and second sides, also named drift layer, a second layer of a second conductivity type, which is arranged between the drift layer and the first electrode, a third layer of the first conductivity type, which is arranged at the first side embedded into the second layer, which layer has a higher doping concentration than the drift layer and contacts the first electrode, a fourth layer of the second conduclivity type, which is arranged at the first side embedded into the second layer and is situated deeper than the third layer, and has a higher doping concentration than the second layer, which fourth layer can be in di rect contact with, or shielded from the first electrode, a first gate electrode, which is arranged at the first side and the first gate electrode can be electrically insulated by a first insulating layer from the second layer, the third layer and the drift layer, a lateral / horizontal /vertical channel is formable between the first elect-ode, the second layer, the third layer and the drift layer or a first gate electrode in direct contact with the fourth layer, optionally, a fifth layer of the first conductivity type, which is arranged at the second side on the drift layer, and has a higher doping concentration than the drift layer, a sixth layer of highly conductive material, which is arranged and structured at the second side on the fifth layer, a seventh layer of the second conductivity type, which is arranged between the sixth layer and the second electrode on the second side The sixth layer of highly conductive material can also be arranged at other i nterfaces/PN junctions in the power device, as long as the junction is not an electric field sustaining junction or part of a depletion region, etc With such a method for an inventive electrically shorted PN junction, an RC -IG BT or R C-IG CT can be provided with good control for the integrated diode part while reducing or eliminating overshooting of the current during reverse recovery of the di ode due to additional hole injection. The layers can be made thin, so that the manufacturing can be performed with thin wafers (e. g. below 200 and, as the final semiconductor devices can also be made thin. Such devices, are especially suitable for low voltages, e.g. below 1700 V. The inventive design is also suitable for reducing the leakage current in junction termination regions, and furthermore can be applied to all power semiconductors based on si I i con or wide bandgap materials such as SiC, GaN, A I N, Ga203, diamond, etc. Further preferred embodiments of the inventive subject matter are disclosed in the dependent claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which: FIG. 1A -B: show the cross sections of a Planar non-shorted PN junction and an electrically shorted PN junction according to pri or art.
FIG. 2: shows a first exemplary embodiment of an electrically shorted PN junction in a power semiconductor device according to the invention.
FIG. 3A-C: show a second exemplary embodiment of an electrically shorted PN junction with various P and N type dopant profiles in the lateral di recti on.
FIG. 4A-B: show a third exemplary embodiment of an electrically shorted PN junction taking into account van ous geometries and dopant prof i I es possible at the P/N interface.
FIG. 5A-B: show a fourth exemplary embodiment of a Reverse-Conducting IGBT according to prior art, and according to the invention.
FIG. 6A-B: show a fifth exemplary embodiment of a Reverse-Conducting IGCT according to prior art, and according to the invention.
FIG. 7A -B: show a sixth exemplary embodiment of a fast recovery power di ode according to prior art and according to the invention.
FIG. 8: shows a seventh exemplary embodiment of the termination region of a general power semiconductor device (IGBT, IGCT, Thyristor, Diode, MOSFET, and the like) according to the invention.
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schemati cal I y and not to scale. General ly, alike or al i ke-functi oni ng parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
MODES FOR CARRYING OUT THE INVENTION
In the fol I owi ng D etai led Description, reference is made to the accompanying drawings, which forma part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as 'top," 'bottom" 'front" 'back," 'leading," "trailing," etc., is used with reference to the orientation of the Figure (s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limit ng the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.
Unless otherwise defined, al l terms (including technical and scientific terms) used herei n have the same meaning as commonly understood by one of ordinary skill in the art to which 1c) example embodiments belong. It will be further understood that terms, e. g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. However, should the present disclosure give a specific meaning to a term deviating from a meaning commonly understood by one of ordinary skill, this meaning is to be taken into account in the specific context this definition is given herein.
In this specification, N -doped is referred to as first conductivity type while P -doped is referred to as second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be P -doped and the second conductivity type can be N -doped. Furthermore, some figures illustrate relative doping concentrations by indicating or "+" next to the doping type. For example, "N-" means a doping concentration which is less than the doping concentration of ' N _ -doping region while an ' N +" -doping region has a larger doping concentration than the N _ -doping region. However, indicating the relative doping concentration does not mean that doping regions of the same relative doping concentration have to have the same absolute doping concentration unless otherwise stated. For example, two different N+ -doping regions can have different absolute doping concentrations. The same applies, for example, to an N+ -doping and a P+ -doping region.
Specific embodiments described in this specification pertain to, without being limited thereto, electrically shorted PN junction -based semiconductor devices.
When referring to semiconductor devices, at least two -terminal devices are meant an example is a diode. Semiconductor devices can also be three -terminal devices such as a field -effect transistors (FETs), insulated gate bipolar transistors (IGBTs), junction field effect transistors U FETs), and thyristors to name a few. The semiconductor devices can also include more than three terminals.
Wide band -gap semiconductor materials such as SiC or GaN (Gallium Nitride) or AIN (Aluminium Nitride) or Diamond or G a203 (Gallium Oxide) have a high breakdown field strength and high critical avalanche field strength, respectively. Accordingly, the doping of semiconductor regions can be chosen higher compared to lower band -gap semiconductor materials such as Silicon, which reduces the on -state resistance Ron (also referred to as onresi stance Ron). In the following embodiments are mainly explained with regard to Si I icon as semiconductor material.
In the context of the present specification, the term 'in Ohmic connection_ intends to describe that there is an Ohmic current path, e.g. a low -Ohmic current path, between respective elements or pordons of a semiconductor device when no voltages or only small probe voltages are applied to and / or across the semiconductor device. Within this specification the terms 'in Ohrric connection _, 'in resistive electric connection", "electrically coupled_, and 'in resistive electric connection_ are used synonymously. In the context of the present specification, the term n Ohmic contact" intends to describe that two elements or portions of a semiconductor device are indirect mechanical and physical contact and in Ohmic connection. The terms 'electrical connection_ and 'electrically connected_ describe an Ohmic conned on between two features.
It will be understood that when an element is referred to as being 'connected_ or coupled_ to another element, it can be directly connected or coupled to the other element or intervening elements may be present In contrast, when an element is referred to as being 'directly connected" or "directly coupled_ to another element, there are no intervening elements present Other words used to describe the relationship between elements should be interpreted in a like fashion (e. g. 'between" versus 'directly between_, 'adjacent_ versus directly adjacent, _ etc.).
PN junctions depicted in FIG. 1A between a layer (5) of a first conductivity type, and layer (4) of a second conductivity type, are omnipresent in power semiconductor devices, where, when connected to el en-odes (20) and (30) they establish mainly two functional i ti es: supporting the formation of a depletion region i.e.. maintaining a high voltage blocking capability in reverse blocking conditions, and injecting minority carriers to ensure a low on-state resistance under forward bias operation (e.g. bipolar devices).
T o ensure additional functional iti es of semi conductors, such as i ntegrati ng a di ode, these PN junctions must be locally spatially interrupted, or electrically shorted. The prior art method for creating an electrically shorted PN junction in any power semiconductor device is shown in FIG. 1B. The flow of electrons follows the path of lowest electrical resistance through the N-doped layers (5) and (6), and therefore in forward bias mode (positive potential applied to electrode (20), negative potential to electrode (30)), the P-doped layer (4) will see a reduced concentration of electrons present at the interface between layers (4) and (6). Consequently, two effects are achieved simultaneously: providing an ohmic path for electrons to reach the first electrode (20), as well as reducing the hole injection effect from the layer (4). This method requires multiple mask, ion implantation, and thermal activation processes for achieving the required dopant compensation and activation levels.
A very similar effect is revealed in the innovative exemplary embodiment depicted in FIG. 2 that additionally includes an embedded/buried highly conductive layer (3) based on metals, silicides, or graphene, etc. The embedded layer (3) is arranged precisely at the interface between layers (4) and (5), i.e. in direct contact with both layers simultaneously.
To prevent a complete shorting of the PN junction, the embedded layer (3) must be interrupted spatially and cannot be continuous. The flow of electrons wi I l focus i n the metal! ike layer due to the absence of a PN junction barrier in that region, and will hence continue to flow towards the electrode (20) via the P+ layer (4) which behaves as a standard low resistor. When desirable, highly doped P+ and N+ layers can be used to reduce the formation of Schottky contacts at the interface with this embedded layer. The highly conductive layer (3) is deposited on the layer (5) by any process known to those skilled in the art, followed by a structuring process with a mask, and by growth/deposition of layer (4) uniformly across the structure. T his process represents a significant simplification compared to the prior art, while provi di ng numerous additi onal innovative embodiments as will be descri bed bel ow.
FIG s. 3A-C show a second exemplary embodiment of an electrically shorted PN j unction in a power semiconductor device according to the invention. The layers (4) and (5) are not uniformly doped in the lateral direction i.e.. layer (4') can be higher or lower doped than layer (4), and layer (57 can be lower doped than layer (5). Various dopant combinations can be envisioned, while making sure the highly conductive layer (3) is always in di rect contact with the highly doped layer (5).
By way of example, but not limited to the two images, the FIGS. 4A-B show yet a third embodiment of the invention, where the PN interface can have any arbitrary geometrical shape and dopant profiles as resulting from various semiconductor processes previously applied on the semiconductor device (e.g. due to dry or wet etch processes). T his means that in some semiconductor designs the plane in which the layer (3) is arranged, i.e.. the PN junction is shorted, will have a different distance to the second side (31) than the plane of the remaining non-shorted PN junction. In addition, the dopant profiles on both sides of the interface can be different, i.e.. a lower doped layer (51 can also be used to contact the layer (41 in areas where the highly conductive layer (3) is not present The embodiments described until now focus mainly on the general concepts for formi ng electrically shorted PN junctions. In the following embodiments, fully functional semiconductor designs will be disclosed by applying the novel electrical shorting method.
By means of example, and by comparison with prior art shown in FIG. 5A, the device shown in FIG. SB describes a fourth exemplary embodi ment for a Reverse Conducting IG BT type of device. The collector side (21) in FIG. SB does not include the alternate arrangement of first and second type conductivity layers (4) and (6) being in di rect contact with electrode (20) and the buffer layer (2) (equivalent to the layer (5) in FIGS. 1-4). Instead, the highly conductive layer (3) is arranged at the interface between layers (4) and (2), enabling the integrated diode functionality i.e.. unrestricted flow of electrons between the layers (2) and (20). The rest of the PN junction not covered by layer (3) enables the actual IG BT part to be formed. A layer with a different concentration (5') than the buffer layer (2) can also be used to contact the layer (4) outside of the layer (3), depending on the design. More importantly, the top side of the IGBT structure is indicated for exemplification purposes as a planar type of design, however it is understood that other features are also included in the embodiment, such as using trench based designs, or enhancement layers.
FIGs. 6A -B show a fifth exemplary embodiment for a Reverse Conducting IGCT, where the anode side (21) is structured using the new shorting method to enable the integration of the di ode functionality.
FIGs. 7A-B show a sixth exemplary embodiment for a fast recovery power diode. The prior art in FIG. 7A depicts the so called 'Field Charge Extraction_ concept, where the additional P-doped shorts (4) are introduced in the cathode side of the diode represented by the N-doped layer (6). During the end stages of the reverse recovery process, the electrons wi I I flow towards the electrode (30) through the buffer layer (2). In trying to reach the layer (6), the electrons will flow also laterally on top of the layer (4). In turn, this will generate a small voltage drop that will forward bias the PN junction between layers (4) and (2), and as a consequence, additional holes will be injected in the diode from the side (21) preventing the current thru the diode to stop immediately. These holes will enable a soft recovery process, thus avoiding high frequency oscillations and overvoltage characteristic to fast power diodes. For the innovative embodiment in FIG. 7B, the working principle is identical s to the one just described, with electrons flowing laterally on top of the portion of layer (6) not covered by the layer (3) towards the layer (3), and the same end effect can be achieved. In forward bias mode, the diode operation remains unchanged as the electrons can fl ow from the electrode (20), through layer (4) (acting as a simple highly P-doped resistor) and through layer (3) in the drift region of the diode.
The innovative shorting concept can be applied not only in the active areas of various power semiconductors as described above, but also in the junction termination regions. These termi nation regions are particularly sensitive to charge card ers being injected at high temperatures from layer (4) at the back side of the device which increase the leakage current levels in those regions. As seen in the seventh exemplary embodiment shown in FIG. 8, by introducing the highly conductive layer (3) in the edge region of the semiconductors, an effective shorting of the P-doped back side layer (4) is achieved. This reduces the leakage current in the forward blocking mode of the semiconductor, and contributes to enhancing the reliability of the semiconductors, especially at higher temperatures.
Reference list 1: substrate/drift layer 2: buffer layer 20: Second side metallization (electrode) 21: Second side 3: highly conductive layer 30: First side metal I izati on (electrode) 31: Fi rst si de 4: P+-doped layer 4': P-doped layer 5: N+-doped layer 5': N-doped layer 6: N+-doped shorts embedded i n the P-doped region 7: N+ source layer i n IG BT : N+ cathode layer in IG CT 8: P-base I ayer i n IGBT 8: P-base layer i n IGCT 9: P-doped guard rings 10: P-doped anode i n di ode 11, 11 -: gate electrodes, electrically conductive layers 12: insulating gate oxide gate electrode i n IG BT 13, 13 -: insulation layers 14: junction termination passivati on I ayer(s) 15: semiconductor device active area 16: semiconductor device termination area 50: typical PN junction in semiconductor devices 50': method of generating PN junction shorts (prior art) 51: electrically shorted PN junctions(invention) 100: Reverse Conduct ng IGBT (prior art) 101: Reverse Conducting IGBT (i nventi on) 200: Reverse Conducting IGCT (prior art) 201: Reverse Conducting IGCT (i nventi on)
300: Fast recovery Diode (prior art)
301: Fast recovery Diode (invention) 401: J unction termi nation of power semiconductor device (invention)

Claims (13)

  1. CLAIMS1. A method for designing an electrically shorted PN junction concept as part of a semiconductor device having a semiconductor substrate, and at least a three-layer structure with layers of a first and a second conductivity types, a first main side, and a second main side, wherein the first main side is arranged opposite of the second main side, wherein a first electrical contact is arranged on the first main side; characterized in that the first electrical contact is coupled directly or by means of other layers to the first conductivity type layer, wherein a second el ectri cal contact is arranged on the second main side; characterized in that, the second electrical contact is coupled directly or by means of other layers to the second conductivity type layer, wherein a third layer is arranged at the interface between the first and the second conductivity type layers; characterized in that the third layer is highly conductive, and covers only partially the interface between the first and the second conductivity type I ayers; the method of a obtaining a third layer on the surface of the first conductivity layer comprising: depositing or growing a third highly conductive layer on the first conductivity type layer; and, structuring the third layer by means of a mask and I ithography process; and, growing and/or depositing the second conductivity type layer on top of the third layer and the first conductivity type layer.
  2. 2. The method according to claim 1, characterized in that the third highly conductive layer can be a single or multi-stack of metals such as Aluminium, Titanium Copper, Nickel, and the I i ke.
  3. 3. The method according to claim 1, characterized in that the third highly conductive layer can be a metal si I i ci de obtained by a thermal anneal process.
  4. 4. The method device according to claim 1, characterized in that the third highly conductive layer can be a graphene layer of single or multiple atomic layer thickness.
  5. 5. The method according to claim 1, wherein the first and second type conductivity layers can have a predetermined varying concentration of dopant particles in the lateral direction parallel to the second side; characterized in that, the third highly conductive layer is i n direct electrical contact with the region of highest dopant concentration in the first type layer.
  6. 6. The method according to claim 1, characterized in that the third highly conductive layer and the first type conductivity layer are in direct contact, their interface being arranged in a first plane parallel to the second main side; and, the first and the second type conductivity layers are in direct contact, their interface being arranged in a second plane parallel to the second main side, the second plane being positioned at a different distance from the second main side than the first plane.
  7. 7. The method according to claim 1, wherein the third highly conductive layer has a geometrical shape of one of cells or stripes.
  8. 8. A bipolar punch-through semiconductor device according to claim 1, and any of the claims 2 thru 7, comprising: a semiconductor substrate, having at least a three-layer structure with layers of a first and a second conductivity type, a first main side, and a second main side, wherein one of the layers is a drift layer of the first conductivity type, wherein the first main side is arranged opposite of the second main side, wherein a first electrical contact is arranged on the first main side, wherein a second electrical contact is arranged on the second main side, wherein a buffer layer of the first conductivity type is arranged on the drift layer on the second main side, which buffer layer has a higher doping concentration than the drift layer and contacts the second conductivity type layer, wherein a highly conductive layer is arranged on the buffer layer, wherein a second conductivity type layer is arranged on the highly conductive layer and the buffer layer.
  9. 9. The bipolar punch-through semiconductor device according to claim 8, wherein the bipolar device is a bipolar switch that includes one of: a reverse conducting insulated gate bipolar transistor or a reverse conducting insulated gate commutated thyristor.
  10. 10. A bipolar non-punch-through semiconductor device according to claim 1, and any of the claims 2 thru 7, comprising: a semiconductor substrate, having at I east a three-layer structure with layers of a first and a second conductivity type, a first main side, and a second main side, wherein one of the layers is a drift layer of the first conductivity type, wherein the first main side is arranged opposite of the second main side, wherein a first electrical contact is arranged on the first main side, wherein a second electrical contact is arranged on the second main side, wherein the drift layer has multiple regions of the first conductivity type on the second main side, each region having a higher doping concentration than the drift layer, wherein a highly conductive layer is arranged on these multiple regions, covering all, or some of these regions, wherein a second conductivity type layer is arranged on the highly conductive and drift layers.
  11. 11. A bipolar semiconductor IG BT device, according to claims 8 and 10, characterized in that the first side (or emitter side) can be structured according to any designs using planar MOS channels, or verti cal trench MOS channels, or a combination of planar and trench MOS channels, some of the designs can make use of enhancement layers, and can be shaped as cell designs, or stripe designs when viewed from the top of the structure.
  12. 12. A bipolar diode, comprising: a semiconductor substrate, having at least a two-layer structure with layers of a first and a second conductivity type, a first main side, and a second main side, wherein one of the layers is a drift layer of the first conductivity type, wherein the first main side is arranged opposite of the second main side, wherein a first electrical contact is arranged on the first main side, wherein a second electrical contact is arranged on the second main side, wherein a buffer layer of the first conductivity type is arranged on the drift layer on the second main side, which buffer layer has a higher doping concentration than the drift layer, wherein a highly conductive layer is arranged on the buffer layer, wherein a second conductivity type layer is arranged on the highly conductive layer and the buffer layer.
  13. 13. A junction-termination structure for controlling the leakage current in a power semiconductor device, comprising: a semiconductor substrate, having at least a two-layer structure with layers of a first and a second conductivity type, a first main side, and a second main side, wherein one of the layers is a drift layer of the first conductivity type, wherein the first main side is arranged opposite of the second main side, wherein a first electrical contact is arranged on the first main side, wherein a second electrical contact is arranged on the second main side, wherein an active area of a device is arranged in the device on the first side arranged in between the drift layer and the first electrode, wherein a junction-termination region is arranged i n the device on the first side, wherein a buffer layer of the first conductivity type is arranged on the drift layer on the second main side, which buffer layer has a higher doping concentration than the drift layer, wherein a highly conductive layer is arranged on the buffer layer, wherein a second conductivity type layer is arranged on the highly conductive layer and the buffer layer.
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Citations (6)

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US5475243A (en) * 1991-07-02 1995-12-12 Fuji Electric Co., Ltd. Semiconductor device including an IGBT and a current-regenerative diode
US5519245A (en) * 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5981981A (en) * 1993-10-13 1999-11-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a bipolar structure
US6452219B1 (en) * 1996-09-11 2002-09-17 Denso Corporation Insulated gate bipolar transistor and method of fabricating the same
US20060145191A1 (en) * 2003-02-18 2006-07-06 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing such a device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4782379A (en) * 1981-11-23 1988-11-01 General Electric Company Semiconductor device having rapid removal of majority carriers from an active base region thereof at device turn-off and method of fabricating this device
US5519245A (en) * 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5475243A (en) * 1991-07-02 1995-12-12 Fuji Electric Co., Ltd. Semiconductor device including an IGBT and a current-regenerative diode
US5981981A (en) * 1993-10-13 1999-11-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including a bipolar structure
US6452219B1 (en) * 1996-09-11 2002-09-17 Denso Corporation Insulated gate bipolar transistor and method of fabricating the same
US20060145191A1 (en) * 2003-02-18 2006-07-06 Koninklijke Philips Electronics N.V. Semiconductor device and method of manufacturing such a device

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