CN111415928B

CN111415928B - Electrostatic discharge protection device

Info

Publication number: CN111415928B
Application number: CN201910007770.1A
Authority: CN
Inventors: 周业宁; 廖显峰; 叶家荣
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2019-01-04
Filing date: 2019-01-04
Publication date: 2022-12-02
Anticipated expiration: 2039-01-04
Also published as: CN111415928A

Abstract

The invention provides an electrostatic discharge protection device, which comprises a first well, a second well, a first doped region and a second heavily doped region. The first well and the second well are disposed in the semiconductor substrate. The first doped region is disposed in the first well and the second well. The second heavily doped region is disposed in the first doped region in the first well. The first well and the first doped region have a first conductivity type, and the second well and the second heavily doped region have a second conductivity type, the second conductivity type being opposite the first conductivity type. The invention can protect the semiconductor device from damage in the event of electrostatic discharge.

Description

Electrostatic discharge protection device

Technical Field

The present invention relates to an electrostatic discharge protection device, and more particularly, to an electrostatic discharge protection device having a low on-resistance.

Background

Electrostatic discharge (ESD) has been one of the important reliability concerns in semiconductor products. There are two types of electrostatic discharge tests known to those of ordinary skill, a Human Body Model (HBM) and a machine discharge model (MM). Typical commercial integrated circuits must have some tolerance for HBM and MM in order to be sold, otherwise the integrated circuits are very vulnerable to accidental esd events. Therefore, how to manufacture an efficient esd protection device/device for protecting an integrated circuit is a problem that is continuously studied and researched.

Disclosure of Invention

Some embodiments of the present invention provide an electrostatic discharge protection device for protecting a semiconductor device from damage in the event of an electrostatic discharge, the electrostatic discharge protection device comprising a first well and a second well. The first well and the second well are disposed in the semiconductor substrate. The first well has a first conductivity type and the second well has a second conductivity type, the second conductivity type being opposite the first conductivity type. The ESD protection device includes a first doped region. The first doped region is disposed in the first well and the second well. The first doped region has a first conductivity type. The ESD protection device includes a second heavily doped region. The second heavily doped region is disposed in the first doped region in the first well. The first heavily doped region has a second conductivity type.

Some embodiments of the present invention provide an electrostatic discharge protection device for protecting a semiconductor device from damage in the event of an electrostatic discharge, the electrostatic discharge protection device comprising a second well. The second well is arranged in the semiconductor substrate. The ESD protection device includes a first doped region. The first doped region has a first portion disposed outside the second well and a second portion disposed in the second well. The ESD protection device includes a second heavily doped region. The second heavily doped region is disposed in the first portion of the first doped region. The ESD protection device includes a third heavily doped region. The third heavily doped region is disposed in the second well. The first doped region has a first conductivity type, and the second well, the second heavily doped region, and the third heavily doped region have a second conductivity type, which is opposite to the first conductivity type.

The ESD protection device in the embodiment of the invention can discharge static electricity through the bipolar junction transistor of the ESD protection device without passing through the protected semiconductor device. Thus, the ESD protection device protects the semiconductor device from damage during an ESD event.

Drawings

Embodiments of the invention will be understood more fully from the detailed description and examples that follow, taken in conjunction with the accompanying drawings. In order to make the drawings clear, various elements in the drawings may not be drawn to scale, wherein:

FIG. 1A is a schematic cross-sectional diagram of an ESD protection device according to some embodiments of the present invention, and FIG. 1B is an equivalent circuit diagram of the ESD protection device of FIG. 1A;

FIG. 2A is a schematic cross-sectional diagram of an ESD protection device according to some other embodiments of the present invention, and FIG. 2B is an equivalent circuit diagram of the ESD protection device of FIG. 2A;

FIG. 3A is a schematic cross-sectional view of an ESD protection device according to some other embodiments of the present invention, and FIG. 3B is an equivalent circuit diagram of the ESD protection device of FIG. 3A;

FIG. 4A is a schematic cross-sectional view of an ESD protection device according to some other embodiments of the present invention, and FIG. 4B is an equivalent circuit diagram of the ESD protection device of FIG. 4A;

FIG. 5A is a schematic cross-sectional view of an ESD protection device according to some other embodiments of the present invention, and FIG. 5B is an equivalent circuit diagram of the ESD protection device of FIG. 5A;

FIG. 6A is a schematic cross-sectional view of an ESD protection device according to some other embodiments of the present invention, and FIG. 6B is an equivalent circuit diagram of the ESD protection device of FIG. 6A;

FIG. 7A is a schematic cross-sectional diagram of an ESD protection device according to some other embodiments of the present invention, and FIG. 7B is an equivalent circuit diagram of the ESD protection device of FIG. 7A;

fig. 8A is a schematic cross-sectional view of an esd protection device according to some other embodiments of the invention, and fig. 8B is an equivalent circuit diagram of the esd protection device of fig. 8A.

The symbols of the attached drawings:

100. 200, 300, 400, 500, 600, 700, 800 electrostatic discharge protection devices;

102. a semiconductor substrate;

104. a first well;

106. a second well;

108. a first doped region;

108A a first portion;

108B second portion;

110. a second doped region;

121. 122, 123 spacer elements;

132. a first heavily doped region;

134. a second heavily doped region;

136. a third heavily doped region;

138. a gate structure;

140. a gate dielectric layer;

142. a gate electrode;

a base electrode B;

c, collecting the electrode;

distance D1 and distance D2;

d3 Size;

an emitter E;

a VDD power line;

and a VSS ground line.

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing various components of the provided electrostatic discharge protection devices (ESD). Specific examples of components and arrangements thereof are described below to simplify the description of the embodiments of the invention. These are, of course, merely examples and are not intended to limit the invention from that described in the embodiments. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.

Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional steps may be provided before, during, or after the method, and that some of the recited steps may be substituted or deleted for other embodiments of the method.

Embodiments of the present invention provide an electrostatic discharge protection device, which includes a parasitic Bipolar Junction Transistor (BJT) formed by a heavily doped region, a middle doped region, and a lightly doped well. When an esd event occurs, the PN junction between the well and the undoped region collapses at a lower voltage to generate a reverse current, such that static electricity is discharged through the bipolar transistor of the esd protection device and not through the protected semiconductor device. Thus, the ESD protection device protects the semiconductor device from damage during an ESD event.

Fig. 1A is a schematic cross-sectional view of an esd protection device 100 according to some embodiments of the invention, and fig. 1B is an equivalent circuit diagram of the esd protection device 100 of fig. 1A.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 comprises a semiconductor substrate 102. According to some embodiments, the semiconductor substrate 102 comprises a silicon (Si) substrate. According to some embodiments, the semiconductor substrate 102 comprises an elemental semiconductor, such as germanium (Ge); compound semiconductors such as GaN, siC, gaAs, gaP, inP, inAs, and/or InSb; alloy semiconductors such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination of the foregoing.

According to some embodiments, the semiconductor substrate 102 is doped to have a first conductivity type or a second conductivity type opposite the first conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In some embodiments, the semiconductor substrate 102 has a first conductivity type (e.g., N-type), which may be doped with phosphorus (P) or doped with arsenic (As), for example. In some embodiments, the semiconductor substrate 102 has a second conductivity type (e.g., P-type), which may be doped with boron (B), for example.

According to some embodiments, in addition to the esd protection device 100, other semiconductor devices (not shown), such as active devices, passive devices (such as resistors or capacitors), or combinations thereof, are formed on the semiconductor substrate 102. In some embodiments, the active device includes a transistor, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Metal Insulator Semiconductor Field Effect Transistor (MISFET), a Junction Field Effect Transistor (JFET), an Insulated Gate Bipolar Transistor (IGBT), or a combination thereof. The esd protection device 100 protects these semiconductor devices during an esd event.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 includes a first well 104 and a second well 106. According to some embodiments, the first well 104 and the second well 106 are disposed in the semiconductor substrate 102 and extend downward from an upper surface of the semiconductor substrate 102. According to some embodiments, the first well 104 is in contact with the second well 106.

According to some embodiments, the first well 104 and the second well 106 have opposite conductivity types. According to some embodiments, the first well 104 has a first conductivity type (e.g., N-type) and the second well has a second conductivity type (e.g., P-type). In some embodiments, the first conductivity type is an N-type dopant, such As phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb) ions, or a combination of the foregoing. In some embodiments, the second conductivity type is a P-type dopant, such as boron (B), gallium (Ga), aluminum (Al), indium (In), or a combination of the foregoing. In some embodiments, first well 104 and second well 106 may be formed by respective ion implantation processes.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 comprises a first doped region 108. According to some embodiments, the first doped region 108 has a first portion 108A disposed in the first well 104 and a second portion 108B disposed in the second well 106. According to some embodiments, the boundary between the first well 104 and the second well 106 passes through the first doped region 108. According to some embodiments, the first doped region 108 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the first doped region 108 has a first conductivity type (e.g., N-type). According to some embodiments, the doping concentration of the first doped region 108 is greater than the doping concentration of the first well 104. According to some embodiments, the doping concentration of the first doped region 108 is greater than the doping concentration of the second well 106. According to some embodiments, the first doped region 108 may be formed by an ion implantation process.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 comprises a second doped region 110. According to some embodiments, the second doped region 110 is disposed in the second well 106. According to some embodiments, the second doped region 110 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the second doped region 110 has a second conductivity type (e.g., P-type). According to some embodiments, the doping concentration of the second doping region 110 is greater than the doping concentration of the second well 106. In some embodiments, the second doped region 110 may be formed by an ion implantation process.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 comprises a first heavily doped region 132. According to some embodiments, the first heavily doped region 132 provides ohmic contact with an interconnect structure (not shown, such as a contact) formed thereon. According to some embodiments, first heavily doped region 132 is disposed in first well 104. According to some embodiments, a portion of the first heavily doped region 132 is disposed in the first doped region 108. According to some embodiments, the first heavily doped region 132 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the first heavily doped region 132 has a first conductivity type (e.g., N-type). According to some embodiments, the doping concentration of the first heavily doped region 132 is greater than the doping concentration of the first well 104 and the doping concentration of the first doped region 108. According to some embodiments, the first heavily doped region 132 may be formed by an ion implantation process.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 comprises a second heavily doped region 134. According to some embodiments, the second heavily doped region 134 provides an ohmic contact to an interconnect structure (not shown, e.g., a contact) formed thereon. According to some embodiments, the second heavily doped region 134 is disposed in the first portion 108A of the first doped region 108. According to some embodiments, all of the second heavily doped region 134 is disposed in the first portion 108A of the first doped region 108. According to some embodiments, the first heavily doped region 132 is in contact with the second heavily doped region 134. According to some embodiments, the second heavily doped region 134 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the second heavily doped region 134 has a second conductivity type (e.g., P-type). According to some embodiments, the doping concentration of the second heavily doped region 134 is greater than the doping concentration of the first doped region 108. According to some embodiments, the second heavily doped region 134 may be formed by an ion implantation process.

According to some embodiments, as shown in fig. 1A, the esd protection device 100 includes a third heavily doped region 136. According to some embodiments, the third heavily doped region 136 provides an interconnect structure (not shown, e.g., a contact) ohmic contact formed thereon. According to some embodiments, the third heavily doped region 136 is disposed in the second well 106 outside the first doped region 108. According to some embodiments, all of the third heavily doped region 136 is disposed in the second doped region 110 in the second well 106. According to some embodiments, the third heavily doped region 136 extends downward from the upper surface of the semiconductor substrate 102.

According to some embodiments, the third heavily doped region 136 has the second conductivity type (e.g., P-type). According to some embodiments, the doping concentration of the third heavily doped region 136 is greater than the doping concentration of the second doped region 110. According to some embodiments, the third heavily doped region 136 may be formed by an ion implantation process.

According to some embodiments, as shown in fig. 1A, the electrostatic discharge protection device 100 includes an isolation member 121 and an isolation member 123. According to some embodiments, the isolation features 121 and 123 extend downward from the upper surface of the semiconductor base 102.

According to some embodiments, the isolation features 121 and 123 define regions of the esd protection device 100 formed in the semiconductor substrate 102. According to some embodiments, isolation features 121 are disposed on a side of first well 104 away from second well 106, and isolation features 123 are disposed on a side of second well 106 away from first well 104.

In some embodiments, the isolation features 121, 123 include Field Oxide (FOX), local oxide of silicon (LOCOS), or Shallow Trench Isolation (STI) structures. In some embodiments, the isolation features 121, 123 are formed of silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations of the foregoing. In some embodiments, the isolation features 121, 123 are formed by a thermal oxidation process. In some embodiments, the isolation features 121, 123 are formed by an etching process and a deposition process.

According to some embodiments, as shown in fig. 1A, the first heavily doped region 132 and the second heavily doped region 134 are electrically connected to a power line (VDD) together, and the third heavily doped region 136 is electrically connected to a ground line (VSS). According to some embodiments, the power line (VDD) and the ground line (VSS) provide high and low potentials, respectively, to the semiconductor devices protected by the esd protection device 100.

In some embodiments, the first heavily doped region 132 and the second heavily doped region 134 are electrically connected to a power line (VDD) and the third heavily doped region 136 is electrically connected to a ground line (VSS) by forming an interconnect structure over the semiconductor substrate 102. In some embodiments, the interconnect structure includes contacts contacting the first heavily doped region 132, the second heavily doped region 134, and the triple doped region 136, respectively. In some embodiments, the interconnect structure further includes conductive lines and vias (via) formed over the contacts.

According to some embodiments, as shown in fig. 1A and 1B, a PN junction exists between the second heavily doped region 134 and the first doped region 108, and a PN junction exists between the second well 106 and the first doped region 108. Thus, the second heavily doped region 134, the first doped region 108, and the second well 106 form a parasitic Bipolar Junction Transistor (BJT). According to some embodiments, the bipolar junction transistor is a PNP bipolar junction transistor. According to some embodiments, the third heavily doped region 136 is a collector (collector) C of the bipolar junction transistor, the first doped region 108 is a base (base) B of the bipolar junction transistor, and the second heavily doped region 134 is an emitter (emitter) E of the bipolar junction transistor.

According to some embodiments, the breakdown voltage of the PN junction between the second well 106 and the first doped region 108 is lower than the operating voltage of the semiconductor device protected by the esd protection device 100. When an esd event occurs from the power line (VDD), since the PN junction between the second well 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, static electricity is discharged from the power line (VDD) to the ground line (VSS) through the bjt of the esd protection device 100, but not through the protected semiconductor device. Thus, the ESD protection device 100 protects the semiconductor device from damage during an ESD event.

Furthermore, once the PN junction between the second well 106 and the first doped region 108 breaks down at a lower voltage to generate a reverse current, a potential difference (VEB) exists between the emitter E (the second heavily doped region 134) and the base B (the first doped region 108), and a large amount of emitter current (IE) flows to the collector C (the third heavily doped region 136), thereby reducing the on-Resistance (RON) of the esd protection device 100. Therefore, the esd protection device 100 discharges static electricity to the ground line (VSS) quickly.

Furthermore, according to some embodiments, the first doped region 108 and the third heavily doped region 136 are spaced apart by a distance D1. If the distance D1 is too small, the breakdown voltage of the PN junction between the second well 106 and the first doped region 108 will be lower. If the distance D1 is too large, the on-Resistance (RON) of the ESD protection device 100 may increase. According to some embodiments, the second heavily doped region 134 disposed in the first well 104 is spaced apart from the edge of the first well 104 by a distance D2.

Furthermore, according to some embodiments, the on-Resistance (RON) of the esd protection device 100 is further reduced by forming the second doped region 110 in the second well 106, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 2A is a schematic cross-sectional view of an esd protection device 200 according to some embodiments of the invention, and fig. 2B is an equivalent circuit diagram of the esd protection device 200 of fig. 2A, wherein the same components as those in the embodiments of fig. 1A and 1B are denoted by the same reference numerals and their descriptions are omitted. The embodiment shown in fig. 2A and 2B differs from the embodiment of fig. 1A and 1B described above in that the esd protection device 200 comprises the isolation component 122.

According to some embodiments, isolation features 122 are disposed in first well 104. According to some embodiments, the isolation feature 122 is disposed between the first and second heavily doped

regions

132 and 134. According to some embodiments, the isolation feature 122 extends downward from the upper surface of the semiconductor substrate 102. According to some embodiments, the first heavily doped region 132 is disposed in the first well 104 outside the first doped region 108A. In some embodiments, the material and formation method of the isolation feature 122 may be the same as or similar to those of the isolation features 121, 123 of fig. 1A.

According to some embodiments, as shown in fig. 2A and 2B, the first well 104 provides a resistance R1 between the first heavily doped region 132 and the first doped region 108 (base B) by forming the isolation part 122. According to some embodiments, the resistance R1 is adjusted by changing the dimension D3 of the isolation feature 122. For example, the larger the dimension D3, the larger the resistance R1, and vice versa. If dimension D3 is too small, resistance R1 does not increase significantly. If D3 is too large, the layout density of the semiconductor devices on the semiconductor substrate 102 is reduced.

According to some embodiments, once the PN junction between the second well 106 and the first doped region 108 breaks down at a lower voltage to generate a reverse current, there is a potential difference (VEB) between the emitter E (the second heavily doped region 134) and the base B (the first doped region 108). If the resistance R1 of the first well 104 is larger, the potential difference (VEB) between the emitter E and the base B is larger, which further increases the emitter current (IE). Therefore, forming the isolation member 122 further reduces the on-Resistance (RON) of the esd protection device 200, thereby more rapidly discharging static electricity to the ground line (VSS).

Fig. 3A is a schematic cross-sectional view of an esd protection device 300 according to some embodiments of the invention, and fig. 3B is an equivalent circuit diagram of the esd protection device 300 of fig. 3A, wherein the same reference numerals are used for the same components as those in the embodiments of fig. 1A and 1B and their descriptions are omitted. The embodiment shown in fig. 3A and 3B differs from the embodiment of fig. 1A and 1B described above in that the esd protection device 300 comprises the gate structure 138.

According to some embodiments, as shown in fig. 3A, the gate structure 138 is disposed on the upper surface of the semiconductor substrate 102. According to some embodiments, the gate structure 138 partially covers the first well 104, the first doped region 108, the second well 106, and the second doped region 110. According to some embodiments, the gate structure 138 is disposed between the second heavily doped region 134 and the third heavily doped region 136. According to some embodiments, the gate structure 138 does not cover the second heavily doped region 134 and the third heavily doped region 136.

According to some embodiments, as shown in fig. 3A, the first heavily doped region 132, the second heavily doped region 134, and the gate structure 138 are electrically connected to a power line (VDD), and the third heavily doped region 136 is electrically connected to a ground line (VSS).

According to some embodiments, the gate structure 138 includes a gate dielectric layer 140 and a gate electrode 142 formed over the gate dielectric layer 140. In some embodiments, the gate dielectric layer 140 comprises silicon oxide, silicon nitride, silicon oxynitride, or a high-k (e.g., dielectric constant greater than 3.9) dielectric material. In some embodiments, the high-k dielectric material comprises hafnium oxide. In some embodiments, the high-k dielectric material comprises LaO, alO, zrO, tiO, ta2O5, Y2O3, srTiO3, baTiO3, baZrO, hfZrO, hfLaO, hfTaO, hfSiO, hfSiON, hfTiO, laSiO, alSiO, baTiO3, srTiO3, al2O3, other suitable high-k dielectric materials, or a combination of the foregoing. In some embodiments, the gate dielectric layer is formed by an oxidation process (e.g., a dry oxidation process or a wet oxidation process), a deposition process (e.g., a Chemical Vapor Deposition (CVD) process), other suitable processes, or a combination of the foregoing.

In some embodiments, gate electrode 142 comprises a conductive material, such as polysilicon (polysilicon) or a metal. In some embodiments, the polysilicon may be doped. In some embodiments, the metal comprises tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), platinum (Pt), similar metals, or combinations of the foregoing. In some embodiments, the conductive material for the gate electrode 142 is formed by a chemical vapor deposition (cvd) process, a Physical Vapor Deposition (PVD) process, a plating process, an Atomic Layer Deposition (ALD) process, other suitable processes, or a combination of the foregoing. Next, the electrode material is patterned through a photolithography process and an etching process to form the gate electrode 142.

According to some embodiments, when an electrostatic discharge event occurs in the power line (VDD), the gate structure 138 electrically connected to the power line (VDD) opens the channel region thereunder, which further increases the collector current (IC). Therefore, forming the gate structure 138 further reduces the on-Resistance (RON) of the esd protection device 300, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 4A is a schematic cross-sectional view of an esd protection device 400 according to some embodiments of the invention, and fig. 4B is an equivalent circuit diagram of the esd protection device 400 of fig. 4A, wherein the same reference numerals are used for the same components as those in the embodiments of fig. 3A and 3B, and descriptions thereof are omitted. The embodiment shown in fig. 4A and 4B differs from the embodiment of fig. 3A and 3B described above in that the esd protection device 400 comprises the isolation component 122 shown in fig. 2A.

According to some embodiments, once the PN junction between the second well 106 and the first doped region 108 breaks down at a lower voltage to generate a reverse current, there is a potential difference (VEB) between the emitter E (the second heavily doped region 134) and the base B (the first doped region 108). If the resistance R1 of the first well 104 is larger, the potential difference (VEB) between the emitter E and the base B is larger, which further increases the emitter current (IE). Therefore, forming the isolation member 122 further reduces the on-Resistance (RON) of the esd protection device 400, thereby more rapidly discharging static electricity to the ground line (VSS).

Fig. 5A is a schematic cross-sectional view of an esd protection device 500 according to some embodiments of the invention, and fig. 5B is an equivalent circuit diagram of the esd protection device 500 in fig. 5A, wherein the same components as those in the embodiments of fig. 1A and 1B are denoted by the same reference numerals and their descriptions are omitted. The embodiment shown in fig. 5A and 5B differs from the previously described embodiment of fig. 1A and 1B in that the first conductivity type is P-type and the second conductivity type is N-type.

According to some embodiments, as shown in fig. 5A, the first heavily doped region 132 and the second heavily doped region 134 are electrically connected together to a ground line (VSS), and the third heavily doped region 136 is electrically connected to a power line (VDD). According to some embodiments, the power line (VDD) and the ground line (VSS) provide high and low potentials, respectively, to the semiconductor devices protected by the ESD protection device 500.

According to some embodiments, as shown in fig. 5A and 5B, a PN junction exists between the second heavily doped region 134 and the first doped region 108, and a PN junction exists between the second well 106 and the first doped region 108. Thus, the second heavily doped region 134, the first doped region 108, and the second well 106 form a parasitic Bipolar Junction Transistor (BJT). According to some embodiments, the bipolar junction transistor is an NPN bipolar junction transistor. According to some embodiments, the third heavily doped region 136 is the collector C of the bipolar junction transistor, the first doped region 108 is the base B of the bipolar junction transistor, and the second heavily doped region 134 is the emitter E of the bipolar junction transistor.

According to some embodiments, the breakdown voltage of the PN junction between the second well 106 and the first doped region 108 is lower than the operating voltage of the semiconductor device protected by the esd protection device 500. When an esd event occurs from the power line (VDD), since the PN junction between the second well 106 and the first doped region 108 collapses at a lower voltage to generate a reverse current, static electricity is discharged from the power line (VDD) to the ground line (VSS) through the bipolar junction transistor of the esd protection device 500, but not through the protected semiconductor device. Thus, the ESD protection device 500 protects the semiconductor device from damage in the event of ESD.

Furthermore, once the PN junction between the second well 106 and the first doped region 108 breaks down at a lower voltage to generate a reverse current, a potential difference (VEB) is generated between the emitter E (the second heavily doped region 134) and the base B (the first doped region 108), and a large amount of emitter current (IE) flows to the collector C (the third heavily doped region 136), thereby reducing the on-Resistance (RON) of the esd protection device 500. Therefore, the esd protection device 500 quickly discharges static electricity to the ground line (VSS).

Fig. 6A is a schematic cross-sectional view of an esd protection device 600 according to some embodiments of the invention, and fig. 6B is an equivalent circuit diagram of the esd protection device 600 of fig. 6A, wherein the same components as those in the embodiments of fig. 5A and 5B are denoted by the same reference numerals and their descriptions are omitted. The embodiment shown in fig. 6A and 6B differs from the embodiment of fig. 5A and 5B described above in that the esd protection device 600 comprises the isolation component 122 shown in fig. 2A.

According to some embodiments, as shown in fig. 6A and 6B, by forming the isolation feature 122, the first well 104 provides a resistance R2 between the first heavily doped region 132 and the first doped region 108 (base B). According to some embodiments, the resistance R2 is adjusted by changing the dimension D3 of the isolation feature 122. For example, the larger the dimension D3, the larger the resistance R1, and vice versa.

According to some embodiments, once the PN junction between the second well 106 and the first doped region 108 breaks down at a lower voltage to generate a reverse current, there is a potential difference (VEB) between the emitter E (the second heavily doped region 134) and the base B (the first doped region 108). If the resistance R1 of the first well 104 is larger, the potential difference (VEB) between the emitter E and the base B is larger, which further increases the emitter current (IE). Therefore, forming the isolation member 122 further reduces the on-Resistance (RON) of the esd protection device 600, thereby discharging static electricity to the ground line (VSS) more quickly.

Fig. 7A is a schematic cross-sectional view of an esd protection device 700 according to some embodiments of the invention, and fig. 7B is an equivalent circuit diagram of the esd protection device 700 of fig. 7A, wherein the same components as those in the embodiments of fig. 5A and 5B are denoted by the same reference numerals and their descriptions are omitted. The embodiment shown in fig. 7A and 7B differs from the embodiment of fig. 5A and 5B described above in that the esd protection device 700 comprises the gate structure 138 shown in fig. 3A.

According to some embodiments, as shown in fig. 7A, the first heavily doped region 132, the second heavily doped region 134, and the gate structure 138 are electrically connected to a ground line (VSS), and the third heavily doped region 136 is electrically connected to a power line (VDD).

According to some embodiments, when an ESD event occurs on the power line (VDD), the gate structure 138 electrically connected to the power line (VDD) opens the channel region thereunder. Therefore, forming the gate structure 138 further reduces the on-Resistance (RON) of the esd protection device 700, thereby discharging static electricity to the ground (VSS) more quickly.

Fig. 8A is a schematic cross-sectional view of an esd protection device 800 according to some embodiments of the invention, and fig. 8B is an equivalent circuit diagram of the esd protection device 800 of fig. 8A, wherein the same reference numerals are used for the same components as those in the embodiments of fig. 7A and 7B, and descriptions thereof are omitted. The embodiment shown in fig. 8A and 8B differs from the previously described embodiment of fig. 7A and 7B in that the esd protection device 800 comprises the isolation component 122 shown in fig. 6A.

According to some embodiments, once the PN junction between the second well 106 and the first doped region 108 breaks down at a lower voltage to generate a reverse current, there is a potential difference (VEB) between the emitter E (the second heavily doped region 134) and the base B (the first doped region 108). If the resistance R2 of the first well 104 is larger, the potential difference (VEB) between the emitter E and the base B is larger, which further increases the emitter current (IE). Therefore, forming the isolation member 122 further reduces the on-Resistance (RON) of the esd protection device 800, thereby discharging static electricity to the ground line (VSS) more quickly.

In summary, the present invention provides an electrostatic discharge protection device including a parasitic Bipolar Junction Transistor (BJT) formed by a heavily doped region, a medium doped region and a lightly doped well. When an electrostatic discharge event occurs, the PN junction of the well and the undoped region collapses at a lower voltage to generate a reverse current, so that static electricity is discharged through the bipolar junction transistor of the electrostatic discharge protection device and does not pass through the protected semiconductor device. Thus, the ESD protection device protects the semiconductor device from damage during an ESD event.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. An electrostatic discharge protection device, comprising:

a first well and a second well disposed in a semiconductor substrate, wherein the first well has a first conductivity type, and the second well has a second conductivity type, the second conductivity type being opposite to the first conductivity type;

a first doped region disposed in the first well and the second well, wherein the first doped region has the first conductivity type;

a first heavily doped region disposed in the first well, wherein the first heavily doped region has the first conductivity type, and at least a portion of the first heavily doped region is located outside the first doped region; and

a second heavily doped region disposed in the first doped region in the first well, wherein the second heavily doped region has the second conductivity type.

2. The ESD protection device of claim 1, wherein the first doped region has a doping concentration greater than that of the first well and less than that of the second heavily doped region.

3. The ESD protection device of claim 1, wherein the first doped region has a doping concentration greater than that of the second well.

4. The ESD protection device of claim 1, wherein the second heavily doped region is electrically connected to a power line or a ground line together with the first heavily doped region.

5. The esd protection device of claim 1, further comprising:

an isolation component is arranged between the first heavily doped region and the second heavily doped region.

6. The ESD protection device of claim 1, wherein the first heavily doped region is in contact with the second heavily doped region.

7. The esd protection device of claim 1, further comprising:

and a third heavily doped region disposed in the second well, wherein the third heavily doped region has the second conductivity type.

8. The ESD protection device of claim 7, wherein the second heavily doped region is electrically connected to one of a power line and a ground line, and the third heavily doped region is electrically connected to the other of the power line and the ground line.

9. The esd protection device of claim 7, further comprising:

and a second doped region disposed in the second well, wherein the second doped region has the second conductivity type, and the third heavily doped region is disposed in the second doped region.

10. The ESD protection device of claim 9, wherein the second doped region has a concentration greater than the second well and less than the third heavily doped region.

11. The ESD protection device of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

12. The ESD protection device of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

13. An electrostatic discharge protection device, comprising:

a second well disposed in a semiconductor substrate;

a first doped region having a first portion disposed outside the second well and a second portion disposed in the second well;

a second heavily doped region disposed in the first portion of the first doped region; and

a third heavily doped region disposed in the second well;

a first well having a first conductivity type, wherein the first portion of the first doped region is disposed in the first well; and

a first heavily doped region disposed in the first well, wherein the first heavily doped region has the first conductivity type, and at least a portion of the first heavily doped region is located outside the first doped region;

the first doped region has a first conductivity type, and the second well, the second heavily doped region, and the third heavily doped region have a second conductivity type opposite to the first conductivity type.

14. The esd protection device of claim 13, further comprising:

and a gate structure partially covering the first doped region and the second well.

15. The esd protection device of claim 14, wherein the gate structure is disposed between the second heavily doped region and the third heavily doped region.

16. The ESD protection device of claim 14, wherein the gate structure and the second heavily doped region are electrically connected together to one of a power line (VDD) and a ground line (VSS), and the third heavily doped region is electrically connected to the other of the power line (VDD) and the ground line (VSS).

17. The ESD protection device of claim 13, wherein the second well, the first doped region, and the second heavily doped region form a bipolar junction transistor.

18. The esd protection device of claim 17, wherein the second heavily doped region is an emitter of the bjt, the first doped region is a base of the bjt, and the third heavily doped region is a collector of the bjt.