CN117727803A

CN117727803A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN117727803A
Application number: CN202211100417.6A
Authority: CN
Inventors: 罗宗仁; 杨晓莹; 刘兴潮; 陈庆钟
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2022-09-09
Filing date: 2022-09-09
Publication date: 2024-03-19

Abstract

The embodiment of the invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a first deep well, at least two second wells, a plurality of isolation structures, and an implant region. The first deep well is disposed in the semiconductor substrate, wherein the first deep well has a first conductivity type. At least two second wells are disposed on the first deep well, wherein the second wells have a second conductivity type. A plurality of isolation structures cover a portion of the first deep well and surround at least a portion of the second well. The implantation region is positioned on the top surface of the semiconductor substrate, wherein the implantation region is provided with a discontinuous part, and the discontinuous part is overlapped with the first deep well part.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

The present invention relates to semiconductor devices, and more particularly to schottky diodes.

Background

The schottky diode Schottky barrier diode is a semiconductor device having a metal-semiconductor junction (metal-semiconductor junction) where contact of metal with lightly doped semiconductor material results in a contact structure (schottky contact) similar to a PN junction that can be used to fabricate the schottky diode. The schottky diode can conduct current carriers when the schottky diode is forward biased (i.e. positive voltage is applied to the anode and negative voltage is applied to the cathode), and can not conduct current carriers when the schottky diode is reverse biased (i.e. negative voltage is applied to the anode and positive voltage is applied to the cathode), so that the schottky diode has the same unidirectional conduction characteristic as a common PN junction diode. In addition, since the schottky diode is a single carrier movement, it has a relatively low threshold voltage in forward bias and very fast response in forward and reverse bias switching. In practice, schottky diodes are not ideal devices and a small amount of reverse leakage current flows. The reverse leakage current can affect the performance of the circuit, reducing the efficiency of the circuit. To reduce the reverse leakage current, argon ions are implanted in the anode region, but this reduces the on-current of the schottky diode.

In view of the foregoing, there is a need for a new schottky diode that can reduce the reverse leakage current while still compromising the on current.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a semiconductor substrate, a first deep well, at least two second wells, a plurality of isolation structures, and an implant region. The first deep well is arranged in the semiconductor substrate, wherein the first deep well has a first conductivity type; at least two second wells are disposed on the first deep well, wherein the second wells have a second conductivity type; a plurality of isolation structures covering a portion of the first deep well and surrounding at least a portion of the second well; the implant region is located in the first deep well and the second well, wherein the implant region has a discontinuous portion that partially overlaps the first deep well.

The invention can avoid the problem that the on current of the Schottky diode is reduced and can improve the leakage in the off state.

Drawings

The aspects of the embodiments of the present invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale and are merely illustrative in accordance with practice standard in the industry. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to improve the clarity of presentation for embodiments of the invention.

Fig. 1 is a schematic top view of a semiconductor device according to some embodiments of the invention.

Fig. 2 is a schematic cross-sectional view taken along line A-A' of the semiconductor device of fig. 1, in accordance with some embodiments of the present invention.

Fig. 3 is a graph comparing the on-current of a semiconductor device according to some embodiments of the present invention with that of a conventional schottky diode.

Fig. 4 is a diagram showing a comparison of the turn-off of a semiconductor device according to some embodiments of the present invention and a conventional schottky diode.

Reference numerals and signs

200 semiconductor substrate

201 top surface

206 first deep well

206E,208-1E,208-2E,208-3E,218-1E,218-2E,218-3E: boundary

204B,206B,208B,210B,211B,218B, bottom surface

208 second well

208-1,208-2,208-3 second well portion

204 isolation structure

210 third well

211 fourth well

211-1,211-2,211-3 fourth well portion

212,216, junction doped regions

218 implantation region

218-1,218-2,218-3 implant region portion

220-1,220-2 discontinuous portions

222 gate dielectric layer

224 gate electrode layer

226 gate spacer

228 gate structure

229 conductive parts

230 anode region

232 cathode region

302,304,402,404 data point population

500 semiconductor device

A-A': tangent line

Detailed Description

The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the invention. However, the present disclosure may be embodied in a variety of different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity and the same or similar reference numbers denote the same or similar elements in the various drawings.

Embodiments of the present invention provide a semiconductor device, such as a schottky diode (Schottky barrier diode). An implant region (implantation region) is provided in the semiconductor device that partially covers the anode region, the implant region being located only in the second well for clamping off-state leakage current (off-state leakage current), and no implant region being present in the first deep well for conducting on-state current. Therefore, the problem that the on current of the Schottky diode is reduced and the off state leakage is improved can be avoided.

Fig. 1 is a schematic top view of a semiconductor device 500 according to some embodiments of the invention. Fig. 2 is a schematic cross-sectional view taken along line A-A' of the semiconductor device 500 of fig. 1, in accordance with some embodiments of the present invention. For illustration, fig. 1 shows only a part of the components, the remaining components being visible in the schematic cross-section of fig. 2. In some embodiments, the semiconductor device 500 includes a schottky diode. As shown in fig. 1 and 2, in some embodiments, the semiconductor device 500 includes a semiconductor substrate 200, a first deep well 206, a second well 208, an isolation structure 204, and an implant region 218.

In some embodiments, the semiconductor substrate 200 includes an elemental semiconductor, such as silicon (Si), germanium (Ge), or the like; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or the like; an alloy semiconductor such as silicon germanium alloy (SiGe), gallium arsenide phosphide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), indium gallium phosphide alloy (GaInP), indium gallium phosphide alloy (GaInAsP), or a combination of the foregoing. In addition, the semiconductor substrate 200 may also include an insulating layer-over-semiconductor (semiconductor on insulator, SOI). In some embodiments, the conductivity type of the semiconductor substrate 200 may be P-type or N-type according to design requirements.

As shown in fig. 1 and 2, a first deep well 206 and a plurality of second wells 208 are provided in the semiconductor substrate 200. The plurality of second wells 208 are disposed on the first deep well 206 and outside the first deep well 206, respectively. The second well 208 disposed on the first deep well 206 includes second well portions 208-1,208-2, 208-3. In the top view shown in fig. 1, a boundary 206E of the first deep well 206 surrounds a second well 208 disposed within the first deep well 206. In the cross-sectional view shown in fig. 2, a bottom surface 206B of the first deep well 206 is located below a bottom surface 208B of the second well 208. In other words, the first deep well 206 surrounds the second well 208 disposed on the first deep well 206.

In some embodiments, the second well 208 surrounded by the first deep well 206 has a shape in which a plurality of annular portions are adjacently arranged in a top view as shown in fig. 1. In some embodiments, the second well 208 surrounded by the first deep well 206 includes a plurality of finger-shaped second well portions 208-1,208-2,208-3 that are substantially parallel to each other, spaced apart from each other in the cross-sectional view shown in fig. 2, for example, in a zig-zag shape. In some embodiments, the second well 208 may not include the second well portion 208-2 between the second well portions 208-1, 208-3, and thus is annular in top view as shown in fig. 1.

As shown in fig. 1 and 2, the second well 208 disposed outside the first deep well 206 surrounds the first deep well 206, and the second well 208 disposed outside the boundary 206E of the first deep well 206 is adjacent to the first deep well 206. In some embodiments, the semiconductor device 500 further includes a wire doped region 216 disposed on the second well 208 outside of the boundary 206E of the first deep well 206.

In some embodiments, the first deep well 206 has a first conductivity type. In some embodiments, the second well 208 and the wire doped region 216 have a second conductivity type opposite the first conductivity type. For example, when the first deep well 206 is an N-type deep well (DNW), the second well 208 is a P-type well (e.g., a P-type high voltage well (HVPW)), and the wire doped region 216 is a P-type wire doped region. However, the present invention is not limited thereto, and those skilled in the art can adjust the present invention according to the actual requirements. In some embodiments, the doping concentration of the wire doped region 216 is greater than the doping concentration of the second well 208, and the doping concentration of the second well 208 is greater than the doping concentration of the semiconductor substrate 200. In some embodiments, the doping concentration of the first deep well 206 is about 1E12 atoms/cm ² To 1E13 atoms/cm ² Between, the doping concentration of the second well 208 is about 1E12 atoms/cm ² To 1E13 atoms/cm ² Between them.

In some embodiments, the on-current flows primarily through the first deep well 206 in the anode region 230 when the semiconductor device 500 is forward biased. In some embodiments, when the semiconductor device 500 is reverse biased, a depletion region is created in the first deep well 206 between the second well portions 208-1,208-2,208-3 in the anode region 230, which has a clamping (pin) effect on off-state leakage. In some embodiments, the semiconductor substrate 200 is electrically connected to the base (Bulk) of the final semiconductor device 500 by the second well 208 outside the first deep well 206 and the wire doped region 216 thereon.

As shown in fig. 1 and 2, the semiconductor device 500 further includes a third well 210 in the semiconductor substrate 200 and a wire doping region 212 disposed on the third well 210. The third well 210 and the wire doped region 212 are disposed on the first deep well 206. The third well 210 and the wire doped region 212 are proximate to the boundary 206E of the first deep well 206 and are disposed on opposite sides of the isolation structure 204 from the second well portions 208-1, 208-3, respectively. The third well 210 and the wire doped region 212 are also disposed on opposite sides of the isolation structure 204 on the boundary 206E of the first deep well 206 from the second well 208 outside the boundary 206E of the first deep well 206, respectively. As shown in fig. 2, bottom surface 210B of third well 210 is located above bottom surface 206B of first deep well 206 and bottom surface 208B of second well 208. As shown in fig. 1 and 2, the third well 210 and the wire doped region 212 directly above it surround the second well 208 on the first deep well 206. In some embodiments, the third well 210 and the wire doped region 212 have a first conductivity type. For example, when the first deep well 206 is an N-type deep well (DNW), the third well 210 is an N-type well (e.g., an N-type low voltage well (NW)), and the wire doped region 212 is an N-type wire doped region. However, the present invention is not limited thereto, and those skilled in the art can adapt to actual needsAnd (5) adjusting. In some embodiments, the doping concentration of the wire doped region 212 is greater than the doping concentration of the third well 210, and the doping concentration of the third well 210 is greater than the doping concentration of the first deep well 206. The first deep well 206 is electrically connected to the cathode region 232 of the final semiconductor device 500 by the third well 210 and the wire doped region 212 thereon. In some embodiments, the doping concentration of the third well 210 is about 1E13 atoms/cm ² To 1E14 atoms/cm ² Between these, the doping concentration of the wiring doped region 212 is about 1E15 atoms/cm ² To 1E16 atoms/cm ² Between them.

As shown in fig. 1 and 2, in one embodiment, the semiconductor device 500 further includes a fourth well 211 in the semiconductor substrate 200. The fourth well 211 is disposed on the second well 208 and includes fourth well portions 211-1,211-2, 211-3. Fourth well portions 211-1,211-2,211-3 are located over second well portions 208-1,208-2,208-3, respectively, and are surrounded by second well portions 208-1,208-2,208-3, respectively. As shown in fig. 2, the bottom surface 211B of the fourth well 211 is located above the bottom surface 208B of the second well 208. In some embodiments, the fourth well 211 has the second conductivity type. For example, when the first deep well 206 is an N-type deep well (DNW), the fourth well 211 is a P-type well (P-type low voltage well (PW), for example). However, the present invention is not limited thereto, and those skilled in the art can adjust the present invention according to the actual requirements. In some embodiments, the doping concentration of the fourth well 211 is greater than the doping concentration of the second well 208 and less than the doping concentration of the wire doped region 216. The second well 208 is electrically connected to the anode region 230 of the final semiconductor device 500 via the fourth well 211 thereon. In some embodiments, the doping concentration of the fourth well 211 is about 1E13 atoms/cm ² To 1E14 atoms/cm ² Between them.

In some embodiments, dopants of the first conductivity type and the second conductivity type may be implanted in the semiconductor substrate 200 using a multi-ion implantation process to form the first deep well 206, the second well 208, the third well 210, the fourth well 211, and the wire doped regions 212,216, respectively. In some embodiments, the dopant of the first conductivity type is, for example, an N-type dopant, which may include phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In some embodiments, dopants of the second conductivity type, e.g., P-typeDopants, which may include boron, gallium, aluminum, indium, boron trifluoride ions (BF ₃ ⁺ ) Or a combination of the above.

As shown in fig. 1 and 2, a plurality of isolation structures 204 are disposed within the first deep well 206, on a boundary 206E of the first deep well 206, and on the semiconductor substrate 200 in the second well 208 outside the first deep well 206. In the cross-sectional view shown in fig. 2, isolation structure 204 within first deep well 206 surrounds second well portions 208-1,208-2,208-3 and partially overlaps second well portion 208-1 and second well portion 208-3, respectively. In some embodiments, bottom surface 206B of first deep well 206 and bottom surface 208B of second well 208 are located below bottom surface 204B of the isolation structure. As shown in fig. 1 and 2, the isolation structures 204 define the formation locations of the anode region 230 and the cathode region 232 of the final semiconductor device 500. In some embodiments, any number of isolation structures 204 may be provided on the semiconductor substrate 200 according to design requirements. In some embodiments, the isolation structures 204 are Field Oxide (FOX) structures formed using a local oxidation of silicon (local oxidation of silicon, LOCOS) process, shallow trench isolation (shallow trench isolation, STI) structures formed using a deposition process, or other suitable isolation structures. In some embodiments, the isolation structures 204 are formed using a thermal oxidation process, including a dry oxidation process, a wet oxidation process, or other suitable thermal oxidation process.

As shown in fig. 1 and 2, the implantation region 218 is disposed on the surface of the semiconductor substrate 200 and is located in the first deep well 206 and the second well 208. In some embodiments, the top view shape of the implant region 218 substantially overlaps the top view shape of the second well 208 over the first deep well 206, as shown in fig. 1. As shown in fig. 1 and 2, the implanted region 218 has a ring shape or a shape in which a plurality of ring-shaped regions are adjacently arranged in a plan view as shown in fig. 1, for example, a zigzag shape. In some embodiments, the implant region 218 includes a plurality of finger-shaped implant region portions 218-1,218-2,218-3 that are substantially parallel to one another, spaced apart from one another in the cross-sectional view shown in FIG. 2, and disposed corresponding to the second well portions 208-1,208-2, 208-3. For example, the implant region portion 218-1 is disposed corresponding to the second well portion 208-1 and may extend to the isolation structure 204 of an adjacent second well portion 208-1. In some embodiments, the boundary 208-1E of the second well portion 208-1, the boundary 208-2E of the second well portion 208-2, and the boundary 208-3E of the second well portion 208-3 are located at the corresponding boundary 218-1E of the implant region portion 218-1, the boundary 218-2E of the implant region portion 218-2, and the boundary 218-3E of the implant region portion 218-3, respectively, and one skilled in the art can adjust the relative positions of the second well boundaries 208-1E,208-2E,208-3E and the implant region boundaries 218-1E,218-2E,218-3E, as the invention is not limited thereto.

As shown in fig. 1 and 2, the implant region 218 has discontinuities 220-1,220-2, with the discontinuities 220-1,220-2 partially overlapping the first deep well 206. For example, the discontinuous portion 220-1 of the implant region 218 is located in the first deep well 206 between the second well portions 208-1,208-2 of the second well 208. The discontinuous portion 220-2 of the implant region 218 is located in the first deep well 206 between the second well portions 208-2,208-3 of the second well 208. In some embodiments, the discontinuous portions 220-1,220-2 of the implanted region 218 completely overlap at least a portion of the first deep well 206 surrounded by the second well 208. Alternatively, the portion of the first deep well 206 surrounded by the second well 208 may partially overlap with the discontinuous portions 220-1,220-2 of the implanted region 218. In some embodiments, the discontinuous portions 220-1,220-2 of the implanted region 218 do not overlap at all with the second well portions 208-1,208-2,208-3 of the second well 208. As shown in fig. 2, a bottom surface 218B of the implant region 218 is above the bottom surface 204B of the isolation structure 204. In some embodiments, an ion implantation process may be used to implant ions of argon, silicon, germanium, fluorine, nitrogen, selenium, sulfur, or combinations thereof into the region of the semiconductor substrate 200 proximate the top surface 201 to form the implanted region 218 and to convert the material of the semiconductor substrate 200 within the implanted region 218 into an amorphous semiconductor material, such as amorphous silicon (α -Si). Thus, the implanted region 218 may also be considered as an amorphous semiconductor material region 218. The amorphous semiconductor material has a high resistance to form a schottky barrier, which reduces the current flowing through the anode region 230. In some embodiments, the implant region 218 has a doping concentration of approximately 1E1 atoms/cm ² To 1E15 atoms/cm ² Between them.

As shown in fig. 1 and 2, the semiconductor device 500 further includes a gate structure 228 disposed on the semiconductor substrate 200 in the first deep well 206 and extending to cover the isolation structure 204 and the adjacent second well 208. In the top view shown in fig. 1, the gate structure 228 surrounds the second well 208 and partially overlaps the isolation structure 204 and an adjacent second well 208 within the first deep well 206 and surrounding the second well 208. In some embodiments, the gate structure 228 includes a gate dielectric layer 222 disposed on the semiconductor substrate 200, a gate electrode layer 224 disposed over the gate dielectric layer 222, and a gate spacer 226 disposed on sidewalls of the gate dielectric layer 222 and the gate electrode layer 224. The gate structure 228 is electrically connected to the anode region 230 of the semiconductor device, and has an electric field dispersing effect when the semiconductor device 500 is under reverse bias, so as to improve the voltage breakdown performance of the semiconductor device 500 under reverse bias.

In some embodiments, the gate dielectric layer 222 includes silicon oxide (si oxide), silicon nitride (si nitride), silicon oxynitride (silicon oxynitride), a high-k material, other suitable dielectric materials, and/or combinations thereof. The high dielectric constant material may be, for example, hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, and/or combinations thereof or the like. In some embodiments, the gate dielectric layer 222 may be formed on the semiconductor substrate 200 using an oxidation process, a deposition process, or other suitable process.

In some embodiments, gate electrode layer 224 comprises polysilicon, amorphous silicon, a metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, other suitable metals, or combinations thereof), a metal alloy, a metal nitride (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, other suitable metal nitrides, or combinations thereof), a metal oxide (ruthenium oxide, indium tin oxide, other suitable metal oxides, or combinations thereof), other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 224 may be doped in-situ (in-situ doping).

In some embodiments, the gate spacers 226 comprise silicon oxide (si oxide), silicon nitride (si nitride), silicon oxynitride (silicon oxynitride), low-k materials, other suitable dielectric materials, and/or combinations thereof. In some embodiments, an oxidation process, a deposition process, or other suitable process may be used to form gate spacers 226 on sidewalls of gate dielectric layer 222 and gate electrode layer 224.

As shown in fig. 1 and 2, the semiconductor device 500 further includes a conductive member 229 disposed on the semiconductor substrate 200 and contacting (physically contacting) the second well 208 on the first deep well 206 and a portion of the first deep well 206 surrounded by the second well 208. Also, in one embodiment, the conductive feature 229 contacts the discontinuous portions 220-1,220-2 of the implanted region 218. In one embodiment, conductive feature 229 contacts second well portion 208-2 of second well 208, first deep well 206 between second well portions 208-1,208-2, and first deep well 206 between second well portions 208-2, 208-3. In some embodiments, the conductive feature 229 is electrically connected to the gate structure 228. In some embodiments, the conductive member 229 may serve as an anode electrode of the semiconductor device 500, which includes a metal (e.g., nickel (Ni), cobalt (Co), platinum (Pt), titanium (Ti), tungsten (W), aluminum (Al), a combination thereof, or the like) to form a metal silicide with the semiconductor substrate 200. In some embodiments, the conductive feature 229 may also comprise doped polysilicon. In some embodiments, the conductive features 229 may be formed using a deposition process (e.g., physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), sputtering, or combinations of the above) and a subsequent patterning process.

In some embodiments, the semiconductor device 500 is formed by providing the semiconductor substrate 200, and then forming the isolation structure 204 in the semiconductor substrate 200. Next, a first deep well 206 is formed in the semiconductor substrate 200. Then, a second well 208 is formed on the first deep well 206. Thereafter, a fourth well 211 is formed on the second well 208. Next, a third well 210 is formed on the first deep well 206. Then, a gate structure 228 is formed on the semiconductor substrate 200 within the first deep well 206. Thereafter, a wire doped region 212 is formed over the first deep well 206. Next, an implant region 218 is formed on the surface of the semiconductor substrate 200 and in the first deep well 206 and the second well 208. Then, a conductive member 229 is formed on the semiconductor substrate 200. Finally, the semiconductor device 500 of the embodiment of the present invention is formed.

As shown in fig. 1 and 2, a portion of the first deep well 206 between the second well 208 and the second well portions 208-1,208-2,208-3 serves as an anode region 230 of a semiconductor device 500, such as a schottky diode. In other words, in the top view shown in fig. 1, the second well 208 and the portion of the first deep well 206 around which the second well 208 surrounds act as the anode region 230 of the semiconductor device 500, e.g., a schottky diode. Also, portions of the first deep well 206 and the third well 210 thereon on opposite sides of the isolation structure 204 from the second well portions 208-1, 208-3 of the second well 208 serve as the cathode region 232 of the semiconductor device 500, e.g., a schottky diode. In other words, the portion of the first deep well 206 located between the boundary 206E of the first deep well 206 and the second well portions 208-1, 208-3 of the second well 208 and the third well 210 thereon serve as the cathode region 232 of the semiconductor device 500, such as a schottky diode. In some embodiments, the anode region 230 of the semiconductor device 500 includes discontinuous portions 220-1,220-2 of the implanted region 218. In other words, a portion of the anode region 230 of the semiconductor device 500 does not have the implant region 218.

Fig. 3 is a graph showing on-current distribution of a semiconductor device according to some embodiments of the present invention and a schottky diode according to an opposite embodiment. The data point population 302 in fig. 3 represents the on-current of the opposite embodiment (the implant region completely covers the anode region), and the data point population 304 represents the on-current of the semiconductor device 500, such as a schottky diode, according to some embodiments of the present invention (the implant region has a discontinuous portion). As can be seen from fig. 3, compared to the schottky diode of the related embodiment, the semiconductor device 500 of some embodiments of the present invention has no injection region (or only a portion of the injection region) in the first deep well 206 through which the on-current flows, so that the resistance of a portion of the anode region (schottky barrier (Schottky barrier height)) can be reduced, and thus the on-current of the semiconductor device 500 can be significantly improved.

Fig. 4 is a graph showing the cumulative percentage of off-state current (leakage) for a semiconductor device according to some embodiments of the present invention and a schottky diode according to an opposite embodiment. The data point population 402 in fig. 4 represents the on-current of the opposite embodiment (the implant region completely covers the anode region), and the data point population 404 represents the on-current of the semiconductor device 500, such as a schottky diode, according to some embodiments of the present invention (the implant region has a discontinuous portion). As can be seen from fig. 4, the second well 208 through which the off-state current (leakage) flows in the semiconductor device 500 according to some embodiments of the present invention still has the injection region, so that the off-state current of the semiconductor device 500 is lower than that of the related embodiments.

Embodiments of the present invention provide a semiconductor device, such as a schottky diode (Schottky barrier diode). The semiconductor device includes an implant region (Ar ion implantation region) overlying a portion of the anode region, the implant region being located only in the second-type well for clamping off-state current (leakage) to form an amorphous semiconductor material region therein having a higher resistance, thereby increasing the schottky barrier and reducing the off-state leakage of the semiconductor device 500. And conducting an on-current in the semiconductor device) has no implanted region in the first type deep well, adverse effects on the on-current can be reduced. Therefore, the semiconductor device of the embodiment of the invention can simultaneously improve the problem of off-state leakage under the condition of avoiding the reduction of the on-current of the Schottky diode.

Although the present invention has been described in terms of the foregoing embodiments, it is not limited thereto. Those skilled in the art will appreciate that many modifications and variations may be made without departing from the spirit and scope of the invention. The scope of the invention is therefore defined by the appended claims.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first deep well disposed in the semiconductor substrate; wherein the first deep well has a first conductivity type;

at least two second wells disposed on the first deep well; wherein the second well has a second conductivity type;

at least one isolation structure covering part of the first deep well and surrounding at least part of the second well; and

an implantation region located on a top surface of the semiconductor substrate; wherein the implant region has a discontinuity that overlaps the first deep well portion.

2. The semiconductor device of claim 1, wherein the discontinuous portion of the implant region is located in the first deep well between the second wells.

3. The semiconductor device of claim 1, wherein said second well surrounds the discontinuous portion of the implant region.

4. The semiconductor device of claim 1, wherein the implant region completely overlaps a portion of the first deep well surrounded by the second well.

5. The semiconductor device of claim 1, wherein the discontinuous portion of the implant region is completely non-overlapping with the second well.

6. The semiconductor device of claim 1, wherein a bottom surface of the implant region is above a plurality of bottom surfaces of the isolation structures.

7. The semiconductor device of claim 1, wherein the implant region extends within the isolation structure.

8. The semiconductor device of claim 1, wherein the second well partially overlaps an adjacent isolation structure.

9. The semiconductor device according to claim 1, further comprising:

and a gate structure arranged on the semiconductor substrate in the first deep well and extending to cover one of the isolation structures and one of the adjacent second wells.

10. The semiconductor device according to claim 9, further comprising:

and a conductive member disposed on the semiconductor substrate and contacting the second well and the first deep well between the second wells.

11. The semiconductor device of claim 10, wherein said conductive member contacts said discontinuous portion of said implanted region.

12. The semiconductor device of claim 10, wherein the conductive member is electrically connected to the gate structure.

13. The semiconductor device of claim 10, wherein a portion of the first deep well between the second well and the second well acts as an anode region of a schottky diode and a portion of the first deep well on an opposite side of the isolation structure from the second well acts as a cathode region of the schottky diode.

14. The semiconductor device of claim 13, wherein the anode region of the schottky diode comprises the discontinuous portion of the implanted region.

15. The semiconductor device of claim 10, wherein the implant region comprises a plurality of ions of argon, silicon, germanium, fluorine, nitrogen, selenium, sulfur, or a combination thereof.