TWI703648B - Underfill filling method of semicondctor package and filling equipment - Google Patents

Underfill filling method of semicondctor package and filling equipment Download PDF

Info

Publication number
TWI703648B
TWI703648B TW108122152A TW108122152A TWI703648B TW I703648 B TWI703648 B TW I703648B TW 108122152 A TW108122152 A TW 108122152A TW 108122152 A TW108122152 A TW 108122152A TW I703648 B TWI703648 B TW I703648B
Authority
TW
Taiwan
Prior art keywords
primer
chip
negative pressure
pressure suction
substrate
Prior art date
Application number
TW108122152A
Other languages
Chinese (zh)
Other versions
TW202101610A (en
Inventor
褚漢明
陳盈靜
游舜名
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Priority to TW108122152A priority Critical patent/TWI703648B/en
Application granted granted Critical
Publication of TWI703648B publication Critical patent/TWI703648B/en
Publication of TW202101610A publication Critical patent/TW202101610A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The present invention relates to an underfill filling method of Semicondctor package and filling equipment. In the underfill filling method, the underfill is released on a substrate and close to one side of a chip to flow into a space between the chip and the substrate. At the time, a negative pressure is provided to the opposite side of the chip to increase a flowing speed of the underfill. Therefore, an overflow area of the underfill is controlled to be reduced and a lateral size of the semiconductor package is decreased.

Description

半導體封裝結構之底膠填充方法及其底膠填充設備Bottom glue filling method of semiconductor packaging structure and bottom glue filling equipment

本發明係關於一種半導體封裝結構之底膠填充方法，尤指一種半導體封裝結構之底膠填充方法及其底膠填充設備。 The present invention relates to a primer filling method of a semiconductor packaging structure, in particular to a primer filling method of a semiconductor packaging structure and its primer filling equipment.

目前覆晶半導體封裝製程中，如圖6A所示，在晶片31與基板30對接後，會使用點膠機40，由點膠機40沿著晶片周緣注入流動型底膠41(undferfill)，使底膠41透過毛細現象擴大至該晶片31與該基板30之間的空間，速度較慢；再如圖6B所示，為了填滿該晶片31與該基板30之間的全部空間，底膠41的使用量會大於空間總量，也造成底膠41會自晶片31四周向外溢流，如圖6C所示。 In the current flip-chip semiconductor packaging process, as shown in FIG. 6A, after the wafer 31 is docked with the substrate 30, a dispenser 40 is used, and the dispenser 40 injects a flow-type primer 41 (undferfill) along the periphery of the wafer to make The primer 41 expands to the space between the chip 31 and the substrate 30 through the capillary phenomenon, and the speed is relatively slow; and as shown in FIG. 6B, in order to fill the entire space between the chip 31 and the substrate 30, the primer 41 The usage amount of is greater than the total amount of space, which also causes the primer 41 to overflow from the periphery of the chip 31, as shown in FIG. 6C.

如圖6D所示，底膠41的外溢區域會佔據基板一定面積，該外溢區域寬度為d1，對半導體封裝從業人員來說，該外溢區域為設計死區，即無法設置其他元件或材料層，而相對增加半導體封裝結構的橫向尺寸；因此，對於目前底膠的填充方式有必要進一步改良之。 As shown in Figure 6D, the overflow area of the primer 41 occupies a certain area of the substrate. The width of the overflow area is d1. For semiconductor packaging practitioners, the overflow area is a design dead zone, that is, other components or material layers cannot be set. The lateral size of the semiconductor packaging structure is relatively increased; therefore, it is necessary to further improve the current filling method of the primer.

有鑑於上述目前半導體封裝結構使用的底膠造成的諸多問題，本發明的主要目的係提供一種半導體封裝結構之底膠填充方法及其底膠填充設備。 In view of the many problems caused by the above-mentioned primers currently used in semiconductor packaging structures, the main purpose of the present invention is to provide a primer filling method for semiconductor packaging structures and a primer filling equipment thereof.

欲達上述目的所使用的主要技術手段係令該半導體封裝結構之底膠填充方法包含：(a)將底膠釋放於一基板上並靠近一晶片的一側邊位置；其中該晶片係對接於該基板上，該晶片與該基板之間形成有空間；(b)於該晶片的相對另一側邊位置提供一負壓吸力。一晶片，係包含有一主動面，該主動面上包含有多個接墊；以及(c)當底膠自上述提供負壓吸力所在的側邊處流出時，回收溢流出的底膠。 The main technical means used to achieve the above purpose is to make the underfilling method of the semiconductor package structure include: (a) releasing the underfill on a substrate and close to one side of a chip; wherein the chip is butted to On the substrate, a space is formed between the wafer and the substrate; (b) a negative pressure suction force is provided at the opposite side of the wafer. A chip includes an active surface that includes a plurality of pads; and (c) when the primer flows out from the side where the negative pressure suction is provided, the overflowed primer is recovered.

由上述可知，本發明的底膠填充方法係主要在底膠釋放在基板上並往晶片與基板之間空間流入時，在該晶片另一側提供負壓吸力，加速底膠流經該空間的速度，也可控制該底膠外溢至晶片四側邊之面積可被控制並減縮，有助於該半導體封裝結構的橫向尺寸縮減。 It can be seen from the above that the primer filling method of the present invention mainly provides negative pressure suction on the other side of the wafer when the primer is released on the substrate and flows into the space between the wafer and the substrate to accelerate the flow of the primer through the space. The speed can also be controlled, and the area of the primer overflow to the four sides of the chip can be controlled and reduced, which helps to reduce the lateral size of the semiconductor packaging structure.

欲達上述目的所使用的主要技術手段係令該底膠填充設備包含：一底膠釋放頭；一底膠供應單元，係與該底膠釋放頭連通，經由設定由該底膠供應單元輸出足量的底膠給該底膠釋放頭，由該底膠釋放頭流出底膠；一負壓吸力頭，係與該底膠釋放頭設置在相對位置，以提供一負壓吸力以及一底膠回收單元，係與該負壓吸力頭連通，透過該負壓吸力頭吸取底膠。 The main technical means used to achieve the above purpose is to make the primer filling equipment include: a primer release head; a primer supply unit connected with the primer release head, and the primer supply unit outputs enough through settings The amount of primer is given to the primer release head, and the primer discharges from the primer release head; a negative pressure suction head is arranged at an opposite position to the primer release head to provide a negative pressure suction and a primer recovery The unit is connected with the negative pressure suction head, and sucks the primer through the negative pressure suction head.

本發明底膠填充設備係主要該底膠釋放頭及該負壓吸力頭分別置於該晶片兩相對側邊，當底膠會自該晶片側邊流入晶片與其接合的基板之間空間，該晶片的相對側邊所提供負壓吸力可加速底膠流動的速度，也可控制該 底膠外溢至晶片四側邊之面積可被控制並減縮，有助於該半導體封裝結構的橫向尺寸縮減。 The primer filling equipment of the present invention is mainly that the primer releasing head and the negative pressure suction head are respectively placed on two opposite sides of the chip. When the primer flows from the chip side into the space between the chip and its bonded substrate, the chip The negative pressure suction provided by the opposite side of the base rubber can accelerate the flow rate of the primer, and can also control the The area of the primer overflow to the four sides of the chip can be controlled and reduced, which helps reduce the lateral size of the semiconductor package structure.

10:載板 10: Carrier board

11:基板 11: substrate

12:晶片 12: chip

13、13a:底膠 13, 13a: primer

20:底膠填充設備 20: Primer filling equipment

21:底膠釋放頭 21: Base glue release head

22:底膠供應單元 22: Primer supply unit

23:負壓吸力頭 23: Negative pressure suction head

231:長管 231: long tube

231a:L形長管 231a: L-shaped long tube

232:穿孔 232: Piercing

24:底膠回收單元 24: primer recovery unit

30:基板 30: substrate

31:晶片 31: chip

40:點膠機 40: Dispenser

41:底膠 41: primer

圖1：本發明底膠填充設備之第一實施例對一半導體封裝結構進行底膠填充的示意圖。 Figure 1: A schematic diagram of underfilling a semiconductor package structure in the first embodiment of the underfill filling equipment of the present invention.

圖2：圖1底膠填充設備的操作示意圖。 Figure 2: Figure 1 Schematic diagram of the operation of the primer filling equipment.

圖3A：本發明半導體封裝結構的剖面圖。 Fig. 3A: A cross-sectional view of the semiconductor package structure of the present invention.

圖3B：圖3A的俯視平面圖。 Figure 3B: Top plan view of Figure 3A.

圖4A：本發明底膠填充設備之第二實施例對一半導體封裝結構進行底膠填充的側視示意圖。 4A: A schematic side view of the second embodiment of the primer filling equipment of the present invention for underfilling a semiconductor package structure.

圖4B：本發明底膠填充設備之第二實施例對一半導體封裝結構進行底膠填充的俯視示意圖。 4B: A schematic top view of underfilling a semiconductor package structure in the second embodiment of the underfill filling equipment of the present invention.

圖5A：本發明底膠填充設備之第三實施例對一半導體封裝結構進行底膠填充的側視示意圖。 FIG. 5A: A schematic side view of the third embodiment of the primer filling equipment of the present invention for underfilling a semiconductor package structure.

圖5B：本發明底膠填充設備之第三實施例對一半導體封裝結構進行底膠填充的俯視示意圖。 FIG. 5B: A schematic top view of the third embodiment of the primer filling device of the present invention performing primer filling on a semiconductor package structure.

圖6A及圖6B：既有底膠填充設備對一半導體封裝結構進行底膠填充的操作示意圖。 6A and 6B are schematic diagrams of the operation of underfilling a semiconductor package structure by the existing underfilling equipment.

圖6C：既有半導體封裝結構的側視剖面圖。 Figure 6C: A side cross-sectional view of a conventional semiconductor package structure.

圖6D：圖6C的俯視平面圖。 Fig. 6D: a top plan view of Fig. 6C.

本發明係針對半導體封裝結構之底膠填充方法及其底膠填充設備提出改良，並以實施例配合圖式詳加說明本發明技術內容如下。 The present invention proposes an improvement to the primer filling method of the semiconductor package structure and the primer filling equipment thereof, and the technical content of the present invention is described in detail with embodiments and drawings as follows.

首先請參閱圖1所示，係為本發明一底膠填充設備20對一半導體封裝結構進行底膠填充之示意圖，實際封裝作業中，於一載板10上設置有多個半導體封裝結構，圖中僅以單一半導體封裝結構進行說明。該半導體封裝結構係包含有一基板11及一晶片12，該晶片12係與該基板11對向接合；於本實施例，該半導體封裝結構為一覆晶封裝結構。 First, please refer to FIG. 1, which is a schematic diagram of underfilling a semiconductor package structure by a primer filling device 20 of the present invention. In actual packaging operations, a plurality of semiconductor package structures are arranged on a carrier board 10. Only a single semiconductor package structure is used in the description. The semiconductor package structure includes a substrate 11 and a chip 12, and the chip 12 is oppositely bonded to the substrate 11; in this embodiment, the semiconductor package structure is a flip chip package structure.

上述底膠填充設備20係包含有一底膠釋放頭21、一底膠供應單元22、一負壓吸力頭23及一底膠回收單元24；其中該底膠釋放頭21係與該底膠提供應單元22連通，經設定由該底膠供應單元22輸出足量的底膠13給該底膠釋放頭21，再由該底膠釋放頭21流出底膠13；該負壓吸力頭23則設置與該底膠釋放頭21的相對位置，以提供負壓吸力，加速底膠的流動。又該負壓吸力頭23再與該底膠回收單元24連通，如圖2所示，該負壓吸力頭23將溢流的底膠13a回吸至該底膠回收單元24；此外，該底膠回收單元24可進一步與該底膠供應單元22連通，將回收的底膠13a再補充回該底膠供應單元22。 The above-mentioned primer filling equipment 20 includes a primer releasing head 21, a primer supply unit 22, a negative pressure suction head 23, and a primer recycling unit 24; wherein the primer releasing head 21 is connected to the primer providing application The unit 22 is connected. After setting, the primer supply unit 22 outputs a sufficient amount of primer 13 to the primer release head 21, and then the primer release head 21 flows out the primer 13; the negative pressure suction head 23 is set with The relative position of the primer release head 21 can provide negative pressure suction and accelerate the flow of the primer. In addition, the negative pressure suction head 23 is in communication with the bottom rubber recovery unit 24. As shown in FIG. 2, the negative pressure suction head 23 sucks the overflowing primer 13a back to the bottom rubber recovery unit 24; in addition, the bottom rubber The glue recovery unit 24 can further communicate with the primer supply unit 22 to replenish the recovered primer 13a back to the primer supply unit 22.

請參閱圖2所示，當該底膠釋放頭21及該負壓吸力頭23分別置於該基板11上並分別靠近該晶片12兩相對側邊，該底膠釋放頭21受控制沿著其所在之晶片12側邊移動並均勻地釋放底膠，在基板11上的底膠13會自該晶片12側邊流入晶片12與其接合的基板13之間空間，並藉由毛細現象往該晶片12的相對側邊流動；此時，該負壓吸力頭23設置在該晶片12的相對側邊並提供一負壓吸力，如此可加速底膠13流動的速度。當底膠13a自該負壓吸力頭所在該晶片的相對側邊流出，即被該負壓吸力頭23吸取並回收至該底膠回收單元24；如此，如圖3A及圖3B所示，該底膠13外溢至晶片四側邊之面積可被控制並減縮，即底膠外溢區域的寬度d2小於圖6D所示之底膠外溢區域寬度d1。 Please refer to FIG. 2, when the primer release head 21 and the negative pressure suction head 23 are respectively placed on the substrate 11 and are respectively close to two opposite sides of the chip 12, the primer release head 21 is controlled along its The side of the chip 12 where it is located moves and uniformly releases the primer. The primer 13 on the substrate 11 flows from the side of the chip 12 into the space between the chip 12 and the substrate 13 to which it is bonded, and wicks to the chip 12 At this time, the negative pressure suction head 23 is arranged on the opposite side of the wafer 12 and provides a negative pressure suction, so that the flow rate of the primer 13 can be accelerated. When the primer 13a flows out from the opposite side of the chip where the negative pressure suction head is located, it is sucked by the negative pressure suction head 23 and recovered to the primer recovery unit 24; thus, as shown in FIGS. 3A and 3B, the The overflow area of the primer 13 to the four sides of the chip can be controlled and reduced, that is, the width d2 of the primer overflow area is smaller than the width d1 of the primer overflow area shown in FIG. 6D.

請參閱圖4A及圖4B所示，係為該負壓吸力頭23的另一實施例，該負壓吸力頭23係為一長管231，該長管231可平置於基板11上並靠近該晶片12側邊，其對應該晶片12側邊形成有多個小穿孔232，以提供負壓吸力及吸收底膠；於本實施例，該長管231剖面呈三角形。 Please refer to FIGS. 4A and 4B, which is another embodiment of the negative pressure suction head 23. The negative pressure suction head 23 is a long tube 231, which can be placed flat on the substrate 11 and close to A plurality of small perforations 232 are formed on the side of the wafer 12 corresponding to the side of the wafer 12 to provide negative pressure suction and absorb primer; in this embodiment, the cross section of the long tube 231 is triangular.

請參閱圖5A及圖5B所示，係為該負壓吸力頭23的又一實施例，該負壓吸力頭23係為一L形長管231a，該L形長管231a可平置於基板11上並靠近該晶片12二相鄰側邊，其對應該晶片12的側邊形成有多個小穿孔232，以提負壓吸力及吸收底膠；於本實施例，該L形長管231a剖面呈三角形。 Please refer to FIGS. 5A and 5B, which is another embodiment of the negative pressure suction head 23. The negative pressure suction head 23 is an L-shaped long tube 231a, and the L-shaped long tube 231a can be placed on the substrate. 11 and close to the two adjacent sides of the wafer 12, a plurality of small perforations 232 are formed on the side of the wafer 12 corresponding to the sides of the wafer 12 to increase the negative pressure suction and absorb the primer; in this embodiment, the L-shaped long tube 231a The section is triangular.

由上述說明可知，於一晶片12對應接合於一基板11後，該晶片11與該基板12之間形成有空間，如圖1及圖2所示，本發明半導體封裝結構之底膠填充方法係首先將底膠13釋放於該晶片12的一側邊位置，並於晶片12相對一側邊位置提供一負壓吸力，加速底膠13流經該空間的速度。於本實施例，該底膠13可沿著晶片12單一側邊釋放或兩相鄰側邊釋放；同理，負壓吸力也可在相對的單一側邊處提供，或另兩相鄰側邊提供，以加速底膠13流動速度，以縮短底膠填充時間。 It can be seen from the above description that after a chip 12 is correspondingly bonded to a substrate 11, a space is formed between the chip 11 and the substrate 12. As shown in FIGS. 1 and 2, the primer filling method of the semiconductor package structure of the present invention is First, the primer 13 is released on one side of the chip 12, and a negative pressure suction is provided at the opposite side of the chip 12 to accelerate the speed of the primer 13 flowing through the space. In this embodiment, the primer 13 can be released along a single side of the chip 12 or two adjacent sides; similarly, the negative pressure suction can also be provided at the opposite single side, or the other two adjacent sides Provided to accelerate the flow rate of the primer 13 to shorten the filling time of the primer.

此外，當底膠13a自提供負壓吸力的側邊處流出，可同時將該溢流的底膠13a回收，使底膠不外溢過大區域。 In addition, when the primer 13a flows out from the side where the negative pressure suction is provided, the overflowed primer 13a can be recovered at the same time, so that the primer does not overflow over a large area.

綜上所述，本發明當該底膠釋放頭及該負壓吸力頭分別置於該晶片兩相對側邊，該底膠釋放頭受控制沿著其所在之晶片側邊的點膠路徑，均勻地釋放底膠，底膠會自該晶片側邊流入晶片與其接合的基板之間空間，並藉由毛細現象往該晶片的相對側邊流動；此時，該底膠釋放頭設置在該晶片的相對側邊，對該晶片的相對側邊提供一負壓吸力，加速底膠流動的速度，當底膠溢流出該負壓吸力頭所在該晶片的相對側邊，即被該負壓吸力頭吸取並回收至該 底膠回收單元；如此，該底膠外溢至晶片四側邊之面積可被控制並減縮，有助於該半導體封裝結構的橫向尺寸縮減。 In summary, in the present invention, when the primer release head and the negative pressure suction head are respectively placed on two opposite sides of the chip, the primer release head is controlled to dispense evenly along the side of the chip where it is located. Ground releases the primer, the primer will flow into the space between the chip and its bonded substrate from the side of the chip, and flow to the opposite side of the chip by capillary phenomenon; at this time, the primer release head is set on the chip The opposite side provides a negative pressure suction to the opposite side of the wafer to accelerate the flow rate of the primer. When the primer overflows out of the opposite side of the wafer where the negative pressure suction head is located, it is sucked by the negative pressure suction head And recycled to this The bottom glue recovery unit; in this way, the area of the bottom glue overflowing to the four sides of the chip can be controlled and reduced, which helps to reduce the lateral size of the semiconductor packaging structure.

以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。 The above are only the embodiments of the present invention and do not limit the present invention in any form. Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field, Without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make slight changes or modification into equivalent embodiments with equivalent changes, but any content that does not depart from the technical solution of the present invention is based on the technical essence of the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solutions of the present invention.

10:載板 10: Carrier board

11:基板 11: substrate

12:晶片 12: chip

13、13a:底膠 13, 13a: primer

20:底膠填充設備 20: Primer filling equipment

21:底膠釋放頭 21: Base glue release head

22:底膠供應單元 22: Primer supply unit

23:負壓吸力頭 23: Negative pressure suction head

24:底膠回收單元 24: primer recovery unit

Claims (8)

一種半導體封裝結構之底膠填充方法，其中該半導體封裝結構係包含一晶片及一基板，該晶片對接於該基板上，且該晶片與該基板之間形成有空間；該底膠填充方法包括：(a)將底膠釋放於該基板上並靠近該晶片的一側邊位置；(b)於該晶片的相對另一側邊位置提供一負壓吸力；以及(c)當底膠自上述提供負壓吸力所在的側邊處流出時，回收溢流出的底膠。 A method for filling a primer of a semiconductor package structure, wherein the semiconductor package structure comprises a chip and a substrate, the chip is butted on the substrate, and a space is formed between the chip and the substrate; the method for filling the primer includes: (a) Release the primer on the substrate close to one side of the chip; (b) Provide a negative pressure suction on the opposite side of the chip; and (c) When the primer is provided from above When the negative pressure suction flows out from the side, the overflowed primer is recovered. 如請求項1所述之底膠填充方法，其中於該步驟(a)中，該底膠係沿著其所靠近之晶片側邊移動並釋放於該基板上。 The primer filling method according to claim 1, wherein in the step (a), the primer is moved along the side of the chip close to it and released on the substrate. 如請求項1所述之底膠填充方法，其中：於該步驟(a)中，該底膠係沿著其所靠近之晶片側邊及該側邊的一相鄰側邊移動並釋放於該基板上；以及於該步驟(b)中，於該晶片的另二相鄰側邊提供負壓吸力。 The primer filling method according to claim 1, wherein: in the step (a), the primer is moved along the chip side that it is close to and an adjacent side of the side and released on the On the substrate; and in the step (b), a negative pressure suction is provided on the other two adjacent sides of the wafer. 一種底膠填充設備，包括：一底膠釋放頭；一底膠供應單元，係與該底膠釋放頭連通，經由設定由該底膠供應單元輸出足量的底膠給該底膠釋放頭，由該底膠釋放頭流出底膠；以及一負壓吸力頭，係與該底膠釋放頭設置在相對位置，以提供一負壓吸力；以及一底膠回收單元，係與該負壓吸力頭連通，透過該負壓吸力頭吸取底膠。 A primer filling equipment includes: a primer releasing head; a primer supply unit connected to the primer releasing head, and the primer supply unit is set to output a sufficient amount of primer to the primer releasing head, The bottom rubber is discharged from the bottom rubber release head; and a negative pressure suction head is arranged at an opposite position to the bottom rubber release head to provide a negative pressure suction; and a bottom rubber recovery unit is connected to the negative pressure suction head Connect, suck the bottom glue through the negative pressure suction head. 如請求項4所述之底膠填充設備，該底膠回收單元係與該底膠供應單元連通，將回收之底膠提供予該底膠供應單元。 According to the primer filling equipment of claim 4, the primer recovery unit is connected to the primer supply unit, and the recovered primer is provided to the primer supply unit. 如請求項4或5所述之底膠填充設備，該負壓吸力頭係為一長管，該長管的一側邊形成有多個小穿孔。 According to the primer filling equipment of claim 4 or 5, the negative pressure suction head is a long tube, and one side of the long tube is formed with a plurality of small perforations. 如請求項6所述之底膠填充設備，該長管為L形。 According to the primer filling equipment of claim 6, the long tube is L-shaped. 如請求項6所述之底膠填充設備，該長管剖面呈三角形。 According to the primer filling equipment of claim 6, the section of the long tube is triangular.
TW108122152A 2019-06-25 2019-06-25 Underfill filling method of semicondctor package and filling equipment TWI703648B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW108122152A TWI703648B (en) 2019-06-25 2019-06-25 Underfill filling method of semicondctor package and filling equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108122152A TWI703648B (en) 2019-06-25 2019-06-25 Underfill filling method of semicondctor package and filling equipment

Publications (2)

Publication Number Publication Date
TWI703648B true TWI703648B (en) 2020-09-01
TW202101610A TW202101610A (en) 2021-01-01

Family

ID=73643929

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108122152A TWI703648B (en) 2019-06-25 2019-06-25 Underfill filling method of semicondctor package and filling equipment

Country Status (1)

Country Link
TW (1) TWI703648B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113727514A (en) * 2021-08-26 2021-11-30 维沃移动通信有限公司 Circuit board assembly and electronic device
CN114308527A (en) * 2021-11-09 2022-04-12 天芯互联科技有限公司 Glue filling device and glue filling method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW421291U (en) * 1999-09-04 2001-02-01 Jian Huei Jiuan Device for guiding the distribution of filler at the bottom of a flip-chip by extracting air
TW200627651A (en) * 2005-01-25 2006-08-01 Taiwan Semiconductor Mfg Co Ltd IC chip package structure and underfill process
TW201120969A (en) * 2009-12-15 2011-06-16 Powertech Technology Inc Method of filling underfill into package structure
TW201131666A (en) * 2010-03-03 2011-09-16 Powertech Technology Inc Method for forming an underfilling material

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW421291U (en) * 1999-09-04 2001-02-01 Jian Huei Jiuan Device for guiding the distribution of filler at the bottom of a flip-chip by extracting air
TW200627651A (en) * 2005-01-25 2006-08-01 Taiwan Semiconductor Mfg Co Ltd IC chip package structure and underfill process
TW201120969A (en) * 2009-12-15 2011-06-16 Powertech Technology Inc Method of filling underfill into package structure
TW201131666A (en) * 2010-03-03 2011-09-16 Powertech Technology Inc Method for forming an underfilling material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113727514A (en) * 2021-08-26 2021-11-30 维沃移动通信有限公司 Circuit board assembly and electronic device
CN114308527A (en) * 2021-11-09 2022-04-12 天芯互联科技有限公司 Glue filling device and glue filling method thereof

Also Published As

Publication number Publication date
TW202101610A (en) 2021-01-01

Similar Documents

Publication Publication Date Title
US7791209B2 (en) Method of underfill air vent for flipchip BGA
TWI703648B (en) Underfill filling method of semicondctor package and filling equipment
US9780076B2 (en) Package-on-package structure with through molding via
US11894353B2 (en) Driving substrate and manufacturing method thereof, and micro LED bonding method
US8159067B2 (en) Underfill flow guide structures
US6498054B1 (en) Method of underfilling a flip-chip semiconductor device
US9245865B1 (en) Integrated circuit package with multi-trench structure on flipped substrate contacting underfill
CN104916556A (en) Chip arranging method
TWI236747B (en) Manufacturing process and structure for a flip-chip package
WO2021120075A1 (en) Tft structure, light-emitting member, display device, and preparation method therefor
US20170322376A1 (en) Methods of attaching surfaces together by adhesives, and devices including surfaces attached together by adhesives
US20070224729A1 (en) Method for manufacturing a flip-chip package, substrate for manufacturing and flip-chip assembly
JP2004127974A (en) Cof tape carrier, semiconductor element, semiconductor device
TWI469310B (en) Flip-chip stacked package structure and its package methodfabrication method of a photonic crystal structure
KR20100021891A (en) Semiconductor chip package and manufacturing method thereof
CN107768395B (en) Chip mounting process method and suction nozzle of oversized optical image sensor chip
JP2016048752A (en) Wiring board and electronic module manufacturing method
JP5720245B2 (en) Multilayer wafer, resin sealing method, and semiconductor device manufacturing method
JP5400116B2 (en) Flip chip carrier and semiconductor mounting method using the same
TWI713167B (en) Flip-chip semiconductor package and packaging method thereof
WO2018150809A1 (en) Semiconductor device, chip-like semiconductor element, electronic device equipped with semiconductor device, and semiconductor device manufacturing method
JP3019630B2 (en) Adhesive coating device
CN218730887U (en) Semiconductor packaging structure
TW201421619A (en) Flip-chip bonding structure for preventing contamination of underfill climbing
JP5104149B2 (en) Semiconductor device and manufacturing method thereof