CN218730887U

CN218730887U - Semiconductor packaging structure

Info

Publication number: CN218730887U
Application number: CN202222499290.1U
Authority: CN
Inventors: 崔凤佑; 李仲培
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2023-03-24
Anticipated expiration: 2032-09-21

Abstract

The utility model relates to a semiconductor packaging structure. According to an embodiment of the present invention, a semiconductor package structure includes a substrate, a bare chip, a solder resist, and a spacer. The substrate has a first surface. A die is disposed on the first surface. A solder resist is disposed on the first surface and adjacent to the die. The spacer overhangs the solder resist. The semiconductor packaging structure can solve the problems of seepage of underfill and creeping of the underfill.

Description

Semiconductor packaging structure

Technical Field

The present disclosure generally relates to a semiconductor package structure.

Background

In the current process of manufacturing semiconductor packages, the bleeding control of the Underfill exclusion area (Underfill key Out Zone) at the dispensing position is one of the important challenges. In a process of manufacturing a semiconductor package, when an underfill ooze problem occurs during a dispensing process, a silicon spacer near a flip chip controller die may be cracked or damaged, and the silicon spacer may be easily peeled off due to low adhesion between the underfill and a die attach film. Thus, underfill bleed carries the risk of silicon spacer peeling and/or spacer cracking.

Furthermore, as the thickness of the controller die gets thinner, the potential risk of underfill fillet bleed and underfill climbing (on the top surface of the die) also increases. Although a separate solder mask trench can be designed to solve the above problem, it is still difficult to control underfill fillet and underfill climbing problems due to process limitations.

In view of the above, there is a need in the art for a novel semiconductor package design that avoids such serious problems in the process of manufacturing semiconductor package structures employing thin dies.

SUMMERY OF THE UTILITY MODEL

In view of this, the present disclosure provides a semiconductor package structure including a spacer overhanging a solder resist, whereby an underfill bleeding problem and an underfill climbing problem from an underfill exclusion area can be solved.

According to the utility model discloses an embodiment, a semiconductor package structure includes: a substrate having a first surface; a die disposed on the first surface; a solder resist disposed on the first surface and adjacent to the die; and a spacer overhanging the solder resist.

According to a further embodiment of the present invention, the semiconductor package structure further comprises an underfill disposed on the first surface to attach the die to the substrate.

According to another embodiment of the invention, the underfill is further disposed in an area between the die and the spacer.

According to another embodiment of the present invention, the solder resist has a groove, and the spacer is suspended on the solder resist to cover a part of the groove.

According to another embodiment of the invention, the overhang distance of the spacer is equal to or less than 30% of the width of the groove.

According to another embodiment of the invention, said width of said groove is equal to or larger than 120 μm.

According to another embodiment of the present invention, the groove is filled with the underfill.

According to another embodiment of the present invention, no underfill is located on the top surface of the die.

According to another embodiment of the present invention, a creeping distance of the underfill on the top surface of the die is less than 200 μm.

According to another embodiment of the present invention, the spacer is located near the dispensing side of the underfill.

According to another embodiment of the present invention, the overhang distance of the spacer is equal to or less than 30% of the distance between the solder resist and the die.

Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the invention.

Drawings

Fig. 1 is a diagram illustrating a spacer of a semiconductor package structure in the prior art being broken.

Fig. 2A is a schematic cross-sectional view of a semiconductor package structure in the prior art.

Fig. 2B is a schematic cross-sectional view of another semiconductor package structure in the prior art.

Fig. 3A is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view of a semiconductor package structure according to another embodiment of the present invention.

Fig. 4A and 4B respectively illustrate a process flow of manufacturing a semiconductor package structure in the prior art and a process flow of manufacturing a semiconductor package structure according to an embodiment of the present invention.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. The shapes of the respective members illustrated in the drawings are merely exemplary shapes, and do not limit the actual shapes of the members. Additionally, the implementations illustrated in the figures may be simplified for clarity. Thus, the figures may not illustrate all of the components of a given device or apparatus. Finally, the same reference numerals may be used throughout the description and drawings to refer to the same features.

Detailed Description

For a better understanding of the spirit of the invention, some preferred embodiments of the invention will be described in detail below.

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In this specification, unless specified or limited otherwise, relative terms such as: the words "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing. These relative terms are for convenience of description only and do not require that the invention be constructed or operated in a particular orientation.

Various embodiments of the present invention are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the invention. The present invention may be implemented without including all the components or steps described in the embodiments described in the specification, and the execution sequence of the steps may be adjusted according to the actual application.

Fig. 1 is a diagram illustrating a spacer of a semiconductor package structure in the prior art being broken. As shown in fig. 1, the semiconductor package structure 10 includes a substrate 100, a die 110, and a spacer 120. The substrate 100 has a first surface 100a. The die 110 is disposed on the first surface 100a and is adhered to the substrate 100 by an underfill 130. The spacer 120 is disposed on the first surface 100a and adjacent to the die 110. Before the spacer 120 is not disposed, a portion of the spacer 120 contacting the underfill 130 is broken (as indicated by a dotted circle) after the spacer 120 is disposed due to a portion of the underfill 130 oozing out to the vicinity of a predetermined position of the spacer 120.

Fig. 2A is a schematic cross-sectional view of a semiconductor package structure in the prior art. As shown in fig. 2A, the semiconductor package structure 20 includes a substrate 200, a die 210, and solder resists 241 and 242. The substrate 200 has a first surface 200a, and a plurality of pads 250 are disposed on the first surface 200a. The die 210 is flip-chip disposed on the first surface 200a. A plurality of connections 260 are provided on a surface 210a of the die 210 facing the first surface 200a. The connectors 260 are connected to the pads 250 to electrically connect the die 210 and the substrate 200. The die 210 is adhered to the first surface 200a by an underfill 230. The underfill 230 includes a resin and a filler. The resin may include an epoxy resin. The filler may include a small particle size filler p1 and a large particle size filler p2. Solder resists 241 and 242 are disposed on the first surface 200a and adjacent to the die 210. Solder resist 241 is provided on the dispensing (dispense) side, and solder resist 242 is provided on the non-dispensing (exit) side. To allow the underfill 230 to flow more under the die 210 in the dispensing process, the edge of the solder resist 241 is at a distance from the edge of the die 210. The edges of the solder resist 242 may be aligned with the edges of the die 210. The semiconductor package structure 20 further includes a spacer (not shown in the drawings), which is disposed on the solder resists 241 and 242. The spacer is spaced from the die 210 and the area between the spacer and the die 210 serves as an underfill exclusion zone. The underfill excluding region on the dispensing side has a first distance (or length) D1 in the horizontal direction D1, and the underfill excluding region on the non-dispensing side has a second distance (or length) D2 in the horizontal direction D1. Since the dispensing side may exude relatively much underfill, the underfill dispensing area is usually larger than the underfill dispensing area of the non-dispensing side. For example, the first distance d1 is less than or equal to 900 μm and the second distance d2 is less than or equal to 500 μm. Although it is desirable that the maximum distance that the underfill 230 on the dispensing side seeps in the horizontal direction D1 is less than or equal to the first distance D1, in practice, the underfill 230 often seeps out of the first distance D1 (as indicated by the dashed circle), for example, the first distance D1 is 900 μm, and the seepage distance of the underfill 230 on the dispensing side is 800 μm to 1000 μm. In the process of preparing the semiconductor package structure 20, the spacer is formed after the process of priming the underfill 230, and thus the underfill 230 oozing out of the underfill exclusion area may cause the spacer disposed on the solder resist 241 to be cracked or peeled off. In addition, due to structural design and machine capability limitations, the underfill 230 also climbs to the top surface 210b of the die 210 and climbs the third distance d3 on the top surface 210b of the die 210. Although it is desirable that the third distance d3 is less than or equal to the design creep distance, in practice, the third distance d3 may be greater than the design creep distance, thereby affecting the reliability of the semiconductor package structure 20. For example, the design creep distance is 200 μm, and the third distance d3 is greater than 200 μm.

Fig. 2B is a schematic cross-sectional view of another semiconductor package structure in the prior art. The semiconductor package 20 'in fig. 2B is substantially similar to the semiconductor package 20 in fig. 2A, and differs therefrom in that the solder resist 241' on the dispensing side has a groove T1. Since the solder resist 241' has the groove T1, the underfill dispensing area on the dispensing side can accommodate more underfill 230, thereby reducing the bleeding distance of the underfill 230. In the semiconductor package 20', the underfill 230 has a bleeding distance of 700 μm to 900 μm. Although the semiconductor package 20' has a smaller underfill bleed distance than the semiconductor package 20, the underfill bleed distance cannot be further reduced or controlled due to process limitations. Also, to prevent the underfill from peeling off, the groove T1 generally has a certain width, and thus the underfill oozing distance cannot be further reduced by continuously increasing the width of the groove T1. In addition, in the semiconductor package structure 20', the underfill 230 climbs to the top surface 210b of the die 210 and climbs a third distance d3' on the top surface 210b of the die 210. Although the third distance d3 'in fig. 2B is smaller than the third distance d3 in fig. 2A, there is still a risk that the creeping distance of the underfill 230 is too large to affect the reliability of the semiconductor package structure 20'.

To address the above-described problems with prior art semiconductor packages 20 and 20', the present disclosure provides a semiconductor package that improves or eliminates underfill oozing out of the underfill fillet area and underfill climbing.

Fig. 3A is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. As shown in fig. 3A, the semiconductor package structure 30 includes a substrate 300, a die 310, solder resists 341 and 342, and a spacer 320. The substrate 300 has a first surface 300a. The die 310 is disposed on the first surface 300a. Solder resists 341 and 342 are disposed on the first surface 300a and adjacent to the die 310. The spacer 320 overhangs the solder resist 341. The semiconductor package structure 30 may further include an underfill 330.

Substrate 300 may be any suitable substrate or base plate. In some embodiments, substrate 300 is a silicon substrate. A plurality of pads 350 are disposed on the first surface 300a.

The die 310 may be disposed on the first surface 300a in a flip-chip manner. In some embodiments, die 310 is a controller die. A plurality of connectors 360 are disposed on a surface 310a of the die 310 facing the first surface 300a. The connector 360 is connected to the pad 350 to electrically connect the die 310 and the substrate 300.

The solder resist 341 may be provided on the dispensing side. To allow the underfill 330 to flow more under the die 330 in the dispensing process, the edge of the solder resist 341 is at a distance from the edge of the die 310. Solder resist 341 has groove T2, and groove T2 divides solder resist 341 into first solder resist portion 3411 and second solder resist portion 3412. The groove T2 has a certain width w1. In some embodiments, the width w1 of the groove T2 is equal to or greater than about 120 μm. The solder resist 342 may be disposed on the non-dispensing side. The edges of the solder resist 342 may be aligned with the edges of the die 310. The solder resist 341 and the solder resist 342 may have the same thickness. In some embodiments, the thickness of the solder resists 341 and 342 may be about 15 μm.

The spacer 320 is attached to the solder resist 341 by a die attach film (not shown in the figure) and overhangs the solder resist 341. The overhang of the spacer 320 over the solder resist 341 may minimize backflow of the underfill 330 from the spacer 320, thereby solving the problem of climbing of the underfill 330. In some embodiments, the spacer 320 overhangs the solder resist 341 to cover a portion of the groove T2, so the overhang distance w2 of the spacer 320 is equal to the width of the portion of the groove T2 covered by the spacer 320. Overhang distance w2 is less than width w1 of groove T2. In some embodiments, the overhang distance w2 of the spacer 320 is equal to or less than 30% of the width w1 of the groove T2 to prevent underfill 330 voiding problems in the overhang region. The top surface of the spacer 320 may be flush with the top surface of the die 310. In some embodiments, the spacers 320 may be silicon spacers. Although fig. 3A exemplarily shows that the solder resist 341 on the dispensing side is provided with the spacer 320, another spacer may be provided on the solder resist 342 on the non-dispensing side. In some embodiments, the solder resist 342 comprises a recess, and another spacer overhangs the solder resist 342 to cover a portion of the recess.

An underfill 330 is disposed on the first surface 300a to attach the die 310 to the substrate 300. An underfill 330 may further be disposed in the area between the die 310 and the spacer 320. The groove T2 may be filled with an underfill 330. The underfill 330 includes a resin and a filler. In some embodiments, the resin may comprise an epoxy resin. The fillers may include fillers of different particle size sizes to improve the flow of the underfill 330. In some embodiments, the filler may include a small particle size filler p3 and a large particle size filler p4.

The combined use of the overhanging spacer and the solder resist trench in the semiconductor package structure 30 may minimize capillary forces from the underfill 330 dispensing onto the die 310. Thus, no underfill 330 climbs onto the top surface 310b of the die 310 (as shown by the dashed circle), or less underfill 330 climbs onto the top surface 310b of the die 310. When a small amount of underfill 330 climbs to the top surface 310b of the die 310, the creeping distance d6 of the underfill 330 on the top surface 310b of the die 310 is less than 200 μm.

In the semiconductor package 30, the spacers 320 may be formed before priming the underfill 330 (described in detail below), and the underfill 330 is blocked by the overhanging spacers 320, so that the underfill 330 may be prevented from oozing out on the dispensing side, so that the underfill exclusion area on the dispensing side of the semiconductor package 30 may have a reduced distance. As shown in fig. 3A, the underfill exclusion area on the dispensing side has a fourth distance (or length) D4 in the horizontal direction D1', and the underfill exclusion area on the non-dispensing side has a fifth distance (or length) D5 in the horizontal direction D1'. The fourth distance d4 may be equal to the fifth distance d5. In some embodiments, the fourth distance d4 is less than or equal to 500 μm and the fifth distance d5 is less than or equal to 500 μm. As can be seen in fig. 3A, no underfill 330 seeps out of the underfill ejection area on the dispensing side (as indicated by the dashed circle).

Fig. 3B is a schematic cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. The semiconductor package structure 30 'in fig. 3B is different from the semiconductor package structure 30 in fig. 3A in that the solder resist 341' has no recess. Other components (e.g., die 310, etc.) of the semiconductor package structure 30' in fig. 3B are the same as those of the semiconductor package structure 30 in fig. 3A, and are not repeated herein.

As shown in fig. 3B, the spacer 320 has a distance w3 from the die 310, the spacer 320 overhangs the solder resist 341' (as shown by the dashed box), and the overhang distance w2' of the spacer is less than the distance w3 between the solder resist 341' and the die 310. In some embodiments, the overhang distance w2 'of the spacer is equal to or less than 30% of the distance w3 between the solder resist 341' and the die 310. In the semiconductor package structure 30', the suspension of the spacer 320 over the solder resist 341' may minimize the backflow of the underfill 330 from the spacer 320, thereby solving the problem of the underfill 330 climbing (as indicated by the dashed circle). In addition, the spacers 320 may be formed before priming the underfill 330, and the underfill 330 may be blocked by the overhanging spacers 320, so that the underfill 330 may be prevented from oozing out on the dispensing side (as indicated by the dotted circles), so that the underfill exclusion area on the dispensing side of the semiconductor package structure 30' may have a reduced distance. As shown in fig. 3B, the underfill exclusion area on the dispensing side has a fourth distance D4 'in the horizontal direction D1', and the underfill exclusion area on the non-dispensing side has a fifth distance D5 'in the horizontal direction D1'. The fourth distance d4 'may be equal to the fifth distance d5'. In some embodiments, the fourth distance d4 'is less than or equal to 500 μm and the fifth distance d5' is less than or equal to 500 μm.

Fig. 4A and 4B illustrate a process flow of manufacturing a semiconductor package structure in the prior art and a process flow of manufacturing a semiconductor package structure according to an embodiment of the present invention, respectively.

The process flow 1 in fig. 4A is a process flow for manufacturing a semiconductor package structure in the prior art, and the semiconductor package structures 20 and 20' in fig. 2A and 2B can be manufactured through the process flow 1. The process flow 2 in fig. 4B is a process flow for manufacturing a semiconductor package structure according to an embodiment of the present invention, and the semiconductor package structures 30 and 30' in fig. 3A and 3B can be manufactured through the process flow 2.

As shown in fig. 4A, a process flow 1 for forming a prior art semiconductor package structure may include: load (load), surface Mount Technology (SMT), flip chip, reflow (reflow), solder resist removal (deflux), printed Circuit (PCB) pre-bake, underfill (UF) plasma, under-coating (underfil), UF curing, PCB pre-bake, die attach (forming spacers), die attach (forming memory die, e.g., forming NAND), and die attach cure. In process flow 1, a controller die may be disposed on a substrate by a flip chip technique, then an underfill is formed to bond the controller die, and finally a spacer and a memory die are sequentially formed by a die bonding technique. Since the spacers are formed after the priming underfill process, underfill that seeps out of the underfill exclusion area during the priming process can affect the placement of the spacers, e.g., causing the spacers to crack or peel.

The process flow 2 for manufacturing the semiconductor package structure according to an embodiment of the present invention includes the same process steps as the process flow 1, but the sequence of the process steps is different. As shown in fig. 4B, in process flow 2, the spacer is formed on the substrate by die attach technology, then the controller die is disposed on the substrate by flip chip technology, and an underfill is formed to attach the controller die, and finally the memory die is formed by die attach technology. Since the spacers are formed prior to the undercoating underfill process, the spacers may act as a barrier to bleed out of the underfill during the undercoating process, thereby avoiding bleed out of the underfill and reducing the distance of the underfill exclusion area. Furthermore, the spacers may be arranged to overhang the solder resist as shown in fig. 3A and 3B during the die attach process to address the climbing of the underfill.

The utility model discloses a semiconductor packaging structure can solve or reduce the underfill and spill over and scramble the problem at least, consequently can reduce the output loss, realizes that the cost is practiced thrift. The suspension spacer in the semiconductor package structure of the present invention can reduce the size of the underfill exclusion area (for example, as shown in fig. 3A, the underfill exclusion area has a width of 500 μm in the horizontal direction), provide a large process margin and design flexibility for the layout of the semiconductor package structure, and improve the effective utilization rate of the substrate. In addition, the overhanging spacer in the semiconductor package structure of the present invention can solve the underfill climbing problem, providing a stable design choice for the application of thin dies (e.g., with a thickness less than or equal to 50 μm). Therefore, the utility model discloses a semiconductor package structure can be applied to compact semiconductor package. Furthermore, the semiconductor package structure of the present invention can be fabricated by adjusting the order of the existing process steps without adding new processes/materials.

The description in this specification is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present invention is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor package, comprising:

a substrate having a first surface;

a die disposed on the first surface;

a solder resist disposed on the first surface and adjacent to the die; and

a spacer overhanging the solder resist.

2. The semiconductor package structure of claim 1, further comprising an underfill disposed on the first surface to attach the die to the substrate.

3. The semiconductor package structure of claim 2, wherein the underfill is further disposed in a region between the die and the spacer.

4. The semiconductor package structure according to claim 3, wherein the solder resist has a groove, and the spacer overhangs the solder resist to cover a portion of the groove.

5. The semiconductor package structure of claim 4, wherein the overhang distance of the spacer is equal to or less than 30% of the width of the groove.

6. The semiconductor package structure according to claim 5, wherein the width of the groove is equal to or greater than 120 μm.

7. The semiconductor package according to claim 4, wherein the recess is filled with the underfill.

8. The semiconductor package structure of claim 4, wherein no underfill is on a top surface of the die.

9. The semiconductor package structure of claim 4, wherein a creeping distance of the underfill on a top surface of the die is less than 200 μm.

10. The semiconductor package according to claim 2, wherein the spacer is located near a dispensing side of the underfill.

11. The semiconductor package structure of claim 1, wherein a overhang distance of the spacer is equal to or less than 30% of a distance between the solder resist and the die.