TWI701847B - Light-emitting element having a reflective structure with high efficiency - Google Patents

Light-emitting element having a reflective structure with high efficiency Download PDF

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TWI701847B
TWI701847B TW105102586A TW105102586A TWI701847B TW I701847 B TWI701847 B TW I701847B TW 105102586 A TW105102586 A TW 105102586A TW 105102586 A TW105102586 A TW 105102586A TW I701847 B TWI701847 B TW I701847B
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layer
light
transparent
emitting
reflective
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TW105102586A
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TW201705538A (en
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謝明勳
廖文祿
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晶元光電股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46Reflective coating, e.g. dielectric Bragg reflector

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Led Devices (AREA)

Abstract

A light-emitting element comprises a substrate; a light-emitting stack on the substrate; a transparent layer between the light-emitting stack and the substrate; and a plurality of cavities between the substrate and the light-emitting stack; wherein from a cross section view of the light-emitting element, the transparent layer comprises a first width, and the light-emitting stack comprises a second width smaller than the first width.

Description

具有高效率反射結構之發光元件 Light-emitting element with high-efficiency reflective structure

本發明關於一種發光元件,特別是關於一種具有高效率反射結構之發光元件。 The present invention relates to a light-emitting element, in particular to a light-emitting element with a highly efficient reflective structure.

光電元件,例如發光二極體(Light-emitting Diode;LED),目前已經廣泛地使用在光學顯示裝置、交通號誌、資料儲存裝置、通訊裝置、照明裝置與醫療器材上。此外,上述之LED可與其他元件組合連接以形成一發光裝置。第1圖為習知之發光裝置結構示意圖,如第1圖所示,一發光裝置1包含一具有一電路14之次載體(submount)12;一焊料16(solder)位於上述次載體12上,藉由此焊料16將LED 11固定於次載體12上並使LED 11與次載體12上之電路14形成電連接;以及一電性連接結構18,以電性連接LED 11之電極15與次載體12上之電路14;其中,上述之次載體12可以是導線架(lead frame)或大尺寸鑲嵌基底(mounting substrate)。 Optoelectronic components, such as light-emitting diodes (LEDs), are currently widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices, and medical equipment. In addition, the above-mentioned LED can be combined with other components to form a light emitting device. Figure 1 is a schematic diagram of the structure of a conventional light emitting device. As shown in Figure 1, a light emitting device 1 includes a submount 12 with a circuit 14; a solder 16 (solder) is located on the submount 12, and As a result, the solder 16 fixes the LED 11 on the secondary carrier 12 and electrically connects the LED 11 with the circuit 14 on the secondary carrier 12; and an electrical connection structure 18 to electrically connect the electrode 15 of the LED 11 and the secondary carrier 12 The above circuit 14; wherein, the above-mentioned secondary carrier 12 can be a lead frame or a large-size mounting substrate (mounting substrate).

本申請提供一種發光元件,其包括:一基板;一發光疊層位於該基板上;一透明層位於該基板及該發光疊層之間;以及複數孔洞位於該基板及該 發光疊層之間;其中由該發光元件的剖面觀之,該透明層具有一第一寬度,且該發光疊層具有一第二寬度小於該第一寬度。 The present application provides a light-emitting element, which includes: a substrate; a light-emitting stack on the substrate; a transparent layer between the substrate and the light-emitting stack; and a plurality of holes located on the substrate and the substrate Between the light-emitting stacks; where viewed from the cross-section of the light-emitting element, the transparent layer has a first width, and the light-emitting stack has a second width smaller than the first width.

本申請之發光元件中,該發光疊層將該透明層裸露出來。 In the light-emitting element of the present application, the light-emitting stack exposes the transparent layer.

1:發光裝置 1: Light-emitting device

11:LED 11: LED

12:次載體 12: Secondary carrier

13、20、50:基板 13, 20, 50: substrate

14:電路 14: Circuit

15、56:電極 15, 56: Electrode

16:焊料 16: Solder

18:電性連接結構 18: Electrical connection structure

2、3、40、5:發光元件 2, 3, 40, 5: light-emitting element

21:第一電極 21: First electrode

22:黏結層 22: Adhesive layer

23:第二電極 23: second electrode

24、54:反射結構 24, 54: reflective structure

241、543:凸部 241, 543: convex

242、544:反射層 242, 544: reflective layer

243、545:凹部 243, 545: recess

244、542:第一透光層 244, 542: the first transparent layer

245、30、547:孔洞 245, 30, 547: holes

246:第二透光層 246: second light transmission layer

247:第一下表面 247: The first lower surface

248、540:窗戶層 248, 540: Window layer

26:發光疊層 26: luminous stack

261、541:粗化上表面 261, 541: Roughen the upper surface

262、522:第一半導體層 262, 522: first semiconductor layer

263:粗化下表面 263: Roughen the bottom surface

264、524:主動層 264, 524: Active layer

265:平坦部 265: flat part

266、526:第二半導體層 266, 526: second semiconductor layer

32:導電部 32: conductive part

41:燈罩 41: Lampshade

42:透鏡 42: lens

43:載體 43: carrier

44:照明模組 44: lighting module

45:燈座 45: lamp holder

46:散熱槽 46: heat sink

47:連結部 47: Connection

48:電連結器 48: electric connector

51:第一接觸層 51: first contact layer

53:第二接觸層 53: second contact layer

546:第一絕緣層 546: first insulating layer

548:第三透光層 548: third transparent layer

549:通道 549: Channel

562:第一導電層 562: first conductive layer

564:第二導電層 564: second conductive layer

h:高度 h: height

t:厚度 t: thickness

701:成長基板 701: growth substrate

90E2:第二電極墊 90E2: second electrode pad

76:發光疊層 76: luminous stack

762:第一半導體層 762: first semiconductor layer

764:活性層 764: active layer

766:第二半導體層 766: second semiconductor layer

744:第一透明層 744: first transparent layer

746:第二透明層 746: second transparent layer

745:孔穴 745: hole

745b:晶界 745b: Grain boundary

745w:第一部分 745w: Part One

745n:第二部分 745n: part two

744c:凸出部 744c: protrusion

744cB1:底基體 744cB1: Substrate

744cB2:頂基體 744cB2: Top substrate

745a:底表面 745a: bottom surface

742:反射層 742: reflective layer

72a:第一黏結層 72a: First bonding layer

70:基板 70: substrate

72b:第二黏結層 72b: second adhesive layer

72:黏著層 72: Adhesive layer

70E1:第一電極墊 70E1: the first electrode pad

70E1’:延伸電極 70E1’: Extension electrode

70E2:第二電極墊 70E2: second electrode pad

70R:粗化表面 70R: roughened surface

77:保護層 77: protective layer

80:基板 80: substrate

86:發光疊層 86: luminous stack

862:第一半導體層 862: first semiconductor layer

864:活性層 864: active layer

866:第二半導體層 866: second semiconductor layer

86E、86E’:裸露區域 86E, 86E’: naked area

D1:第一介電層 D1: The first dielectric layer

844:第一透明層 844: first transparent layer

846:第二透明層 846: second transparent layer

845:孔穴 845: hole

844c:凸出部 844c: protrusion

842:反射層 842: reflective layer

D2:第二介電層 D2: second dielectric layer

D2E、D2E’:裸露區域 D2E, D2E’: naked area

M1:導電層 M1: conductive layer

D3:第三介電層 D3: The third dielectric layer

M2E:區域 M2E: area

80E1:第一電極墊 80E1: the first electrode pad

80E2:第二電極墊 80E2: second electrode pad

90:基板 90: substrate

96:發光疊層 96: luminous stack

962:第一半導體層 962: first semiconductor layer

964:活性層 964: active layer

966:第二半導體層 966: second semiconductor layer

96E、96E’:裸露區域 96E, 96E’: naked area

90CB:電流阻擋層 90CB: current blocking layer

944:第一透明層 944: first transparent layer

946:第二透明層 946: second transparent layer

945:孔穴 945: hole

944c:凸出部 944c: protrusion

MF1、MF1E:中間導電層 MF1, MF1E: Intermediate conductive layer

MF1’、MF1’E:中間導電層 MF1’, MF1’E: Intermediate conductive layer

96E:裸露區域 96E: bare area

942:反射層 942: reflective layer

942:布拉格反射鏡結構 942: Bragg reflector structure

942E:裸露區域 942E: exposed area

M2E:區域 M2E: area

90E1:第一電極墊 90E1: first electrode pad

W1、W2、W3、W4:寬度 W 1 , W 2 , W 3 , W 4 : width

第1圖為習知之發光裝置結構示意圖;第2圖繪示本申請案一實施例之發光元件之剖面示意圖;第3圖繪示本申請案另一實施例之發光元件之剖面示意圖;第4圖繪示第3圖之實施例之第二透光層之材料沉積方向示意圖;第5圖繪示本申請案另一實施例之發光元件之剖面示意圖;第6圖為本申請案一實施例之燈泡分解示意圖;第7A至第7G圖為本申請案另一實施例之發光元件之製造方法;第8A至第8E圖為本申請案另一實施例之發光元件之製造方法,第8E圖繪示發光元件沿著如第8F圖中所示的DD剖面線之剖面示意圖;第8F圖繪示發光元件之上視圖; 第9A圖至9E圖繪示本申請案另一實施例之發光元件及其製造方法,第9E圖繪示發光元件沿著如第9F圖中所示的HIJK剖面線之剖面示意圖;以及第9F圖繪示發光元件之上視圖。 Fig. 1 is a schematic diagram of the structure of a conventional light-emitting device; Fig. 2 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present application; Fig. 3 is a schematic cross-sectional view of a light-emitting element according to another embodiment of the present application; Fig. 3 is a schematic diagram of the material deposition direction of the second light-transmitting layer in the embodiment of Fig. 3; Fig. 5 is a cross-sectional schematic diagram of a light-emitting element of another embodiment of the application; Fig. 6 is an embodiment of the application Fig. 7A to Fig. 7G are a method of manufacturing a light-emitting device according to another embodiment of the application; Figs. 8A to 8E are a method of manufacturing a light-emitting device according to another embodiment of the application, Fig. 8E A schematic cross-sectional view of the light-emitting element along the DD section line as shown in Figure 8F is shown; Figure 8F is a top view of the light-emitting element; Figures 9A to 9E show a light-emitting device and its manufacturing method according to another embodiment of the present application. Figure 9E shows a schematic cross-sectional view of the light-emitting device along the HIJK section line as shown in Figure 9F; and Figure 9F The figure shows the top view of the light-emitting element.

為讓本申請的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。在圖式或說明中,相似或相同之部份係使用相同之標號,並且在圖式中,元件之形狀或厚度可擴大或縮小。需特別注意的是,圖中未繪示或描述之元件,可以是熟習此技藝之人士所知之形式。 In order to make the above-mentioned features and advantages of the present application more obvious and understandable, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows. In the drawings or descriptions, similar or identical parts use the same reference numerals, and in the drawings, the shape or thickness of the components can be enlarged or reduced. It should be noted that the components not shown or described in the figure may be in the form known to those who are familiar with the art.

第2圖為本申請案一實施例之發光元件之剖面圖。如第2圖所示,一發光元件2具有一基板20;一黏結層22,位於基板20之上;一反射結構24,位於黏結層22之上;一發光疊層26,位於反射結構24之上;一第一電極21,位於基板20之下;以及一第二電極23,位於發光疊層26之上。發光疊層26具有一第一半導體層262,位於反射結構24之上;一主動層264,位於第一半導體層262之上;以及一第二半導體層266,位於主動層264之上。 Figure 2 is a cross-sectional view of a light-emitting device according to an embodiment of the application. As shown in Figure 2, a light-emitting element 2 has a substrate 20; an adhesive layer 22 located on the substrate 20; a reflective structure 24 located on the adhesive layer 22; a light-emitting stack 26 located on the reflective structure 24 On; a first electrode 21, located under the substrate 20; and a second electrode 23, located on the light-emitting stack 26. The light-emitting stack 26 has a first semiconductor layer 262 on the reflective structure 24; an active layer 264 on the first semiconductor layer 262; and a second semiconductor layer 266 on the active layer 264.

第一電極21及/或第二電極23用以接受外部電壓,可由透明導電材料或金屬材料所構成。透明導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鋅(IZO)、類鑽碳薄膜(DLC)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO) 或上述材料之化合物。金屬材料包含但不限於鋁(Al)、鉻(Cr)、銅(Cu)、錫(Sn)、金(Au)、鎳(Ni)、鈦(Ti)、鉑(Pt)、鉛(Pb)、鋅(Zn)、鎘(Cd)、銻(Sb)、鈷(Co)或上述材料之合金等。 The first electrode 21 and/or the second electrode 23 are used to receive an external voltage, and may be made of a transparent conductive material or a metal material. Transparent conductive materials include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium zinc oxide (IZO), diamond-like carbon film (DLC), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO) Or a compound of the above materials. Metal materials include but are not limited to aluminum (Al), chromium (Cr), copper (Cu), tin (Sn), gold (Au), nickel (Ni), titanium (Ti), platinum (Pt), lead (Pb) , Zinc (Zn), cadmium (Cd), antimony (Sb), cobalt (Co) or alloys of the above materials.

發光疊層26具有一粗化上表面261與一粗化下表面263,可降低全反射的機率,提高出光效率。粗化上表面具有一平坦部265,第二電極23可位於平坦部265之上,提升第二電極23與發光疊層26之間的黏著性,降低第二電極23因後續製程,例如打線,而自發光疊層26上剝離的機率。發光疊層26之材料可為半導體材料,包含一種以上之元素,此元素可選自鎵(Ga)、鋁(Al)、銦(In)、磷(P)、氮(N)、鋅(Zn)、鎘(Cd)與硒(Se)所構成之群組。第一半導體層262與第二半導體層266的電性相異,用以產生電子或電洞。主動層124可發出一種或多種色光,可為可見光或不可見光,其結構可為單異質結構、雙異質結構、雙側雙異質結構、多層量子井或量子點。 The light-emitting laminate 26 has a roughened upper surface 261 and a roughened lower surface 263, which can reduce the probability of total reflection and improve the light extraction efficiency. The roughened upper surface has a flat portion 265, and the second electrode 23 can be located on the flat portion 265, which improves the adhesion between the second electrode 23 and the light-emitting stack 26, and reduces the subsequent processing of the second electrode 23, such as wire bonding. And the probability of peeling off from the light-emitting laminate 26. The material of the light-emitting stack 26 can be a semiconductor material, containing more than one element, and this element can be selected from gallium (Ga), aluminum (Al), indium (In), phosphorus (P), nitrogen (N), zinc (Zn) ), cadmium (Cd) and selenium (Se). The electrical properties of the first semiconductor layer 262 and the second semiconductor layer 266 are different, and are used to generate electrons or holes. The active layer 124 can emit one or more color lights, which can be visible or invisible light, and its structure can be a single heterostructure, a double heterostructure, a double-sided double heterostructure, a multilayer quantum well, or a quantum dot.

反射結構24自黏結層22往發光疊層26之方向具有一反射層242、一第一透光層244與一窗戶層248。窗戶層248具有一粗化下表面,粗化下表面具有複數個凸部241與凹部243。其中,粗化下表面更具有一平坦部位於第二電極23之正下方,用以與第一透光層244形成歐姆接觸。至少一孔洞245形成於第一透光層244之中,孔洞245可自窗戶層248之粗化下表面向下延伸至反射層242。另一實施例中,孔洞245可自凸部241向下延伸至反射層242。其中,孔洞245之折射率小於窗戶層248與第一透光層244之折射率。由於孔洞245之折射率小於窗戶層248與第一透光 層244之折射率,窗戶層248與孔洞245間之介面其臨界角小於窗戶層248與第一透光層244間之介面的臨界角,所以發光疊層26所發之光射向孔洞245後,在窗戶層248與孔洞245之間的介面形成全反射的機率增加。此外,原本在窗戶層248與第一透光層244介面未形成全反射而進入第一透光層244之光,在第一透光層244與孔洞245之間的介面亦會形成全反射,因而提升發光元件2的出光效率。孔洞245由剖面圖觀之可以為上寬下窄的漏斗狀。反射結構24可更包含一第二透光層246,第二透光層246位於部分第一透光層244與窗戶層248之間,以增加第一透光層244與窗戶層248之間的歐姆接觸。另一實施例中,第二透光層246可具有孔洞245,其中孔洞245之折射率小於窗戶層248與第二透光層246之折射率。由於孔洞245之折射率小於窗戶層248與第二透光層246之折射率,第二透光層246與孔洞245間之介面的臨界角小於窗戶層248與第二透光層246間之介面的臨界角,所以發光疊層26所發之光射向孔洞245後,在第二透光層246與孔洞245之間的介面形成全反射的機率增加。又一實施例中,反射結構24可不具有窗戶層248,第一透光層244形成於發光疊層26之下。此時,發光疊層26之粗化下表面263具有複數個凸部與凹部,利於孔洞245之形成。 The reflective structure 24 has a reflective layer 242, a first transparent layer 244 and a window layer 248 from the bonding layer 22 to the light-emitting stack 26. The window layer 248 has a roughened lower surface, and the roughened lower surface has a plurality of convex portions 241 and concave portions 243. Wherein, the roughened lower surface further has a flat portion located directly under the second electrode 23 for forming an ohmic contact with the first transparent layer 244. At least one hole 245 is formed in the first light-transmitting layer 244, and the hole 245 can extend from the roughened lower surface of the window layer 248 down to the reflective layer 242. In another embodiment, the hole 245 may extend downward from the convex portion 241 to the reflective layer 242. The refractive index of the hole 245 is smaller than the refractive index of the window layer 248 and the first transparent layer 244. Since the refractive index of the hole 245 is smaller than the window layer 248 and the first light transmission The refractive index of the layer 244, the critical angle of the interface between the window layer 248 and the hole 245 is smaller than the critical angle of the interface between the window layer 248 and the first light-transmitting layer 244, so the light emitted by the light-emitting laminate 26 is directed to the hole 245 , The probability of forming total reflection at the interface between the window layer 248 and the hole 245 increases. In addition, the light that enters the first light-transmitting layer 244 without forming total reflection at the interface between the window layer 248 and the first light-transmitting layer 244 will also form total reflection at the interface between the first light-transmitting layer 244 and the hole 245. Therefore, the light extraction efficiency of the light emitting element 2 is improved. The hole 245 can be viewed as a funnel with a wide top and a narrow bottom. The reflective structure 24 may further include a second light-transmitting layer 246. The second light-transmitting layer 246 is located between a portion of the first light-transmitting layer 244 and the window layer 248 to increase the gap between the first light-transmitting layer 244 and the window layer 248. Ohmic contact. In another embodiment, the second light-transmitting layer 246 may have a hole 245, wherein the refractive index of the hole 245 is smaller than the refractive index of the window layer 248 and the second light-transmitting layer 246. Since the refractive index of the hole 245 is smaller than the refractive index of the window layer 248 and the second transparent layer 246, the critical angle of the interface between the second transparent layer 246 and the hole 245 is smaller than the interface between the window layer 248 and the second transparent layer 246 Therefore, after the light emitted by the light-emitting stack 26 is directed to the hole 245, the probability of forming a total reflection at the interface between the second light-transmitting layer 246 and the hole 245 increases. In another embodiment, the reflective structure 24 may not have the window layer 248 and the first light-transmitting layer 244 is formed under the light-emitting stack 26. At this time, the roughened lower surface 263 of the light-emitting stack 26 has a plurality of protrusions and recesses, which facilitate the formation of the holes 245.

窗戶層248對於發光疊層26所發之光為透明,用以提升出光效率,其材料可為導電材料,包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、 氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)或上述材料之組合。粗化下表面之凹部243與凸部241之間的高度差h約為窗戶層厚度t的1/3至2/3,利於孔洞245的形成。 The window layer 248 is transparent to the light emitted by the light-emitting stack 26 to improve the efficiency of light extraction. The material can be a conductive material, including but not limited to indium tin oxide (ITO), indium oxide (InO), and tin oxide (SnO) , Cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), oxide Indium Cerium (ICO), Indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO) or a combination of the above materials. The height difference h between the concave portion 243 and the convex portion 241 of the roughened lower surface is about 1/3 to 2/3 of the thickness t of the window layer, which facilitates the formation of the hole 245.

第一透光層244及/或第二透光層246之材料對於發光疊層26所發之光為透明,以增加窗戶層248與反射層242之間的歐姆接觸以及電流傳導與擴散,並與反射層242形成全方位反射鏡(Omni-Directional Reflector,ODR)。其材料可為透明導電材料,包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)或上述材料之組合。其中第一透光層244之材料較佳為氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、氧化銦鋅(IZO)或上述材料之組合。形成第一透光層244及/或第二透光層246之方法包含物理氣相沉積法,例如電子束蒸鍍或濺鍍。反射層242可反射來自發光疊層26之光,其材料可為金屬材料,包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)或上述材料之合金等。 The material of the first light-transmitting layer 244 and/or the second light-transmitting layer 246 is transparent to the light emitted by the light-emitting laminate 26, so as to increase the ohmic contact between the window layer 248 and the reflective layer 242, as well as current conduction and diffusion, and The reflective layer 242 forms an Omni-Directional Reflector (ODR). The material can be a transparent conductive material, including but not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO) ), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), Indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO) or a combination of the above materials. The material of the first transparent layer 244 is preferably aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium zinc oxide (IZO) or a combination of the above materials . The method of forming the first light-transmitting layer 244 and/or the second light-transmitting layer 246 includes physical vapor deposition, such as electron beam evaporation or sputtering. The reflective layer 242 can reflect the light from the light emitting stack 26, and its material can be a metal material, including but not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W) or alloys of the above materials.

黏結層22可連接基板20與反射結構24,可具有複數個從屬層(未顯示)。黏結層22之材料可為透明導電材料或金屬材料,透明導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、 氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)或上述材料之組合。金屬材料包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)或上述材料之合金等。 The bonding layer 22 can connect the substrate 20 and the reflective structure 24, and can have a plurality of subordinate layers (not shown). The material of the bonding layer 22 can be a transparent conductive material or a metal material. The transparent conductive material includes but not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), Zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium oxide Aluminum zinc (GAZO) or a combination of the above materials. Metal materials include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt) , Tungsten (W) or alloys of the above materials, etc.

基板20可用以支持位於其上之發光疊層26與其它層或結構,其材料可為透明材料或導電材料。透明材料包含但不限於藍寶石(Sapphire)、鑽石(Diamond)、玻璃(Glass)、環氧樹脂(Epoxy)、石英(Quartz)、壓克力(Acryl)、氧化鋁(Al2O3)、氧化鋅(ZnO)或氮化鋁(AlN)等。導電材料包含但不限於銅(Cu)、鋁(Al)、鉬(Mo)、錫(Sn)、鋅(Zn)、鎘(Cd)、鎳(Ni)、鈷(Co)、類鑽碳薄膜(Diamond Like Carbon;DLC)、石墨(Graphite)、碳纖維(Carbon Fiber)、金屬基複合材料(Metal Matrix Composite;MMC)、陶瓷基複合材料(Ceramic Matrix Composite;CMC)、矽(Si)、磷化碘(IP)、硒化鋅(ZnSe)、砷化鎵(GaAs)、碳化矽(SiC)、磷化鎵(GaP)、磷砷化鎵(GaAsP)、硒化鋅(ZnSe)、磷化銦(InP)、鎵酸鋰(LiGaO2)或鋁酸鋰(LiAlO2)。 The substrate 20 can be used to support the light-emitting stack 26 and other layers or structures on it, and its material can be a transparent material or a conductive material. Transparent materials include but are not limited to Sapphire, Diamond, Glass, Epoxy, Quartz, Acrylic, Alumina (Al 2 O 3 ), Oxidation Zinc (ZnO) or aluminum nitride (AlN), etc. Conductive materials include but are not limited to copper (Cu), aluminum (Al), molybdenum (Mo), tin (Sn), zinc (Zn), cadmium (Cd), nickel (Ni), cobalt (Co), diamond-like carbon film (Diamond Like Carbon; DLC), Graphite, Carbon Fiber, Metal Matrix Composite (MMC), Ceramic Matrix Composite (CMC), Silicon (Si), Phosphating Iodine (IP), zinc selenide (ZnSe), gallium arsenide (GaAs), silicon carbide (SiC), gallium phosphide (GaP), gallium arsenide phosphorus (GaAsP), zinc selenide (ZnSe), indium phosphide (InP), lithium gallate (LiGaO 2 ), or lithium aluminate (LiAlO 2 ).

第3圖為本申請案另一實施例之發光元件之剖面圖。一發光元件3具有上述發光元件2類似之結構,但反射結構24之第二透光層246具有複數個孔洞30,以致第二透光層246之折射率小於1.4,較佳為1.35。如第4圖所示,孔洞30的形成是將晶圓4固定,以特定的方向,例如與垂直於晶圓的法線夾角θ的方向D,以物理氣相法沉積第二透光層246之材料於晶圓上。因為沉積方向D的調整使材料無法沉積到部分區域而形成孔洞30。其中,夾角θ約為60度。有孔洞30形成之第二透光層246之折射 率較不具有孔洞之透光層之折射率低,可增加第二透光層246與其他層介面間的產生全反射的機率,提升發光元件3的出光效率。第一透光層244可用物理氣相法或化學氣相法形成於第二透光層246之下,其厚度大於第二透光層246之厚度,可防止反射層242之材料擴散至第二透光層246。第一透光層244不具有孔洞,可避免反射層242之材料擴散至孔洞之中,破壞反射層242的結構,導致反射層242的反射率降低。第一透光層244具有一第一下表面247,第一下表面247可用化學機械研磨法(Chemical Mechanical Polishing,CMP)研磨,使其中心線平均粗糙度(Ra)約為1nm~40nm。當反射層242形成於第一下表面247之下時,反射層242可形成一中心線平均粗糙度較低的表面,因而提高反射層242的反射率。 FIG. 3 is a cross-sectional view of a light-emitting device according to another embodiment of the application. A light-emitting element 3 has a structure similar to the above-mentioned light-emitting element 2, but the second transparent layer 246 of the reflective structure 24 has a plurality of holes 30, so that the refractive index of the second transparent layer 246 is less than 1.4, preferably 1.35. As shown in FIG. 4, the formation of the hole 30 is to fix the wafer 4, and deposit the second light-transmitting layer 246 by the physical vapor method in a specific direction, for example, the direction D perpendicular to the normal line of the wafer. The material is on the wafer. Because of the adjustment of the deposition direction D, the material cannot be deposited in a part of the area, and the hole 30 is formed. Among them, the included angle θ is about 60 degrees. Refraction of the second transparent layer 246 formed with holes 30 The refractive index is lower than that of the light-transmitting layer without holes, which can increase the probability of total reflection between the second light-transmitting layer 246 and the interface of other layers, and improve the light-emitting efficiency of the light-emitting element 3. The first light-transmitting layer 244 can be formed under the second light-transmitting layer 246 by a physical vapor method or a chemical vapor method, and its thickness is greater than that of the second light-transmitting layer 246, which can prevent the material of the reflective layer 242 from spreading to the second Transparent layer 246. The first light-transmitting layer 244 does not have holes, which can prevent the material of the reflective layer 242 from being diffused into the holes, damaging the structure of the reflective layer 242, and reducing the reflectivity of the reflective layer 242. The first light-transmitting layer 244 has a first lower surface 247, and the first lower surface 247 can be polished by a chemical mechanical polishing (CMP) method so that the centerline average roughness (Ra) is about 1 nm-40 nm. When the reflective layer 242 is formed under the first lower surface 247, the reflective layer 242 can form a surface with a relatively low centerline average roughness, thereby increasing the reflectivity of the reflective layer 242.

發光元件3更具有至少一導電部32位於發光疊層26與反射層242之間。另一實施例中,導電部32可位於窗戶層248與反射層242之間。導電部32用以傳導電流,其材料可為透明導電材料或金屬材料,透明導電材料包含但不限於氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、磷化鎵(GaP)、氧化銦鈰(ICO)、氧化銦鎢(IWO)、氧化銦鈦(ITiO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鎵鋁鋅(GAZO)或上述材料之組合。金屬材料包含但不限於銅(Cu)、鋁(Al)、錫(Sn)、金(Au)、銀(Ag)、鉛(Pb)、鈦(Ti)、鎳(Ni)、鉑(Pt)、鎢(W)、鍺(Ge)或上述材料之合金等。 The light-emitting element 3 further has at least one conductive portion 32 located between the light-emitting stack 26 and the reflective layer 242. In another embodiment, the conductive portion 32 may be located between the window layer 248 and the reflective layer 242. The conductive portion 32 is used to conduct current, and its material can be a transparent conductive material or a metal material. The transparent conductive material includes but is not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO) ), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), gallium phosphide (GaP), indium cerium oxide (ICO), Indium tungsten oxide (IWO), indium titanium oxide (ITiO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium aluminum zinc oxide (GAZO) or a combination of the above materials. Metal materials include but are not limited to copper (Cu), aluminum (Al), tin (Sn), gold (Au), silver (Ag), lead (Pb), titanium (Ti), nickel (Ni), platinum (Pt) , Tungsten (W), Germanium (Ge) or alloys of the above materials.

此實施例中,第一透光層244及/或第二透光層246之材料 可為絕緣材料,例如為聚亞醯胺(PI)、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、氧化鎂(MgO)、Su8、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)、氟碳聚合物(Fluorocarbon Polymer)、玻璃(Glass)、氧化鋁(Al2O3)、氧化矽(SiOx)、氧化鈦(TiO2)、氧化鉭(Ta2O5)、氮化矽(SiNx)、氟化鎂(MgF2)、旋塗玻璃(SOG)或四乙氧基矽烷(TEOS)。 In this embodiment, the material of the first light-transmitting layer 244 and/or the second light-transmitting layer 246 may be an insulating material, such as polyimide (PI), benzocyclobutene (BCB), or perfluorocyclobutene. Alkyl (PFCB), Magnesium Oxide (MgO), Su8, Epoxy, Acrylic Resin, Cycloolefin Polymer (COC), Polymethyl Methacrylate (PMMA), Polyterephthalic Acid Ethylene Diester (PET), Polycarbonate (PC), Polyetherimide, Fluorocarbon Polymer, Glass, Alumina (Al 2 O 3 ), Silicon Oxide (SiO x ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), silicon nitride (SiN x ), magnesium fluoride (MgF 2 ), spin-on glass (SOG) or tetraethoxysilane (TEOS) .

第5圖為本申請案另一實施例之發光元件之剖面圖。如第5圖所示,一發光元件5具有一基板50;一發光疊層52,位於基板50之上;一反射結構54,位於發光疊層52之上;以及一電極56,位於反射結構54之上。發光疊層52具有一第一半導體層522,位於基板50之上;一主動層524,位於第一半導體層522之上;以及一第二半導體層526,位於主動層524之上,其中部分第二半導體層526與主動層524被移除以裸露第一半導體層522。 Fig. 5 is a cross-sectional view of a light-emitting device according to another embodiment of the application. As shown in FIG. 5, a light-emitting element 5 has a substrate 50; a light-emitting stack 52 on the substrate 50; a reflective structure 54 on the light-emitting stack 52; and an electrode 56 on the reflective structure 54 Above. The light-emitting stack 52 has a first semiconductor layer 522 located on the substrate 50; an active layer 524 located on the first semiconductor layer 522; and a second semiconductor layer 526 located on the active layer 524, part of which is The second semiconductor layer 526 and the active layer 524 are removed to expose the first semiconductor layer 522.

反射結構54具有一窗戶層540,位於發光疊層52之上;一第一透光層542,位於窗戶層540之上;一反射層544,位於第一透光層542之上;以及一第一絕緣層546,位於反射層544之上。窗戶層540具有一粗化上表面541,粗化上表面具有複數個凸部543與凹部545。至少一孔洞547形成於第一透光層542之中,且位於粗化上表面541之上,孔洞547之折射率小於窗戶層540與第一透光層542之折射率。另一實施例中,孔洞547可自凹部545向上延伸。由於孔洞547之折射率小於窗戶層540與 第一透光層542之折射率,在窗戶層540與孔洞547間之介面的臨界角小於窗戶層540與第一透光層542間之介面的臨界角,所以發光疊層52所發之光射向孔洞547後,在窗戶層540與孔洞547之間的介面形成全反射的機率增加。此外,原本在窗戶層540與第一透光層542介面未形成全反射而進入第一透光層542之光,在第一透光層542與孔洞547之間的介面亦會形成全反射,因而提升發光元件5的出光效率,孔洞547由剖面圖觀之可以為下寬上窄的倒漏斗狀。因為發光疊層52所發之光在窗戶層540與孔洞547之間的介面和第一透光層542與孔洞547之間的介面形成全反射的機率增加,降低光到達電極56而被電極56吸收的機率,提升發光元件5之發光效率。第一絕緣層546可包覆反射層544以使反射層544不與電極56直接接觸,避免反射層544之材料擴散至電極56,降低反射層544之反射率。反射結構54更包含複數個通道549形成於第一透光層542與第一絕緣層546之中,電極56可經由通道549與發光疊層52電連結。反射結構54可更包含一第二透光層548,第二透光層548位於部分第一透光層542與反射層544之間,第二透光層548不具有孔洞,可避免反射層544之材料擴散至孔洞之中,破壞反射層544的結構,導致反射層544的反射率降低。 The reflective structure 54 has a window layer 540 on the light-emitting stack 52; a first transparent layer 542 on the window layer 540; a reflective layer 544 on the first transparent layer 542; and a An insulating layer 546 is located on the reflective layer 544. The window layer 540 has a roughened upper surface 541, and the roughened upper surface has a plurality of convex portions 543 and concave portions 545. At least one hole 547 is formed in the first transparent layer 542 and is located on the roughened upper surface 541. The refractive index of the hole 547 is smaller than the refractive index of the window layer 540 and the first transparent layer 542. In another embodiment, the hole 547 may extend upward from the recess 545. Since the refractive index of the hole 547 is smaller than that of the window layer 540 and The refractive index of the first transparent layer 542, the critical angle of the interface between the window layer 540 and the hole 547 is smaller than the critical angle of the interface between the window layer 540 and the first transparent layer 542, so the light emitted by the light-emitting laminate 52 After shooting toward the hole 547, the probability of forming a total reflection at the interface between the window layer 540 and the hole 547 increases. In addition, the light entering the first light-transmitting layer 542 without being totally reflected at the interface between the window layer 540 and the first light-transmitting layer 542 will also form total reflection at the interface between the first light-transmitting layer 542 and the hole 547. Therefore, the light-emitting efficiency of the light-emitting element 5 is improved, and the hole 547 can be in the shape of an inverted funnel with a width at the bottom and a narrow at the top. Because the light emitted from the light-emitting stack 52 has an increased probability of forming total reflection at the interface between the window layer 540 and the hole 547 and the interface between the first light-transmitting layer 542 and the hole 547, the probability of the light reaching the electrode 56 being reduced by the electrode 56 is reduced. The probability of absorption improves the luminous efficiency of the light-emitting element 5. The first insulating layer 546 can cover the reflective layer 544 so that the reflective layer 544 does not directly contact the electrode 56 to prevent the material of the reflective layer 544 from spreading to the electrode 56 and reduce the reflectivity of the reflective layer 544. The reflective structure 54 further includes a plurality of channels 549 formed in the first transparent layer 542 and the first insulating layer 546, and the electrode 56 can be electrically connected to the light emitting stack 52 through the channels 549. The reflective structure 54 may further include a second light-transmitting layer 548. The second light-transmitting layer 548 is located between a portion of the first light-transmitting layer 542 and the reflective layer 544. The second light-transmitting layer 548 has no holes, which can avoid the reflective layer 544. The material diffuses into the holes, destroys the structure of the reflective layer 544, and causes the reflectivity of the reflective layer 544 to decrease.

電極56具有一第一導電層562與一第二導電層564,其中第一導電層562與第二導電層564彼此不直接接觸。第一導電層562經由通道549與第一半導體層522連接,第二導電層564經由通道549與窗戶層540連接。另一實施例中,發光元件5更包含一第一接觸層51位於第一 導電層562與第一半導體層522之間,增加第一導電層562與第一半導體層522之間的歐姆接觸;一第二接觸層53位於第二導電層564與窗戶層540之間,增加第二導電層564與窗戶層540之間的歐姆接觸,降低發光元件5的操作電壓,以提升效率。其中,第一接觸層51與第二接觸層53之材料和上述電極之材料相同。 The electrode 56 has a first conductive layer 562 and a second conductive layer 564, wherein the first conductive layer 562 and the second conductive layer 564 do not directly contact each other. The first conductive layer 562 is connected to the first semiconductor layer 522 via a channel 549, and the second conductive layer 564 is connected to the window layer 540 via a channel 549. In another embodiment, the light-emitting element 5 further includes a first contact layer 51 located on the first Between the conductive layer 562 and the first semiconductor layer 522, the ohmic contact between the first conductive layer 562 and the first semiconductor layer 522 is increased; a second contact layer 53 is located between the second conductive layer 564 and the window layer 540, increasing The ohmic contact between the second conductive layer 564 and the window layer 540 reduces the operating voltage of the light-emitting element 5 to improve efficiency. Among them, the materials of the first contact layer 51 and the second contact layer 53 are the same as the material of the aforementioned electrode.

第6圖係繪示出一燈泡分解示意圖,一燈泡6具有一燈罩61;一透鏡62,置於燈罩61之中;一照明模組64,位於透鏡62之下;一燈座65,具有一散熱槽66,用以承載照明模組64;一連結部67;以及一電連結器68,其中連結部67連結燈座65與電連接器68。照明模組66具有一載體63;以及複數個前述任一實施例之發光元件60,位於載體63之上。 Figure 6 is an exploded schematic diagram of a light bulb. A light bulb 6 has a lamp shade 61; a lens 62 is placed in the lamp shade 61; an illumination module 64 is located under the lens 62; and a lamp holder 65 has a The heat dissipation slot 66 is used to carry the lighting module 64; a connecting portion 67; and an electrical connector 68, wherein the connecting portion 67 connects the lamp holder 65 and the electrical connector 68. The lighting module 66 has a carrier 63; and a plurality of light-emitting elements 60 of any of the foregoing embodiments are located on the carrier 63.

第7A至第7G圖為本申請案另一實施例之發光元件之製造方法。請參閱第7A圖,本實施例之發光元件之製造方法包括提供一個成長基板701以及於成長基板701上形成一發光疊層76。發光疊層76依序包含一第一半導體層762、一活性層764以及一第二半導體層766於成長基板701上。第一半導體層762以及第二半導體層766具有不同的導電型態。例如,第一半導體層762為p型半導體層,第二半導體層766為n型半導體層。第一半導體層762、活性層764以及第二半導體層766包含三五族化合物材料,例如AlgInhGa(1-g-h)P(0≦g≦1,0≦h≦1,0≦g+h≦1)。接著,於發光疊層76上形成一第一透明層744。於第一透明層744形成之前,可以選擇性地形成一第二透明層746。於一實施例中,第二透明層746 與發光疊層76形成一歐姆接觸。於另一實施例中,第二透明層746增加第一透明層744以及發光疊層76之間的黏著力或是電流擴散的能力。第一透明層744以及第二透明層746的材料可讓發光疊層76發出的光穿透。第一透明層744以及第二透明層746的材料包含一透明導電材料,透明導電材料包含,但不限於,氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鋅共摻雜鎵鋁(GAZO)或其等之組合。第一透明層744以及第二透明層746的材料還可包含磷化鎵或類鑽碳(DLC)。於本實施例中,第一透明層744包含氧化銦錫(ITO),第二透明層746包含磷化鎵(GaP)。於另一實施例中,第一透明層744包含一第一透明導電氧化物,第二透明層746包含一不同於第一透明導電氧化物的第二透明導電氧化物。 Figures 7A to 7G show a method of manufacturing a light-emitting device according to another embodiment of the application. Please refer to FIG. 7A. The manufacturing method of the light-emitting element of this embodiment includes providing a growth substrate 701 and forming a light-emitting stack 76 on the growth substrate 701. The light-emitting stack 76 includes a first semiconductor layer 762, an active layer 764, and a second semiconductor layer 766 on the growth substrate 701 in sequence. The first semiconductor layer 762 and the second semiconductor layer 766 have different conductivity types. For example, the first semiconductor layer 762 is a p-type semiconductor layer, and the second semiconductor layer 766 is an n-type semiconductor layer. The first semiconductor layer 762, the active layer 764, and the second semiconductor layer 766 include three or five group compound materials, such as Al g In h Ga (1-gh) P(0≦g≦1, 0≦h≦1, 0≦g +h≦1). Next, a first transparent layer 744 is formed on the light-emitting stack 76. Before the first transparent layer 744 is formed, a second transparent layer 746 may be selectively formed. In one embodiment, the second transparent layer 746 forms an ohmic contact with the light-emitting stack 76. In another embodiment, the second transparent layer 746 increases the adhesion between the first transparent layer 744 and the light-emitting stack 76 or the ability of current diffusion. The materials of the first transparent layer 744 and the second transparent layer 746 can allow the light emitted by the light-emitting stack 76 to penetrate. The material of the first transparent layer 744 and the second transparent layer 746 includes a transparent conductive material. The transparent conductive material includes, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), and cadmium tin oxide. (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO) ), zinc oxide co-doped gallium aluminum (GAZO) or a combination thereof. The materials of the first transparent layer 744 and the second transparent layer 746 may also include gallium phosphide or diamond-like carbon (DLC). In this embodiment, the first transparent layer 744 includes indium tin oxide (ITO), and the second transparent layer 746 includes gallium phosphide (GaP). In another embodiment, the first transparent layer 744 includes a first transparent conductive oxide, and the second transparent layer 746 includes a second transparent conductive oxide different from the first transparent conductive oxide.

接著,請參閱第7B圖,本方法更包括於第一透明層744中形成複數孔穴745。於本實施例中,複數孔穴745是藉由一蝕刻方式形成。蝕刻方式包含例如使用化學溶液沿著第一透明層744的晶粒界面745b蝕刻。化學溶液包含一酸的溶液,例如包含草酸((COOH)2.2H2O)、鹽酸(HCl)、或是硫酸(H2SO)以及氫氟酸(HF)的混和。根據蝕刻步驟的控制,例如蝕刻時間或是蝕刻溶液的組成,孔穴745的剖面形狀實質上為三角形或是梯形。一小開孔形成於孔穴745的上方的周圍。於其中一情況,孔穴745較靠近發光疊層76的第一部分745w之寬度W3大於孔穴745較遠離發光疊層76的第二部分745n之寬度W4。為了清楚表示,請參閱第7B圖的左下圖,複 數孔穴745彼此之間是相通的。第一透明層744包含複數實質上彼此分離但緊密排列的凸出部744c,且如第7B圖所示,各凸出部744c被複數孔穴745圍繞。複數孔穴745以及複數凸出部744c形成一多孔結構。凸出部744c的形狀為一倒置的截頂圓錐或倒置的角錐。各凸出部744c的剖面形狀實質上為一倒置的梯形。同樣地,凸出部744c的剖面形狀可以藉由控制蝕刻步驟,例如蝕刻時間或是蝕刻溶液的組成而調整。第7B圖的右下的放大圖是為了清楚說明凸出部744c,如圖所示,從剖面圖可得知,其中一凸出部744c的底基體744cB1的寬度W1大於凸出部744c的頂基體744cB2的寬度W2的1/3倍,藉以維持機械強度。於一實施例中,當凸出部744c為截頂的圓錐,且凸出部744c的剖面形狀包含具有底基體744cB1的寬度W1大於1/3倍的頂基體744cB2的寬度W2之梯形時,複數孔穴745的總底面積,亦即,全部的複數孔穴745的底表面745a的總面積是介於發光疊層76之面積的50%以及90%之間。也就是說,所有的複數孔穴745在發光疊層76上的投影面積是介於發光疊層76之一表面的面積的50%以及90%之間。於蝕刻步驟之後,可以使用去離子水將化學溶液自第一透明層744沖洗掉。在蝕刻第一透明層744以形成複數孔穴745之後,本方法可選擇性地包含對第一透明層744進行熱處理以降低第一透明層744的片電阻。 Next, referring to FIG. 7B, the method further includes forming a plurality of holes 745 in the first transparent layer 744. In this embodiment, the plurality of holes 745 are formed by an etching method. The etching method includes, for example, etching along the grain interface 745b of the first transparent layer 744 using a chemical solution. Chemical solution comprises a solution of an acid, such as oxalic acid containing ((COOH) 2 .2H 2 O ), hydrochloric acid (HCI), or sulfuric acid (H 2 SO) and hydrofluoric acid (HF) is mixed. According to the control of the etching step, such as the etching time or the composition of the etching solution, the cross-sectional shape of the cavity 745 is substantially triangular or trapezoidal. A small opening is formed around the upper part of the hole 745. In one case, the width W 3 of the first portion 745w of the hole 745 closer to the light-emitting stack 76 is larger than the width W 4 of the second portion 745n of the hole 745 farther from the light-emitting stack 76. For clarity, please refer to the lower left diagram of Figure 7B, the plurality of holes 745 are connected to each other. The first transparent layer 744 includes a plurality of protrusions 744c that are substantially separated from each other but closely arranged, and as shown in FIG. 7B, each protrusion 744c is surrounded by a plurality of holes 745. The plurality of holes 745 and the plurality of protrusions 744c form a porous structure. The shape of the protrusion 744c is an inverted truncated cone or an inverted pyramid. The cross-sectional shape of each protrusion 744c is substantially an inverted trapezoid. Similarly, the cross-sectional shape of the protrusion 744c can be adjusted by controlling the etching step, such as the etching time or the composition of the etching solution. The enlarged view at the bottom right of Figure 7B is to clearly illustrate the protrusion 744c. As shown in the cross-sectional view, the width W 1 of the base body 744cB1 of one of the protrusions 744c is greater than that of the protrusion 744c. The width W 2 of the top substrate 744cB2 is 1/3 times to maintain the mechanical strength. In one embodiment, when the protruding portion 744c is a truncated cone, and the cross-sectional shape of the protruding portion 744c includes a trapezoid with a width W 1 of the bottom substrate 744cB1 greater than 1/3 times the width W 2 of the top substrate 744cB2 , The total bottom area of the plurality of holes 745, that is, the total area of the bottom surface 745a of all the plurality of holes 745 is between 50% and 90% of the area of the light emitting stack 76. In other words, the projected area of all the plurality of holes 745 on the light-emitting stack 76 is between 50% and 90% of the area of one surface of the light-emitting stack 76. After the etching step, deionized water may be used to rinse the chemical solution from the first transparent layer 744. After the first transparent layer 744 is etched to form a plurality of holes 745, the method may optionally include heat-treating the first transparent layer 744 to reduce the sheet resistance of the first transparent layer 744.

接著,請參閱第7C圖,本方法更包含在第一透明層744上形成一反射層742。因為孔穴745的開孔夠小,反射層742不會填入孔穴745中,因此孔穴745中會留有空隙。反射層742包含金屬材料,例如金、銀或鋁。於一實施例中,反射層742包含布拉格反射鏡(Distributed Bragg Reflector)結構。布拉格反射鏡結構包含複數布拉格反射鏡組,其中每一布拉格反射鏡組由一高折射率層以及一低折射率層組成。反射層742、第一透明層744和/或第二透明層746共同形成一全方位反射鏡(Omni-Directional Reflector(ODR)。 Next, referring to FIG. 7C, the method further includes forming a reflective layer 742 on the first transparent layer 744. Because the opening of the hole 745 is small enough, the reflective layer 742 will not fill the hole 745, so there will be a gap in the hole 745. The reflective layer 742 includes a metal material, such as gold, silver, or aluminum. In one embodiment, the reflective layer 742 includes a Bragg reflector (Distributed Bragg Reflector) structure. The Bragg reflector structure includes a plurality of Bragg reflector groups, wherein each Bragg reflector group is composed of a high refractive index layer and a low refractive index layer. The reflective layer 742, the first transparent layer 744 and/or the second transparent layer 746 together form an Omni-Directional Reflector (ODR).

接著,請參閱第7D圖,本方法更包含在反射層742上形成一第一黏結層72a。如第7E圖所示,本方法更包含提供一基板70,以及在基板上形成一第二黏結層72b。基板70包含一導電基板,例如矽基板。第一黏結層72a以及第二黏結層72b包含金(Au)、銦(In)、錫(Sn)、銀(Ag)、銅(Cu)、鎳(Ni)、鉍(Bi)或其等之合金。然後,如第7F圖所示,第一黏結層72a與第二黏結層72b結合共同形成一黏著層72。於結合之後,如第7G圖所示,移除成長基板701。接著,在第二半導體層766上形成一第一電極墊70E1以及一延伸電極70E1’。在基板70上形成一第二電極墊70E2。可選擇性地對第二半導體層766進行粗化製程以形成一粗化表面70R,藉以增加光取出效率。接著,進行微影製程以及蝕刻製程以移除發光疊層76的周圍以及裸露第二透明層746。可能會些許的過蝕刻第二透明層746。最後,一保護層77覆蓋粗化表面70R以及發光疊層76的側壁以保護發光元件免於大氣中造成的損害。於本實施例中,為了更佳的保護,保護層77亦覆蓋發光疊層76的複數側壁。 Next, referring to FIG. 7D, the method further includes forming a first bonding layer 72a on the reflective layer 742. As shown in FIG. 7E, the method further includes providing a substrate 70, and forming a second bonding layer 72b on the substrate. The substrate 70 includes a conductive substrate, such as a silicon substrate. The first bonding layer 72a and the second bonding layer 72b include gold (Au), indium (In), tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi) or the like alloy. Then, as shown in FIG. 7F, the first adhesive layer 72a and the second adhesive layer 72b are combined to form an adhesive layer 72. After the bonding, as shown in FIG. 7G, the growth substrate 701 is removed. Next, a first electrode pad 70E1 and an extension electrode 70E1' are formed on the second semiconductor layer 766. A second electrode pad 70E2 is formed on the substrate 70. A roughening process can be selectively performed on the second semiconductor layer 766 to form a roughened surface 70R, thereby increasing the light extraction efficiency. Then, a lithography process and an etching process are performed to remove the periphery of the light-emitting stack 76 and expose the second transparent layer 746. The second transparent layer 746 may be slightly over-etched. Finally, a protective layer 77 covers the roughened surface 70R and the sidewalls of the light-emitting stack 76 to protect the light-emitting element from damage caused by the atmosphere. In this embodiment, for better protection, the protective layer 77 also covers the multiple sidewalls of the light-emitting stack 76.

第7G圖繪示本申請案之發光元件之剖面示意圖。發光元件7依序包含基板70、黏著層72、反射層742、第一透明層744、第二透明層746以及發光疊層76。發光疊層76依序包含第一半導體層762、活性層 764以及具有粗化表面70R的第二半導體層766。第一電極墊70E1以及延伸電極70E1’在第二半導體層766上。第二電極墊70E2在基板70上。保護層77覆蓋粗化表面70R以及發光疊層76的側壁。第一透明層744包含被複數孔穴745圍繞的凸出部744c。複數孔穴745以及複數凸出部744c形成一多孔結構。當發光疊層76發出的光到達第一透明層744時,藉由具有空隙在其中的孔穴745以及第一透明層744之間的介面的全反射,光會被孔穴745反射或是散射,因而增加發光元件7的光取出效率。發光元件7的各結構的詳細敘述已在前述第7A圖至第7F圖中詳述。 Fig. 7G shows a schematic cross-sectional view of the light-emitting device of the present application. The light-emitting element 7 includes a substrate 70, an adhesive layer 72, a reflective layer 742, a first transparent layer 744, a second transparent layer 746, and a light-emitting stack 76 in this order. The light-emitting stack 76 includes a first semiconductor layer 762, an active layer 764 and a second semiconductor layer 766 having a roughened surface 70R. The first electrode pad 70E1 and the extension electrode 70E1' are on the second semiconductor layer 766. The second electrode pad 70E2 is on the substrate 70. The protective layer 77 covers the roughened surface 70R and the sidewalls of the light-emitting stack 76. The first transparent layer 744 includes a protrusion 744 c surrounded by a plurality of holes 745. The plurality of holes 745 and the plurality of protrusions 744c form a porous structure. When the light emitted by the light-emitting stack 76 reaches the first transparent layer 744, the light will be reflected or scattered by the holes 745 by the total reflection of the interface between the holes 745 with voids therein and the first transparent layer 744, thus The light extraction efficiency of the light emitting element 7 is increased. The detailed description of each structure of the light-emitting element 7 has been described in detail in the aforementioned FIGS. 7A to 7F.

第8A至第8E圖為本申請案另一實施例之發光元件之製造方法。第8F圖繪示發光元件之上視圖。第8E圖繪示發光元件沿著如第8F圖中所示的DD剖面線之剖面示意圖。如第8A圖所示,本實施例之發光元件之製造方法包括提供一個基板80,例如藍寶石基板。發光元件之製造方法更包括於基板80上形成一發光疊層86。發光疊層86包含半導體疊層,其依序包含一第一半導體層862、一活性層864以及一第二半導體層866。第一半導體層862以及第二半導體層866具有不同的導電型態。例如,第一半導體層862為p型半導體層,第二半導體層866為n型半導體層。第一半導體層862、活性層864以及第二半導體層866包含三五族化合物材料,例如AlxInyGa(1-x-y)N(0≦x≦1,0≦y≦1,0≦x+y≦1)。接著,進行微影製程以及蝕刻製程以移除位於裸露區域86E、86E’的第一半導體層862以及活性層864,藉以裸露部份的第二半導體層866。經過蝕刻,可能蝕刻掉部分深度的第二半導體層866。接著,如第8B圖所示,一第一介電層 D1實質上形成在發光疊層86的複數側壁。接著,一第一透明層844實質上形成於第一半導體層862上。於第一透明層844形成之前,可以選擇性地形成一第二透明層846。於一實施例中,第二透明層846與第一半導體層862形成歐姆接觸。於另一實施例中,第二透明層846增加第一透明層844以及發光疊層86之間的黏著力或是電流擴散的能力。第一透明層844以及第二透明層846的材料可讓發光疊層86發出的光穿透。第一透明層844以及第二透明層846的材料包含一透明導電材料,透明導電材料包含,但不限於,氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鋅共摻雜鎵鋁(GAZO)或其等之組合。第一透明層844以及第二透明層846的材料還可包含磷化鎵或類鑽碳(DLC)。於本實施例中,第一透明層844包含氧化銦錫(ITO),第二透明層846包含氧化銦鋅(IZO)。於另一實施例中,第一透明層844包含一第一透明導電氧化物,第二透明層846包含一不同於第一透明導電氧化物的第二透明導電氧化物。 Figures 8A to 8E are a method of manufacturing a light-emitting device according to another embodiment of the application. Figure 8F shows a top view of the light-emitting element. FIG. 8E shows a schematic cross-sectional view of the light-emitting device along the DD section line as shown in FIG. 8F. As shown in FIG. 8A, the manufacturing method of the light-emitting element of this embodiment includes providing a substrate 80, such as a sapphire substrate. The manufacturing method of the light-emitting device further includes forming a light-emitting stack 86 on the substrate 80. The light-emitting stack 86 includes a semiconductor stack, which sequentially includes a first semiconductor layer 862, an active layer 864, and a second semiconductor layer 866. The first semiconductor layer 862 and the second semiconductor layer 866 have different conductivity types. For example, the first semiconductor layer 862 is a p-type semiconductor layer, and the second semiconductor layer 866 is an n-type semiconductor layer. The first semiconductor layer 862, the active layer 864, and the second semiconductor layer 866 include three or five group compound materials, such as Al x In y Ga (1-xy) N(0≦x≦1, 0≦y≦1, 0≦x +y≦1). Then, a lithography process and an etching process are performed to remove the first semiconductor layer 862 and the active layer 864 located in the exposed regions 86E, 86E′, thereby exposing a portion of the second semiconductor layer 866. After etching, a partial depth of the second semiconductor layer 866 may be etched away. Next, as shown in FIG. 8B, a first dielectric layer D1 is substantially formed on the plurality of sidewalls of the light-emitting stack 86. Next, a first transparent layer 844 is formed substantially on the first semiconductor layer 862. Before the first transparent layer 844 is formed, a second transparent layer 846 may be selectively formed. In one embodiment, the second transparent layer 846 and the first semiconductor layer 862 form an ohmic contact. In another embodiment, the second transparent layer 846 increases the adhesion between the first transparent layer 844 and the light emitting stack 86 or the ability of current spreading. The materials of the first transparent layer 844 and the second transparent layer 846 can allow the light emitted by the light-emitting stack 86 to pass through. The material of the first transparent layer 844 and the second transparent layer 846 includes a transparent conductive material. The transparent conductive material includes, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO) ), zinc oxide co-doped gallium aluminum (GAZO) or a combination thereof. The materials of the first transparent layer 844 and the second transparent layer 846 may further include gallium phosphide or diamond-like carbon (DLC). In this embodiment, the first transparent layer 844 includes indium tin oxide (ITO), and the second transparent layer 846 includes indium zinc oxide (IZO). In another embodiment, the first transparent layer 844 includes a first transparent conductive oxide, and the second transparent layer 846 includes a second transparent conductive oxide different from the first transparent conductive oxide.

接著,請參閱第8C圖,本方法更包括於第一透明層844中形成複數孔穴845。同樣地,第一透明層844包含複數凸出部844c,為了清楚說明,其中一凸出部844c表示在右下圓圈內的放大圖中。凸出部844c被複數孔穴845圍繞。形成孔穴845和凸出部844c的詳細方法以及孔穴845和凸出部844c的結構實質上與前述的實施例的內容相同,在此不再贅述。形成孔穴845之後,可以使用去離子水潤洗第一透明層844。本方法 可選擇性地包含對第一透明層844進行熱處理以降低第一透明層844的片電阻。接著,在第一透明層844上形成一反射層842。因為孔穴845的開孔夠小,反射層842不會填入孔穴845中,因此孔穴845中會留有空隙。於本實施例中,反射層84亦包覆第一透明層844以及第二透明層846的側壁。反射層842包含金屬材料,例如金(Au)、銀(Ag)或鋁(Al)。反射層842、第一透明層844和/或第二透明層846共同形成一全方位反射鏡(Omni-Directional Reflector(ODR)。 Next, referring to FIG. 8C, the method further includes forming a plurality of holes 845 in the first transparent layer 844. Similarly, the first transparent layer 844 includes a plurality of protrusions 844c. For clarity of description, one of the protrusions 844c is shown in the enlarged view in the lower right circle. The protrusion 844c is surrounded by a plurality of holes 845. The detailed method of forming the hole 845 and the protrusion 844c and the structure of the hole 845 and the protrusion 844c are substantially the same as the content of the foregoing embodiment, and will not be repeated here. After the holes 845 are formed, the first transparent layer 844 can be rinsed with deionized water. This method It may optionally include heat-treating the first transparent layer 844 to reduce the sheet resistance of the first transparent layer 844. Next, a reflective layer 842 is formed on the first transparent layer 844. Because the opening of the hole 845 is small enough, the reflective layer 842 will not fill the hole 845, so there will be a gap in the hole 845. In this embodiment, the reflective layer 84 also covers the sidewalls of the first transparent layer 844 and the second transparent layer 846. The reflective layer 842 includes a metal material, such as gold (Au), silver (Ag), or aluminum (Al). The reflective layer 842, the first transparent layer 844 and/or the second transparent layer 846 together form an Omni-Directional Reflector (ODR).

如第8D圖所示,本方法更包含於反射層842、第一介電層D1以及發光疊層86上形成一第二介電層D2。移除位於裸露區域D2E、D2E’的第二介電層D2以裸露第二半導體層866以及部分的反射層842,其中裸露區域D2E實質上對應裸露區域86E。本方法更包含於第二介電層D2以及第二半導體層866上形成一導電層M1。導電層M1與第二半導體層866接觸。 As shown in FIG. 8D, the method further includes forming a second dielectric layer D2 on the reflective layer 842, the first dielectric layer D1, and the light-emitting stack 86. The second dielectric layer D2 located in the exposed areas D2E, D2E' is removed to expose the second semiconductor layer 866 and part of the reflective layer 842, wherein the exposed area D2E substantially corresponds to the exposed area 86E. The method further includes forming a conductive layer M1 on the second dielectric layer D2 and the second semiconductor layer 866. The conductive layer M1 is in contact with the second semiconductor layer 866.

接著,如第8E圖所示,本方法更包含於第二介電層D2上、導電層M1、反射層842以及第二半導體層866上形成一第三介電層D3。移除實質上位於裸露區域D2E’的第三介電層D3以裸露反射層842。本方法更包含於第三介電層D3、反射層842以及導電層M1上形成一第二導電層,接著再移除實質上位於區域M2E的第二導電層以形成一第一電極墊80E1以及一第二電極墊80E2。第一電極墊80E1接觸導電層M1,導電層M1接觸第二半導體層866。換言之,導電層M1作為一個中間導電材料且電連接至第一電極墊80E1以及第二半導體層866。一電源供應器藉由第一 電極墊80E1以及導電層M1提供一電流至第二半導體層866。第二電極墊80E2接觸反射層842。一電源供應器藉由第二電極墊80E2、反射層842以及第一透明層844提供一電流至第一半導體層862。 Next, as shown in FIG. 8E, the method further includes forming a third dielectric layer D3 on the second dielectric layer D2, the conductive layer M1, the reflective layer 842, and the second semiconductor layer 866. The third dielectric layer D3 substantially located in the exposed area D2E' is removed to expose the reflective layer 842. The method further includes forming a second conductive layer on the third dielectric layer D3, the reflective layer 842, and the conductive layer M1, and then removing the second conductive layer substantially located in the region M2E to form a first electrode pad 80E1 and A second electrode pad 80E2. The first electrode pad 80E1 contacts the conductive layer M1, and the conductive layer M1 contacts the second semiconductor layer 866. In other words, the conductive layer M1 serves as an intermediate conductive material and is electrically connected to the first electrode pad 80E1 and the second semiconductor layer 866. A power supply with the first The electrode pad 80E1 and the conductive layer M1 provide a current to the second semiconductor layer 866. The second electrode pad 80E2 contacts the reflective layer 842. A power supply provides a current to the first semiconductor layer 862 through the second electrode pad 80E2, the reflective layer 842 and the first transparent layer 844.

第9A圖至9E圖繪示本申請案另一實施例之發光元件及其製造方法。第9F圖繪示發光元件之上視圖。第9E圖繪示發光元件沿著如第9F圖中所示的HIJK剖面線之剖面示意圖。如第9A圖所示,製造發光元件之方法包含提供一基板90,例如藍寶石基板。製造發光元件之方法更包含於基板90上形成一發光疊層96。發光疊層96包含半導體疊層,其依序包含一第一半導體層962、一活性層964以及一第二半導體層966。第一半導體層962以及第二半導體層966具有不同的導電型態。例如,第一半導體層962為p型半導體層,第二半導體層966為n型半導體層。第一半導體層962、活性層964以及第二半導體層966包含三五族化合物材料,例如AlxInyGa(1-x-y)N(0≦x≦1,0≦y≦1,0≦x+y≦1)。接著,進行微影製程以及蝕刻製程以移除位於裸露區域96E、96E’的第一半導體層962以及活性層964,藉以裸露部份的第二半導體層966。因為裸露區域96E,96E’經過蝕刻,可能蝕刻掉部分深度的第二半導體層966。接著,如第9B圖所示,可以選擇性地形成一電流阻擋層90CB。電流阻擋層90CB包含一介電材料以阻擋電流流過。接著,形成一第一透明層944於第一半導體層962以及電流阻擋層90CB上。於第一透明層944形成之前,可以選擇性形成一第二透明層946。於一實施例中,第二透明層946與第一半導體層962形成歐姆接觸。於另一實施例中,第二透明層946增加第一透明層944以 及發光疊層96之間的黏著力或是電流擴散的能力。第一透明層944以及第二透明層946的材料可讓發光疊層96發出的光穿透。第一透明層944以及第二透明層946的材料包含一透明導電材料,透明導電材料包含,但不限於,氧化銦錫(ITO)、氧化銦(InO)、氧化錫(SnO)、氧化鎘錫(CTO)、氧化銻錫(ATO)、氧化鋁鋅(AZO)、氧化鋅錫(ZTO)、氧化鎵鋅(GZO)、氧化鋅(ZnO)、氧化銦鋅(IZO)、氧化銦鎵(IGO)、氧化鋅共摻雜鎵鋁(GAZO)或其等之組合。第一透明層944以及第二透明層946的材料還可包含磷化鎵或類鑽碳(DLC)。於本實施例中,第一透明層944包含氧化銦錫(ITO),第二透明層946包含氧化銦鋅(IZO)。於另一實施例中,第一透明層944包含一第一透明導電氧化物,第二透明層846包含一不同於第一透明導電氧化物的第二透明導電氧化物。 FIGS. 9A to 9E show a light-emitting device and its manufacturing method according to another embodiment of the present application. Figure 9F shows a top view of the light-emitting element. FIG. 9E shows a schematic cross-sectional view of the light-emitting device along the HIJK section line as shown in FIG. 9F. As shown in FIG. 9A, the method of manufacturing a light-emitting device includes providing a substrate 90, such as a sapphire substrate. The method of manufacturing the light-emitting device further includes forming a light-emitting stack 96 on the substrate 90. The light emitting stack 96 includes a semiconductor stack, which sequentially includes a first semiconductor layer 962, an active layer 964, and a second semiconductor layer 966. The first semiconductor layer 962 and the second semiconductor layer 966 have different conductivity types. For example, the first semiconductor layer 962 is a p-type semiconductor layer, and the second semiconductor layer 966 is an n-type semiconductor layer. The first semiconductor layer 962, the active layer 964, and the second semiconductor layer 966 include a three-five group compound material, such as Al x In y Ga (1-xy) N(0≦x≦1, 0≦y≦1, 0≦x +y≦1). Then, a photolithography process and an etching process are performed to remove the first semiconductor layer 962 and the active layer 964 in the exposed regions 96E and 96E′, thereby exposing a portion of the second semiconductor layer 966. Because the exposed regions 96E and 96E' are etched, a partial depth of the second semiconductor layer 966 may be etched away. Next, as shown in FIG. 9B, a current blocking layer 90CB can be selectively formed. The current blocking layer 90CB includes a dielectric material to block current flow. Next, a first transparent layer 944 is formed on the first semiconductor layer 962 and the current blocking layer 90CB. Before the first transparent layer 944 is formed, a second transparent layer 946 may be selectively formed. In one embodiment, the second transparent layer 946 and the first semiconductor layer 962 form an ohmic contact. In another embodiment, the second transparent layer 946 increases the adhesion between the first transparent layer 944 and the light-emitting stack 96 or the ability of current diffusion. The materials of the first transparent layer 944 and the second transparent layer 946 can allow the light emitted by the light-emitting stack 96 to pass through. The material of the first transparent layer 944 and the second transparent layer 946 includes a transparent conductive material. The transparent conductive material includes, but is not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), and cadmium tin oxide. (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO) ), zinc oxide co-doped gallium aluminum (GAZO) or a combination thereof. The materials of the first transparent layer 944 and the second transparent layer 946 may also include gallium phosphide or diamond-like carbon (DLC). In this embodiment, the first transparent layer 944 includes indium tin oxide (ITO), and the second transparent layer 946 includes indium zinc oxide (IZO). In another embodiment, the first transparent layer 944 includes a first transparent conductive oxide, and the second transparent layer 846 includes a second transparent conductive oxide different from the first transparent conductive oxide.

接著,如第9C圖所示,本方法更包含於第一透明層944中形成複數孔穴945。同樣地,第一透明層944包含複數凸出部944c,為了清楚說明,其中一凸出部944c表示在右下圓圈內的放大圖中。凸出部944c被複數孔穴945圍繞。形成孔穴945和凸出部944c的詳細方法以及孔穴945和凸出部944c的結構實質上與前述的實施例的內容相同,在此不再贅述。值得注意的是,於本實施例中,孔穴945並未形成在第一透明層944之位於電流阻擋層90CB上的區域中。形成孔穴945之後,可以使用去離子水潤洗第一透明層944。本方法可選擇性地包含對第一透明層944進行熱處理以降低第一透明層944的片電阻。接著,藉由使用微影製程以及蝕刻製程形成以圖案化導電層,藉以形成中間導電層MF1、MF1E。如第9F 圖的上視圖所示,中間導電層MF1E是自形狀為圓形的中間導電層MF1延伸的延伸電極。同時形成一中間導電層MF1’、MF1’E(MF1’E並未繪示於第9C圖中但繪示於第9F圖中),如第9F圖所示,中間導電層MF1’E是自形狀為圓形的中間導電層MF1’延伸的延伸電極。中間導電層MF1,MF1E形成在裸露區域96E以及於第二半導體層966上。中間導電層MF1,MF1E接觸第二半導體層966。中間導電層MF1’,MF1’E形成在第一透明層944上且接觸第一透明層944,其中中間導電層MF1是位於如前所述的電流阻擋層90CB上,而中間導電層MF1’E下並未有電流阻擋層90CB。 Next, as shown in FIG. 9C, the method further includes forming a plurality of holes 945 in the first transparent layer 944. Similarly, the first transparent layer 944 includes a plurality of protrusions 944c. For clear description, one of the protrusions 944c is shown in the enlarged view in the lower right circle. The protrusion 944c is surrounded by a plurality of holes 945. The detailed method for forming the cavity 945 and the protrusion 944c and the structure of the cavity 945 and the protrusion 944c are substantially the same as the content of the foregoing embodiment, and will not be repeated here. It is worth noting that, in this embodiment, the hole 945 is not formed in the region of the first transparent layer 944 on the current blocking layer 90CB. After the holes 945 are formed, the first transparent layer 944 can be rinsed with deionized water. The method may optionally include heat-treating the first transparent layer 944 to reduce the sheet resistance of the first transparent layer 944. Then, the conductive layer is patterned by using a photolithography process and an etching process to form the intermediate conductive layers MF1 and MF1E. Such as 9F As shown in the top view of the figure, the intermediate conductive layer MF1E is an extension electrode extending from the intermediate conductive layer MF1 having a circular shape. Form an intermediate conductive layer MF1' and MF1'E at the same time (MF1'E is not shown in Figure 9C but shown in Figure 9F). As shown in Figure 9F, the intermediate conductive layer MF1'E is self-contained An extension electrode extending from the intermediate conductive layer MF1' in a circular shape. The intermediate conductive layers MF1 and MF1E are formed on the exposed area 96E and on the second semiconductor layer 966. The intermediate conductive layers MF1, MF1E contact the second semiconductor layer 966. The intermediate conductive layers MF1', MF1'E are formed on the first transparent layer 944 and contact the first transparent layer 944, wherein the intermediate conductive layer MF1 is located on the current blocking layer 90CB as described above, and the intermediate conductive layer MF1'E There is no current blocking layer 90CB underneath.

接著,如第9D圖所示,本方法更包含形成一反射層942。因為孔穴945的開孔夠小,反射層942不會填入孔穴945中,因此孔穴945中會留有空隙。於本實施例中,形成一布拉格反射鏡(Distributed Bragg Reflector)結構942以包覆前述結構裸露的部分,且藉由微影製程以及蝕刻製程移除位於裸露區域942E的布拉格反射鏡結構942。裸露區域942E實質上對應於中間導電層MF1,MF1’的位置。布拉格反射鏡結構942包含複數布拉格反射鏡組,其中每一布拉格反射鏡組由一具有高折射率的層以及一具有低折射率的層組成。本實施例中,各布拉格反射鏡組由一氧化鈦層(Titanium Oxide,TiOx)以及一氧化矽層(Silicon Oxide,SiOx)所組成。 Next, as shown in FIG. 9D, the method further includes forming a reflective layer 942. Because the opening of the hole 945 is small enough, the reflective layer 942 will not fill the hole 945, so there will be a gap in the hole 945. In this embodiment, a Distributed Bragg Reflector structure 942 is formed to cover the exposed part of the aforementioned structure, and the Bragg reflector structure 942 in the exposed area 942E is removed by a photolithography process and an etching process. The bare area 942E substantially corresponds to the position of the middle conductive layer MF1, MF1'. The Bragg mirror structure 942 includes a plurality of Bragg mirror groups, where each Bragg mirror group is composed of a layer with a high refractive index and a layer with a low refractive index. In this embodiment, each Bragg reflector group is composed of a titanium oxide layer (TiO x ) and a silicon oxide layer (Silicon Oxide, SiO x ).

接著,如第9E圖所示,本方法更包含於布拉格反射鏡結構942上形成一導電層,以及移除實質上位於區域M2E的導電層以形成一第一電極墊90E1以及一第二電極墊90E2。第一電極墊90E1接觸中間導電層 MF1,中間導電層MF1接觸第二半導體層966。換言之,中間導電層MF1作為一個中間導電媒介且電連接第一電極墊90E1以及第二半導體層966。除此之外,中間導電層MF1E作為一增加電流擴散的延伸電極。一電源供應器藉由第一電極墊90E1以及中間導電層MF1、MF1E提供電流至第二半導體層966。第二電極墊90E2接觸中間導電層MF1’,且中間導電層MF1’接觸第一透明層944。第一透明層944電連接至第一半導體層962。除此之外,如第9F圖所示,中間導電層MF1’E作為增加電流擴散的延伸電極。一電源供應器藉由第二電極墊90E2、中間導電層MF1’、MF1’E以及第一透明層944(以及第二透明層946,如果有形成第二透明層946)提供電流至第一半導體層962。 Next, as shown in FIG. 9E, the method further includes forming a conductive layer on the Bragg mirror structure 942, and removing the conductive layer substantially located in the region M2E to form a first electrode pad 90E1 and a second electrode pad 90E2. The first electrode pad 90E1 contacts the middle conductive layer MF1, the intermediate conductive layer MF1 contacts the second semiconductor layer 966. In other words, the intermediate conductive layer MF1 serves as an intermediate conductive medium and electrically connects the first electrode pad 90E1 and the second semiconductor layer 966. In addition, the middle conductive layer MF1E serves as an extension electrode to increase current diffusion. A power supply provides current to the second semiconductor layer 966 through the first electrode pad 90E1 and the intermediate conductive layers MF1 and MF1E. The second electrode pad 90E2 contacts the intermediate conductive layer MF1', and the intermediate conductive layer MF1' contacts the first transparent layer 944. The first transparent layer 944 is electrically connected to the first semiconductor layer 962. In addition, as shown in Fig. 9F, the intermediate conductive layer MF1'E serves as an extension electrode for increasing current diffusion. A power supply provides current to the first semiconductor through the second electrode pad 90E2, the intermediate conductive layers MF1', MF1'E, and the first transparent layer 944 (and the second transparent layer 946, if a second transparent layer 946 is formed) Layer 962.

以上各圖式與說明雖僅分別對應特定實施例,然而,各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外,吾人當可依其所需任意參照、交換、搭配、協調、或合併。 Although the above drawings and descriptions only correspond to specific embodiments respectively, however, the elements, implementations, design criteria, and technical principles described or disclosed in the various embodiments are in conflict, contradictory, or difficult to implement together. In addition, we can refer to, exchange, match, coordinate, or merge as needed.

雖然本申請揭示之內容已說明如上,然其並非用以限制本申請之範圍、實施順序、或使用之材料與製程方法。對於本申請內容所作之各種修飾與變更,皆不脫本申請內容之精神與範圍。 Although the content disclosed in this application has been described above, it is not intended to limit the scope of this application, the order of implementation, or the materials and manufacturing methods used. Various modifications and changes made to the content of this application do not depart from the spirit and scope of the content of this application.

70:基板 70: substrate

70E2:第二電極墊 70E2: second electrode pad

72:黏著層 72: Adhesive layer

742:反射層 742: reflective layer

745:孔穴 745: hole

745a:底表面 745a: bottom surface

744:第一透明層 744: first transparent layer

744c:凸出部 744c: protrusion

746:第二透明層 746: second transparent layer

762:第一半導體層 762: first semiconductor layer

764:活性層 764: active layer

766:第二半導體層 766: second semiconductor layer

76:發光疊層 76: luminous stack

77:保護層 77: protective layer

70E1’:延伸電極 70E1’: Extension electrode

70E1:第一電極墊 70E1: the first electrode pad

Claims (10)

一發光元件,其包括:一基板;一發光疊層,位於該基板上且包含一活性層;一第一電極墊及一第二電極墊位於該發光疊層上且位於該基板的同一側;一第一透明層,位於該基板及該第一電極墊之間;一第二透明層,位於該第一透明層及該發光疊層之間;以及一孔洞,位於該第一透明層中且未形成於該第二透明層中。 A light-emitting element, comprising: a substrate; a light-emitting stack located on the substrate and including an active layer; a first electrode pad and a second electrode pad located on the light-emitting stack and on the same side of the substrate; A first transparent layer is located between the substrate and the first electrode pad; a second transparent layer is located between the first transparent layer and the light-emitting stack; and a hole is located in the first transparent layer and Not formed in the second transparent layer. 如請求項1所述的發光元件,更包含一介電層,位於該第一電極墊及該第一透明層之間。 The light-emitting device according to claim 1, further comprising a dielectric layer located between the first electrode pad and the first transparent layer. 如請求項2所述的發光元件,其中,該發光疊層具有一側壁,且該介電層位於該側壁上。 The light-emitting device according to claim 2, wherein the light-emitting stack has a side wall, and the dielectric layer is located on the side wall. 如請求項1所述的發光元件,其中,該第一透明層具有一第一表面和一第二表面,該複數孔洞係從該第一表面延伸但未延伸至該第二表面。 The light-emitting element according to claim 1, wherein the first transparent layer has a first surface and a second surface, and the plurality of holes extend from the first surface but do not extend to the second surface. 如請求項1所述的發光元件,更包含一導電層,其中,該發光疊層包含一裸露區域,且該導電層位於該裸露區域上。 The light-emitting element according to claim 1, further comprising a conductive layer, wherein the light-emitting stack comprises a bare area, and the conductive layer is located on the bare area. 如請求項5所述的發光元件,還包含一反射結構,其中,該導電層具有一上表面被該反射結構所覆蓋。 The light-emitting element according to claim 5, further comprising a reflective structure, wherein the conductive layer has an upper surface covered by the reflective structure. 如請求項1所述的發光元件,其中,該第二電極墊位於該反射結構上且於一垂直方向上與該導電層重疊。 The light-emitting element according to claim 1, wherein the second electrode pad is located on the reflective structure and overlaps the conductive layer in a vertical direction. 如請求項1所述的發光元件,更包含一反射層覆蓋該發光疊層的一側壁。 The light-emitting element according to claim 1, further comprising a reflective layer covering a side wall of the light-emitting stack. 一種發光元件,包含一發光疊層,包含一第一半導體層、一活性層及一第二半導體層,其中,該第一半導體層具有一部分係從該活性層與該第二半導體層中裸露出來;一反射層,位於該發光疊層上;一第一導電層,位於該反射層上;一絕緣層,位於該反射層和該第一導電層之間以電隔離該反射層和該第一導電層;以及一導電透明層,位於該發光疊層和該反射層之間且具有複數個凸出部。 A light-emitting element includes a light-emitting stack, including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein a portion of the first semiconductor layer is exposed from the active layer and the second semiconductor layer A reflective layer located on the light-emitting stack; a first conductive layer located on the reflective layer; an insulating layer located between the reflective layer and the first conductive layer to electrically isolate the reflective layer and the first A conductive layer; and a conductive transparent layer located between the light-emitting stack and the reflective layer and has a plurality of protrusions. 如請求項9所述的發光元件,更包含一第二導電層,位於該反射層上。 The light-emitting element according to claim 9, further comprising a second conductive layer on the reflective layer.
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