TWI698550B - 半導體製造裝置 - Google Patents

半導體製造裝置 Download PDF

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TWI698550B
TWI698550B TW108124435A TW108124435A TWI698550B TW I698550 B TWI698550 B TW I698550B TW 108124435 A TW108124435 A TW 108124435A TW 108124435 A TW108124435 A TW 108124435A TW I698550 B TWI698550 B TW I698550B
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groove
film
semiconductor manufacturing
semiconductor substrate
stage
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TW202031930A (zh
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浅井俊晶
阿佐見範之
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供可以回避電弧之產生的半導體製造裝置。 一實施形態的半導體製造裝置，係具備：支撐半導體基板的載台；及以圍繞半導體基板的方式設置於載台之外周部的導電性之環狀構件。載台，係具有設置於環狀構件之內周端之下部的溝。

Description

半導體製造裝置
本發明之實施形態係關於半導體製造裝置。 [關連申請] 本申請享受日本專利申請2019-33178號(申請日：2019年2月26日)之基礎申請的優先權。本申請藉由參照該基礎申請而包含基礎申請之全部之內容。
半導體製造裝置中已知有在產生電漿之狀態下於半導體基板上形成導電膜的成膜裝置。在這樣的成膜裝置中，半導體基板係載置於載台上。又，為了均勻地產生電漿，於載台之外周部設置有稱為邊環的環狀構件。 在上述這樣的成膜裝置中產生電漿時，膜不僅形成於半導體基板上，亦形成於邊環上及載台上。因此基於形成於半導體基板上的膜與從邊環至載台為止連續的膜之間的電位差，會有產生電弧(arcing)之情況。該情況下，成膜裝置需要停止阻礙統一性成膜。又，裝置內之元件基於電弧亦有可能破損。
本發明之實施形態提供可以回避電弧之產生的半導體製造裝置。 一實施形態的半導體製造裝置，係具備：支撐半導體基板的載台；及導電性之環狀構件，係以圍繞半導體基板的方式設置於載台之外周部。載台，係具有設置於環狀構件之內周端之下部的溝。
以下，參照圖面說明本發明之實施形態。本實施形態並非用來限定本發明者。 (第1實施形態) 圖1係表示第1實施形態的半導體製造裝置之概略的剖面圖。圖2係圖1所示區域R之擴大圖。圖3係第1實施形態的半導體製造裝置之重要部分之平面圖。 圖1、圖2、及圖3所示半導體製造裝置1，係在產生電漿之狀態下藉由CVD(Chemical Vapor Deposition)法進行成膜的電漿CVD裝置。該半導體製造裝置1具備：載台10；邊環20；及電極板30。 於載台10之上面載置有晶圓狀之半導體基板100。載台10具有對半導體基板100進行加熱的加熱功能。又，於載台10之上面設置有溝11。溝11，如圖3所示，為環狀溝。 邊環20，係以圍繞半導體基板100的方式設置於載台10之外周部，為具有梯形狀之剖面的環狀構件。邊環20係由導電性之材料形成。 電極板30與載台10及邊環20呈對向。在對電極板30供給高頻電力時，於電極板30與載台10之間產生電漿。 本實施形態中，導電性之邊環20設置於載台10之外周部。因此電漿於載台10之中央部與外周部之間均勻地產生。又，為了均勻地產生電漿，較好是邊環20之高度h為半導體基板100之厚度t以上。 本實施形態中，在產生電漿的狀態下導入成膜氣體(未圖示)時，如圖1及圖2所示，膜101a形成於支撐於載台10的半導體基板100上。若電漿均勻地產生，則膜101a之厚度亦成為均勻。又，與膜101a同時，膜101b亦形成於載台10上，膜101c形成於邊環20上。本實施形態中，膜101a、膜101b、及膜101c為使用於遮罩碳膜。但是，各膜可以是碳膜以外之導電膜。 圖4係將比較例的半導體製造裝置之一部分擴大的剖面圖。該半導體製造裝置中，載台10不具有溝11。因此上述成膜工程之結果，形成於載台10上的膜101b，與形成於邊環20上的膜101c成為一體。膜101c與形成於半導體基板100上的膜101a之間的電位差大。因此和膜101c為同電位的膜101b，與膜101a間之電位差亦變大，結果，產生電弧效應。 另一方面，本實施形態的半導體製造裝置1中，係如圖2所示，載台10具有設置於邊環20之內周端20a之下部的溝11。藉由溝11使邊環20之內周端20a與載台10之空間距離擴大。藉此，載台10上之膜101b，係從邊環20上之膜101c分離而形成。亦即，膜101b係從與膜101a間之電位差為較大的膜101c分離。 因此，依據本實施形態，膜101a與膜101b之間的電位差可以減少，因此可以回避電弧效應。藉此，在半導體基板100上可以總括進行膜101a之成膜。亦可以回避電弧引起的元件之破損。 (變形例1) 圖5係變形例1的溝11之剖面圖。上述第1實施形態中，如圖2所示，溝11之內緣部11a，係位於半導體基板100之外周端之下部與邊環20之內周端20a之下部之間。相對於此，於圖5所示溝11中，內緣部11a係位於半導體基板100之外周端之下部。亦即，內緣部11a較邊環20之內周端20a之下部位於更靠近載台10之中央側即可。 依據本變形例，和第1實施形態同樣地，溝11之外緣部11b較邊環20之內周端20a之下部位於更靠近載台10之外周側，因此膜101b可以從膜101c分離。 (變形例2) 圖6為變形例2的溝11之剖面圖。又，圖7為變形例2的溝11之平面圖。 上述第1實施形態中，如圖3所示，溝11係沿著邊環20之內周端20a之全周設置的1個環狀溝。另一方面，本變形例中，如圖6及圖7所示，於上述環狀溝之內側還形成有另一溝11。亦即，溝11為2重之環狀溝。 本變形例中，亦可以使形成於載台10上的膜101b與形成於邊環20上的膜101c分離。因此，在半導體基板100上形成膜101a時可以回避電弧現象。又，溝11亦可以是較2重更多重之環狀溝。 (變形例3) 圖8係變形例3的溝11之剖面圖。上述第1實施形態中，如圖3所示，溝11為沿著邊環20之內周端20a之全周呈連續的環狀溝。另一方面，本變形例的溝11，係如圖8所示，溝11為沿著邊環20之內周端20a斷續設置的溝。 依據本變形例，和溝11未形成於載台10之比較例(參照圖4)比較，可以抑制電弧之產生。 (第2實施形態) 圖9係第2實施形態的半導體製造裝置之概略的剖面圖。又，圖10係表示第2實施形態的邊環20之支撐形態之斜視圖。和上述第1實施形態為同樣構成之要素附加同一符號，並省略詳細說明。 如圖9所示，本實施形態的半導體製造裝置2中，邊環20設置於載台10之外側。亦即，載台10係從邊環20分離。又，如圖10所示，邊環20係藉由4個支撐腳40支撐。又，支撐腳40之個數在可以支撐邊環20的範圍內即可並無限制。 如上述般構成的半導體製造裝置2中，載台10與邊環20之間係藉由空間隔開。因此如圖9所示，在藉由電漿CVD之成膜工程中，形成於載台10上的膜101b與形成於邊環20上的膜101c呈分離。藉此，形成於半導體基板100上的膜101a與膜101b之間的電位差減少。因此，本實施形態中，亦和第1實施形態同樣地，可以回避電弧效應。 說明本發明之幾個實施形態，但彼等實施形態僅為例示者，並非用來限定發明之範圍。彼等實施形態，可以藉由其他各樣的形態實施，在不脫離發明之要旨之範圍內，可以各樣的形態進行省略、置換、變更。彼等實施形態或其變形包含於發明之範圍或要旨，同樣地，亦包含於申請專利範圍記載的發明及其均等之範圍。
1、2:半導體製造裝置 10:載台 11:溝 20:邊環(環狀構件) 40:支撐腳 100:半導體基板
[圖1]第1實施形態的半導體製造裝置之概略的平面圖。 [圖2]圖1所示區域R之擴大圖。 [圖3]第1實施形態的半導體製造裝置之重要部分之平面圖。 [圖4]將比較例的半導體製造裝置之一部分予以擴大的剖面圖。 [圖5]變形例1的溝之剖面圖。 [圖6]變形例2的溝之剖面圖。 [圖7]變形例2的溝之平面圖。 [圖8]變形例3的溝之剖面圖。 [圖9]第2實施形態的半導體製造裝置之概略的剖面圖。 [圖10]表示第2實施形態的邊環之支撐形態之斜視圖。
1:半導體製造裝置
10:載台
11:溝
20:邊環(環狀構件)
100:半導體基板
101a、101b、101c:膜
R:區域
h:邊環之高度
t:半導體基板之厚度
30:電極板

Claims (5)

  1. 一種半導體製造裝置，係具備： 支撐半導體基板的載台；及 導電性之環狀構件，係以圍繞上述半導體基板的方式設置於上述載台之外周部； 上述載台，係具有：溝，其設置於上述環狀構件之內周端之下部。
  2. 如申請專利範圍第1項之半導體製造裝置，其中 上述溝為，沿著上述環狀構件之內周端之全周設置的環狀溝。
  3. 如申請專利範圍第1或2項之半導體製造裝置，其中 上述溝之內緣部，係較上述內周端之上述下部位於更靠近上述載台之中央側， 上述溝之外緣部，係較上述內周端之上述下部位於更靠近上述載台之外周側。
  4. 如申請專利範圍第3項之半導體製造裝置，其中 上述溝之上述內緣部，係位於上述半導體基板之外周端之下部。
  5. 一種半導體製造裝置，係具備： 支撐半導體基板的載台； 導電性之環狀構件，係以圍繞上述半導體基板的方式設置於上述載台之外側；及 對上述環狀構件進行支撐的支撐腳。
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