TWI697997B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI697997B
TWI697997B TW108122319A TW108122319A TWI697997B TW I697997 B TWI697997 B TW I697997B TW 108122319 A TW108122319 A TW 108122319A TW 108122319 A TW108122319 A TW 108122319A TW I697997 B TWI697997 B TW I697997B
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insulating
capacitor
conductor
conductor element
insulating layer
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TW108122319A
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TW202029450A (zh
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王良丞
林孝羲
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台達電子工業股份有限公司
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Abstract

本揭示內容關於一種封裝結構，包含第一電容、系統單晶片及佈線層。第一電容設於基板上。系統單晶片與第一電容被固定於第一絕緣層中。佈線層用以電性連接於第一電容及系統單晶片，且透過第二絕緣層設置於第一絕緣層上。

Description

封裝結構及其製造方法
本揭示內容關於一種封裝結構，特別是具有電容及積體電路的封裝結構。
應用於複雜電子系統的積體電路（Integrated circuit）組件中通常具有數量龐大、相互連接的電路晶片。電路晶片具有微小的尺寸及極高的電路密度。在部份電路中，需要利用大電容來實現某些功能，例如升壓或降壓。 然而，受限於電路晶片的結構，電路晶片內無法設置大的電容器，而這造成了在設計電路上的一個兩難狀況。
本揭示內容的一種實施態樣為一種封裝結構，包含基板、第一電容、系統單晶片、佈線層及第二絕緣層。第一電容設於基板上。系統單晶片與第一電容被固定於第一絕緣層內。佈線層電性連接於第一電容及系統單晶片。第二絕緣層用以將佈線層固定於第一絕緣層上。
本揭示內容的另一種實施態樣為一種封裝結構，包含第一導體元件、絕緣元件及第二導體元件。第一導體元件設於基板上。絕緣元件設於第一導體元件上。第一導體元件、絕緣元件及系統單晶片被固定於第一絕緣層中。第二導體元件設於絕緣元件上，使第一導體元件、絕緣元件及第二導體元件形成第一電容。
本揭示內容的又一種實施態樣為一種封裝結構的製造方法，其先在基板上設置第一電容及系統單晶片。透過第一絕緣材料，固定第一電容及系統單晶片，以形成第一絕緣層。在第一絕緣層上形成佈線層，使第一電容透過佈線層電性連接於系統單晶片。透過第二絕緣材料，將佈線層固定至第一絕緣層上，以在第一絕緣層上形成第二絕緣層。
以下將以圖式揭露本案之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本案。也就是說，在本揭示內容部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
於本文中，當一元件被稱為「連接」或「耦接」時，可指「電性連接」或「電性耦接」。「連接」或「耦接」亦可用以表示二或多個元件間相互搭配操作或互動。此外，雖然本文中使用「第一」、「第二」、…等用語描述不同元件，該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明，否則該用語並非特別指稱或暗示次序或順位，亦非用以限定本案。
請參閱第1圖，為根據本揭示內容之部份實施例之封裝結構示意圖。封裝結構100包含基板130、第一電容200、系統單晶片300及佈線層 121。在部份實施例中，基板130包含第一載板（carrier，為絕緣材質）131及第二載板132。第一載板131及第二載板132分別包含第一傳導層131a以及第二傳導層132a。第一載板131及第二載板132間係相互絕緣設置。第一電容200設置於基板130的第一載板131上。系統單晶片300設置於基板130的第二載板132上。
在部份實施例中，第一導體元件210設於第一載板131上的第一傳導層131a上。系統單晶片300設於第二載板132的第二傳導層132a上。第一載板131及第二載板132的材質可包含不鏽鋼、銅、鋁、金、銀、錫、白金或前述各材質的合金組合。第一載板131 及第一傳導層131a可為相同或相異的材質。同樣地，第二載板 132 及第二傳導層132a 可為相同或相異的材質。
封裝結構100還包含第一絕緣層110及第二絕緣層120。系統單晶片300與第一電容200被固定於第一絕緣層110中。第二絕緣層120用以將佈線層121固定於第一絕緣層110上。在部份實施例中，第一絕緣層110是由第一絕緣材料以射出成型製程形成，以固定第一電容200及系統單晶片300。
佈線層121用以電性連接第一電容200及系統單晶片300。在部份實施例中，佈線層121的材質為金屬，且係透過雷射雕刻（laser drill）及電鍍製程（metal plating process）形成，細節將於後文詳述。
請參閱第1及2A圖所示，「系統單晶片」為一種積體電路（以下簡稱晶片），用以將電腦或電子系統中的多個電子元件整合於晶片中。前述電子元件可包含中央處理器、記憶體、輸入輸出埠以及二次記憶體，且皆設置於單一塊基板上。
在部份實施例中，系統單晶片300包含積體電路，例如邏輯積體電路、數位積體電路、多工積體電路、功率積體電路、記憶體電路、微機電系統（MEMS）、光電器件、傳感器（如：光傳感器或指紋傳感器等）。在部份實施例中，系統單晶片300包括形成在其內的主動元件（圖中未示），例如電晶體、金屬氧化物半導體場效電晶體（MOSFET）、金屬氧化物半導體場效電晶體（MISFET）、接面場效電晶體 （JFET）、絕緣柵雙極電晶體（IGBT）及其組合。
在部份實施例中，系統單晶片300內的電路需要一個大電容。然而，由於大電容的體積與佔用面積都太大，而不易設置在系統單晶片300中。在本實施例中，第一電容200係被設於第一絕緣層110中鄰近系統單晶片300之位置。因此，本揭示內容可以在不影響封裝結構100之整體體積的情況下配置大電容。
請參閱第1及2B圖所示，在部份實施例中，第一電容200包含第一導體元件210、絕緣元件230及第二導體元件220。第一導體元件210及第二導體元件220可為銅柱。第一導體元件210設於第一絕緣層110中。第一導體元件210、絕緣元件230及系統單晶片300皆被固定於第一絕緣層110中。絕緣元件230設於第一導體元件210上，第二導體元件220設於絕緣元件230上。第一導體元件210、絕緣元件230及第二導體元件220用以形成第一電容200。
為了調整第一電容200的電容值，絕緣元件230的材質可與第一絕緣層110或第二絕緣層120的材質不同。舉例而言，絕緣元件230的材質可為陶瓷或雲母，且相異於第一絕緣材料之材質。在其他部份實施例中，第一電容200不包含絕緣元件230。亦即，第一導體元件210與第二導體元件230間保持有預定間隙。第一絕緣材料可填滿第一導體元件210與第二導體元件230間的該預定間隙。換言之，絕緣元件230的材質可與第一絕緣層110的材質相同。
如第1圖所示，在部份實施例中，第一導體元件210與絕緣元件230皆設於第一絕緣層110中。第二導體元件220則設於第二絕緣層120中。第二導體元件220及佈線層121被固定於第二絕緣層120，且第二導體元件220透過佈線層121電性連接至系統單晶片300。然而，請參閱第3圖，在其他部份實施例中，根據不同的製程，第一導體元件210、絕緣元件230及第二導體元件220可皆設於第一絕緣層110中，且被第一絕緣材料所固定。第二導體元件220仍透過佈線層121電性連接於系統單晶片300，細節將於後文詳述。
請參閱第1及2A圖所示，在部份實施例中，系統單晶片300包含晶片基板310、氮化鎵層320及驅動電路330。系統單晶片300的頂側包含至少三個接點，分別為源極S、汲極D以及閘極G。在部份實施例中，系統單晶片300還包含自舉端B及PWM訊號端P，且第一電容200作為驅動電路330的自舉電容。源極S、汲極D及閘極G用以分別接收對應的電壓訊號，以驅動驅動電路330中的電晶體。PWM訊號端P則用以接收PWM訊號（Pulse Width Modulation，脈衝寬度調變），以控制驅動電路330中的開關元件。自舉端B電性連接於驅動電路330中自舉電容（如：第一電容200）的副極端，用以提昇（bootstrap）來自驅動電路330之自舉電容的訊號。
在部份實施例中，系統單晶片300為氮化鎵功率電晶體，驅動電路330為閘極驅動電路。在部份實施例中，閘極驅動電路包含高壓端電晶體、低壓端電晶體及電源泵。舉例而言，閘極驅動電路可為美國專利US9,906,221「DRIVING CIRCUIT OF A POWER CIRCUIT」所討論之電路。
在第一電容200為驅動電路330之自舉電容的實施例中，第一電容200電性連接於閘極端G及自舉端B。第一電容200電性連接於驅動電路330，且能根據自舉訊號而被致能。
如第1圖所示，在部份實施例中，封裝結構100還包含位於第一絕緣層110的第一傳導體111。第一傳導體111可為銅柱。第一傳導體111透過第一傳導層131a設置於第一載板131上，以電性連接於第一電容200的第一側（如：底側）。佈線層121電性連接於第一電容200的第二側（如：頂側）。佈線層121電性連接於系統單晶片200的閘極，第一傳導體111電性連接於第一導體元件210及自舉端B。
封裝結構100還包含第二傳導體112。第二傳導體112可為銅柱。第二傳導體112透過第二傳導層132a設置於第二載板132上，以電性連接於系統單晶片300的第一側（如：底側）。此外，第二傳導體112電性連接於系統單晶片300的源極S，用以接收源極訊號。
第4圖為根據第1圖所示之封裝結構100的製程方法示意圖。第5A～5E圖為封裝結構100之製作過程示意圖。請參閱第1、4及5A～5E圖所示，製造方法包含步驟S401～S406。在步驟S401中，第一電容200的第一導體元件210、系統單晶片300、第一傳導體111、第二傳導體112皆設於基板130上。在部份實施例中，第一電容200的第一導體元件210是和第一傳導層131a形成於第一載板131上。系統單晶片300與第二傳導層132a形成於第二載板132上。
請參閱第5A～5B圖所示，在步驟S402中，絕緣元件230形成於第一導體元件210上。在步驟S403中，第一導體元件210及第一電容200之絕緣元件230透過第一絕緣材料和系統單晶片300固定在一起，以形成第一絕緣層110。在部份實施例中，第一絕緣材料之材質為環氧基樹脂（Epoxy）或BT樹脂（Bismaleimide Triazine Resin）。
在步驟S404中，請參閱第5C～5E圖，透過射出成型製程，在第一絕緣層110上塗布第一加工層（molding layer）120a。接著，透過雷射雕刻與電鍍製程，形成多個第一金屬元件121a。在部份實施例中，如第5C～5D圖所示，在透過射出成型製程形成第一加工層120a後，在第一加工層120a上蝕刻出多個穿孔H，穿孔H的位置對應於絕緣元件230、第一傳導體111、第二傳導體112及系統單晶片300。接著，如第5E圖所示，透過雷射雕刻與電鍍製程，在第一絕緣層110上形成多個第一金屬元件121a。在部份實施例中，該些第一金屬元件121a的其中之一會作為第二導體元件220。第一絕緣層110上的第一加工層120a用以固定第二導體元件220及第一金屬元件121a。
請參閱第5F圖所示，在步驟S405中，以相同於步驟S404之方式，在第一加工層120a上形成第二加工層120b及多個第二金屬元件121b。第一金屬元件121a及第二金屬元件121b用以形成佈線層121，使第一電容200的第一導體元件210透過第一傳導體111及第一金屬元件121a，電性連接於系統單晶片300的自舉端B。第二導體元件220透過第二金屬元件121b電性連接於閘極G。
在步驟S406中，請參閱第1及5G圖所示，在第二加工層120b上形成第三加工層120c及多個第三金屬元件121c。第一加工層120a、第二加工層120b及第三加工層120c用以形成第二絕緣層120。在部份實施例中，第一加工層120a、第二加工層120b及第三加工層120c皆使用第二絕緣材料。第二絕緣材料用以將佈線層121及第二導體元件220固定至第一絕緣層110上以形成第二絕緣層120。在其他部份實施例中，第一加工層120a、第二加工層120b及第三加工層120c亦可使用不同的絕緣材質。
在部份實施例中，在形成第一金屬元件121a及第二金屬元件121b後，佈線層121透過其間隙將形成第二電容C。請參閱第1及5G圖所示，第一金屬元件121a及其中一個第二金屬元件121b的間隙能形成第二電容C。第二電容C形成於第二絕緣層120中，且並聯於於第一電容200，使第一電容200及第二電容C皆作為驅動電路330的自舉電容。
根據本揭示內容之方法，將能把已封裝好的第一電容200設置於基板130上。亦即，第一導體元件210、絕緣元件230及第二導體元件220先封裝為第一電容200，再放置於基板130上。在其他部份實施例中，第一導體元件210及絕緣元件230可先封裝並放置於基板130上，接著，在形成第一絕緣層110後，利用製程形成第二導體元件220或放置第二導體元件220至已經封裝於第一絕緣層110的絕緣元件230及第一導體元件210上。
如第5A～5G圖所示之實施例，第二導體元件220形成於絕緣元件120上，且設於第二絕緣層120中。在部份實施例中，第3圖所示，在形成絕緣元件120於第一導體元件210上後，先在絕緣元件230上設置第二導體元件220。接著，透過第一絕緣材料固定第一導體元件210、第二導體元件220及絕緣元件230。亦即，第一導體元件210、第二導體元件220及絕緣元件230皆設於第一絕緣層110中。
在部份實施例中，在第一導體元件210設置在基板130上後，第一絕緣材料固定第一導體元件210及系統單晶片300。在該實施例中，第一絕緣材料被作為絕緣元件。在形成第一絕緣層110後，再設置第二導體元件220至第一絕緣層110上。第一導體元件210將會與第二導體元件220間保持有預定間隙。據此，第一導體元件210、第二導體元件220，以及介於第一導體元件210及第二導體元件220間的第一絕緣材料將能形成第一電容200。
前述各實施例中的各項元件、運作狀態或技術特徵，係可相互結合，而不以本揭示內容中的文字描述順序或圖式呈現順序為限。
雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本案內容，任何熟習此技藝者，在不脫離本案內容之精神和範圍內，當可作各種更動與潤飾，因此本案內容之保護範圍當視後附之申請專利範圍所界定者為準
100:封裝結構
110:第一絕緣層
111:第一傳導體
112:第二傳導體
120:第二絕緣層
120a:第一加工層
120b:第二加工層
120c:第三加工層
121:佈線層
121a:第一金屬元件
121b:第二金屬元件
130:基板
131:第一載板
131a:第一傳導層
132:第二載板
132a:第二傳導層
200:第一電容
210:第一導體元件
220:第二導體元件
230:絕緣元件
300:系統單晶片
310:晶片基板
320:氮化鎵層
330:驅動電路
G:閘極
D:汲極
S:源極
B:自舉端
P:PWM訊號端
H:穿孔
C:第二電容
S401~S406:步驟
第1圖為根據本揭示內容之部分實施例所繪示的封裝結構的示意圖。 第2A圖為根據本揭示內容之部分實施例所繪示系統單晶片的示意圖。 第2B圖為根據本揭示內容之部分實施例所繪示第一電容的示意圖。 第3圖為根據本揭示內容之部分實施例所繪示的封裝結構的示意圖。 第4圖為根據本揭示內容之部分實施例所繪示的封裝結構之製造方法的流程圖。 第5A～5G圖為根據本揭示內容之部分實施例所繪示的封裝結構的製造過程圖。
100:封裝結構
110:第一絕緣層
111:第一傳導體
112:第二傳導體
120:第二絕緣層
121:佈線層
130:基板
131:第一載板
131a:第一傳導層
132:第二載板
132a:第二傳導層
200:第一電容
210:第一導體元件
220:第二導體元件
230:絕緣元件
300:系統單晶片
C:第二電容

Claims (19)

  1. 一種封裝結構，包含：一基板；一第一電容，設於該基板上；一系統單晶片，與該第一電容被固定於一第一絕緣層內；一佈線層，電性連接於該第一電容及該系統單晶片；一第二絕緣層，用以將該佈線層固定於該第一絕緣層上；以及一第一導體元件，位於該第一絕緣層中，該第一電容透過該第一導體元件及該佈線層電性連接於該系統單晶片。
  2. 如請求項1所述之封裝結構，其中該第一電容包含：一第一導體元件，形成於該第一絕緣層中；一絕緣元件，形成於該第一絕緣層中；以及一第二導體元件，形成於該絕緣元件上。
  3. 如請求項2所述之封裝結構，其中該絕緣元件之材質相異於該第一絕緣層之材質及該第二絕緣層之材質。
  4. 如請求項1所述之封裝結構，其中該第一電容包含：一第一導體元件，位於該第一絕緣層中；以及一第二導體元件，與該第一導體元件間保持有一間隔。
  5. 如請求項1所述之封裝結構，其中該系統單晶片包含一閘極驅動電路，且該第一電容作為該閘極驅動電路的一自舉電容。
  6. 如請求項1所述之封裝結構，其中該系統單晶片包含一氮化鎵功率電晶體。
  7. 如請求項1所述之封裝結構，還包含：一第二電容，形成於該第二絕緣層中，且與該第一電容相並聯。
  8. 一種封裝結構，包含：一第一導體元件，設於一基板上；一絕緣元件，設於該第一導體元件上，其中該第一導體元件、該絕緣元件及一系統單晶片係被固定於一第一絕緣層中；以及一第二導體元件，設於該絕緣元件上，使該第一導體元件、該絕緣元件及該第二導體元件形成一第一電容，其中該第一導體元件、該第二導體元件、該絕緣元件及該系統單晶片被固定於該第一絕緣層中，且該第二導體元件透過一佈線層電性連接於該系統單晶片。
  9. 如請求項8所述之封裝結構，其中該絕緣元件的材質包含陶瓷或雲母。
  10. 如請求項8所述之封裝結構，其中該絕緣元件之材質與該第一絕緣層之材質相同。
  11. 一種封裝結構，包含：一第一導體元件，設於一基板上； 一絕緣元件，設於該第一導體元件上，其中該第一導體元件、該絕緣元件及一系統單晶片係被固定於一第一絕緣層中；以及一第二導體元件，設於該絕緣元件上，使該第一導體元件、該絕緣元件及該第二導體元件形成一第一電容，其中該第二導體元件及一佈線層被固定於一第二絕緣層中，且該第二導體元件透過該佈線層電性連接於該系統單晶片。
  12. 如請求項11所述之封裝結構，其中該絕緣元件的材質包含陶瓷或雲母。
  13. 如請求項11所述之封裝結構，其中該絕緣元件之材質與該第一絕緣層之材質相同。
  14. 一種封裝結構的製造方法，包含：在一基板上設置一第一電容及一系統單晶片；透過一第一絕緣材料，固定該第一電容及該系統單晶片，以形成一第一絕緣層；在該第一絕緣層上形成一佈線層，使該第一電容透過該佈線層電性連接於該系統單晶片；透過一第二絕緣材料，將該佈線層固定至該第一絕緣層上，以在該第一絕緣層上形成一第二絕緣層；在該基板上設置一第一導體元件；在該第一導體元件上設置一絕緣元件；在該絕緣元件上設置一第二導體元件；以及 透過該第一絕緣材料，固定該第一導體元件、該第二導體元件及該絕緣元件。
  15. 如請求項14所述之製造方法，還包含：在該基板上形成一第一導體元件；以及在形成該第一絕緣層後，在該第一絕緣層上設置一第二導體元件，其中該第二導體元件與該第一導體元件之間保持有一間隔。
  16. 如請求項14所述之製造方法，還包含：在該基板上設置一第一導體元件；在該第一導體元件上設置一絕緣元件；在形成該第一絕緣層後，在該第一絕緣層上設置一第二導體元件；以及透過該第二絕緣材料，固定該佈線層與該第二導體元件。
  17. 如請求項14所述之製造方法，還包含：在該基板上設置一第一傳導體，其中該第一傳導體電性連接於該第一電容的一第一側，該佈線層電性連接於該第一電容的一第二側，且該佈線層及該第一傳導體分別電性連接於該系統單晶片的一第一端及一第二端。
  18. 如請求項14所述之製造方法，其中該系統單晶片包含一閘極驅動電路，且該第一電容作為該閘極驅動電路的一自舉電容。
  19. 如請求項14所述之製造方法，還包含：利用該佈線層中的間隙形成一第二電容，其中該第二電容並聯於該第一電容。
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US20230326918A1 (en) * 2022-04-12 2023-10-12 Ancora Semiconductors Inc. Package structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201729388A (zh) * 2015-12-26 2017-08-16 英特爾公司 晶片上之整合式被動裝置
TW201841270A (zh) * 2017-01-26 2018-11-16 台灣積體電路製造股份有限公司 封裝及其製造方法
TW201901864A (zh) * 2017-05-19 2019-01-01 南韓商三星電機股份有限公司 複合天線基板以及半導體封裝模組
TWI648834B (zh) * 2017-07-07 2019-01-21 欣興電子股份有限公司 半導體封裝結構及其製作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6911371B2 (en) * 1997-12-19 2005-06-28 Micron Technology, Inc. Capacitor forming methods with barrier layers to threshold voltage shift inducing material
US6255186B1 (en) * 1998-05-21 2001-07-03 Micron Technology, Inc. Methods of forming integrated circuitry and capacitors having a capacitor electrode having a base and a pair of walls projecting upwardly therefrom
US6611419B1 (en) 2000-07-31 2003-08-26 Intel Corporation Electronic assembly comprising substrate with embedded capacitors
US6734079B2 (en) * 2002-06-13 2004-05-11 Taiwan Semiconductor Manufacturing Co., Ltd Microelectronic fabrication having sidewall passivated microelectronic capacitor structure fabricated therein
US7106105B2 (en) 2004-07-21 2006-09-12 Fairchild Semiconductor Corporation High voltage integrated circuit driver with a high voltage PMOS bootstrap diode emulator
US8470680B2 (en) 2008-07-28 2013-06-25 Kemet Electronics Corporation Substrate with embedded patterned capacitance
US8704454B2 (en) 2009-10-13 2014-04-22 National Semiconductor Corporation Integrated driver system architecture for light emitting diodes (LEDs)
US8896096B2 (en) * 2012-07-19 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Process-compatible decoupling capacitor and method for making the same
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9420693B2 (en) 2014-09-18 2016-08-16 Intel Corporation Integration of embedded thin film capacitors in package substrates
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
CN205140976U (zh) 2015-09-30 2016-04-06 日月光半导体(上海)有限公司 封装基板
US9704796B1 (en) 2016-02-11 2017-07-11 Qualcomm Incorporated Integrated device comprising a capacitor that includes multiple pins and at least one pin that traverses a plate of the capacitor
US9681536B1 (en) 2016-08-28 2017-06-13 Unimicron Technology Corp. Package substrate and method for fabricating the same
US9906221B1 (en) 2016-12-30 2018-02-27 Delta Electronics, Inc. Driving circuit of a power circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201729388A (zh) * 2015-12-26 2017-08-16 英特爾公司 晶片上之整合式被動裝置
TW201841270A (zh) * 2017-01-26 2018-11-16 台灣積體電路製造股份有限公司 封裝及其製造方法
TW201901864A (zh) * 2017-05-19 2019-01-01 南韓商三星電機股份有限公司 複合天線基板以及半導體封裝模組
TWI648834B (zh) * 2017-07-07 2019-01-21 欣興電子股份有限公司 半導體封裝結構及其製作方法

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