TWI695405B - Methods of inspecting samples - Google Patents

Abstract

A scanning electron microscope incorporates a multi-pixel electron detector. The multi-pixel detector may detect back-scattered and/or secondary electrons. The multi-pixel detector may incorporate analog-to-digital converters and other circuits. The multi-pixel electron detector may be capable of approximately determining the energy of incident electrons and/or may contain circuits for processing or analyzing the electron signals. The multi-pixel electron detector is suitable for high-speed operation such as at a speed of about 100 MHz or higher. The scanning electron microscope may be used for reviewing, inspecting or measuring a sample such as an unpatterned semiconductor wafer, a patterned semiconductor wafer, a reticle or a photomask. A method of reviewing or inspecting a sample is also described.

Description

How to check the sample

This application is about a scanning electron microscope, an electron and X-ray detector suitable for use in a scanning electron microscope, and a system and method for examining and inspecting samples. These electron microscopes, detectors, systems and methods are particularly suitable for use in inspection and inspection systems, which include such electronics for inspection and/or inspection of photomasks, main photomasks and semiconductor wafers Microscope, detector, system and method.

The integrated circuit industry needs inspection tools with higher and higher sensitivity to detect increasingly smaller defects and particles whose size can be tens of nanometers (nm) or smaller. These inspection tools must be operated at high speed to inspect the reticle, main reticle or wafer within a short period of time (e.g. 1 hour or less) for inspection during production or for R&D or fault tracing to most hours One of the regions is mostly or even 100%. For quick inspection, inspection tools use pixels or light spot sizes larger than the size of the defect or particle of interest, and even detect a small change in the signal caused by a defect or particle. Most commonly, inspection tools (which operate using UV light) are used in production to perform high-speed inspections. R&D inspection can be performed using UV light or using electronics. Once a defect or particle has been discovered through high-speed inspection, it is usually necessary to generate a higher resolution image and/or perform material analysis to determine the origin or type of the particle or defect. This procedure is often called a review. A scanning electron microscope (SEM) is usually used to perform the review. A review SEM, which is used in semiconductor manufacturing processes, is usually required to review thousands of potential defects or particles every day, so it can be used for every target review for most seconds. The review SEM for the semiconductor and related industries is manufactured by KLA-Tencor (e.g. eDR-7110), manufactured by Applied Materials (e.g. SEMVision G6), and manufactured by other companies. Most commonly, a review SEM detects secondary electrons emitted from the sample to form an image. An exemplary secondary electron detector used in a review SEM is described in US Patent No. 7,141,791, which is named "Apparatus and method for e-beam dark-field imaging" by Masnaghetti et al. This exemplary secondary electron detector includes an electro-optic device for collecting secondary electrons and directing the secondary electrons to a scintillator. The electrons are accelerated toward the scintillator, so that each electron irradiating the scintillator causes multiple photons to be emitted. The part of the photons is captured by a light pipe and guided to one or more photomultiplier tubes. One disadvantage of this method is that the detector is relatively slow. The light emission from the scintillator has a decay time constant of tens of nanoseconds. In addition, the scintillator has multiple time constants. The initial response may have a time constant of tens of nanoseconds, but light emission will continue at a lower level with a much longer time constant. The photomultiplier tube also has a response with multiple time constants. The photocathode that emits photoelectrons has one or more time constants. These electrons take a lot of time to travel from one multiplier electrode to another multiplier electrode and eventually to the anode, which produces an additional time constant. The electron travel time can be reduced by reducing the number of multiplier electrodes, but this reduces the gain of the photomultiplier tube and therefore is not a trade-off because it reduces the sensitivity of the SEM to improve the rate. SEMs designed for review can include electronic micro-probe (X-ray) analysis for material identification. In order for an SEM to have an image resolution of several nanometers or better to provide high-quality images of nano-level defects and particles, the inspected sample is placed close to the final objective lens, so that the sample is immersed in the magnetic field of the lens, so Minimize imaging aberrations. Placing the sample close to the objective prevents the large detector from being placed close to the sample. In particular, X-ray detectors used for microprobing or similar analysis can only collect X-rays in a small solid angle to make these systems very slow. Each target requires tens of seconds or tens of minutes of data acquisition time to capture enough X-rays to determine the target's material composition. A review of the final objective of the SEM also limits the position where the secondary electron detector and backscattered electron detector can be placed and the collection voltage that can be applied to these detectors. A small potential difference (such as less than about 2 kV) between an electron detector and the sample reduces the efficiency and sensitivity of an electron detector to collect and detect low-energy electrons from the sample. Therefore, it is necessary to overcome some or all of the above shortcomings with a high-speed high-resolution review SEM. In particular, a high-speed high-resolution automated SEM with the ability to quickly identify at least some commonly used materials is needed. It may further be expected that the ability to quickly identify materials and/or provide improved image contrast is included in a high-speed inspection SEM.

The present invention is directed to an SEM that utilizes one or more solid-state electron detectors to achieve backscatter or two from the same emission by converting incident electrons into measurable charges completely within a single integrated semiconductor structure High-speed detection of secondary electronics. Specifically, each solid-state electron detector includes a sensor that uses a p-type electron sensitive layer to generate multiple electrons in response to each incident (detected) electron, and uses an n-type buried channel layer To transfer at least part of the generated electrons to an n+ floating diffusion region, and use an electric charge (voltage) collected on the floating diffusion region to control an amplifier to generate an output signal, wherein the p-type electron sensitive layer , The n-type buried channel layer, the n+ floating diffusion region and the amplifier include respective doped regions of the single integrated semiconductor (e.g. epitaxial silicon) structure. In this way, the incident electrons are converted into measurable charges that are completely within an integrated semiconductor structure, which is substantially faster than the conventional photon-based scintillator method, whereby the present invention provides an SEM that is substantially more efficient than scintillation-based The conventional processing speed of the SEM is to achieve a high processing speed (for example, 100 MHz or higher). These solid-state electron detectors also have a smaller size and produce a smaller potential difference between the detector and the sample, which facilitates the generation of an SEM including a backscattered electron detector that is placed close to the same An electron source operating at the high operating rate of the secondary electron detector (eg, between the final (immersion) objective and the sample, or above the final objective), whereby both the secondary electron signal and the backscattered electron signal can be Used in combination to provide higher resolution information than can be obtained from any signal itself with respect to the surface configuration of the sample. Furthermore, by using known semiconductor processing techniques to fabricate electronic sensors on a single semiconductor structure, these solid-state electronic detectors can have a lower total cost and need than conventional sensors based on scintillators A lower operating voltage than this, thereby facilitating the production of SEMs, which have cheaper production costs and exhibit substantially higher efficiency and therefore cheaper operation than conventional scintillator-based SEM systems cost. The present invention describes an exemplary inspection and review SEM using one or more solid-state electronic detectors of the type mentioned above. The SEM includes an electron source, an electron optical system (electro-optical device), at least a solid-state electronic detector, and a computer. The electron source generates an original electron beam directed toward one of the samples. The electron optical device includes a lens and a deflector, which are configured to reduce the original electron beam, focus the original electron beam, and cause the original electron beam to scan the entire area of the sample to be inspected. When the original electron beam irradiates the sample, the sample absorbs many electrons from the original electron beam, but scatters some electrons (backscattered electrons). This absorbed energy causes secondary electrons to be emitted from the sample along with some X-rays and Auger electrons. Position a backscattered electron (first) electron detector close to the sample, thereby converting an analog output signal having a voltage level proportional to the number and energy of the detected backscattered electrons to a corresponding digital value And the analog output signals are transmitted to the computer as corresponding (first) image data signals. The secondary electrons are detected by an optional (second) solid-state electron detector, the sensor of the (second) solid-state electron detector is proportional to the number and energy of the detected secondary electrons Analog output signals, convert the analog output signals into corresponding digital values and transmit the analog output signals to the computer as corresponding (second) image data signals. The computer receives the first image data signal and the second image data signal from the first solid-state detector and the second solid-state detector, and then processes the received image data signals to construct the original electronic An image of the area of the sample on which the beam is scanned. In a preferred embodiment, both the secondary electron detector and the backscattered electron detector include solid-state detectors. In a preferred embodiment, the backscattered electron detector has a pure boron coating on the surface that detects electrons (ie, the forward surface facing the sample or other electron source). In another embodiment, both the backscattered electron detector and the secondary electron detector include a pure boron coating. The present invention describes one exemplary method of checking or reviewing a sample. The method includes: generating a main clock signal; generating a deflection scan synchronized with the main clock, the deflection scan causing an original electron beam to scan a region of the sample; and generating a first synchronized with the main clock The pixel clock is used to collect and digitize backscattered electronic signals. The method further includes: roughly determining the energy of each backscattered electron from the charge generated in each pixel. The number and energy of the backscattered electrons collected can be used to determine whether a defect or defect type exists, classify a defect type, or determine a material type or material type at a location in the scanning area of the sample. In a preferred embodiment of the method, the first pixel clock or a second pixel clock synchronized with the main clock is used to collect and digitize secondary electrons. The secondary electrons can be used to form an image of the scanning area of the sample. The image can be formed by the combined backscattered electronic signal and secondary electronic signal. The secondary electron signals can be used in combination with the backscattered electron signals to determine whether a defect or defect type exists, classify a defect type, or determine a material type at a location in the scanning area of the sample or Material category. These combined signals may also provide more information than can be obtained from any signal itself regarding the surface configuration of the sample. According to another embodiment of the invention, an electronic detector includes an array of pixels and a plurality of analog-to-digital converters, wherein each pixel operates in the manner described above to generate an analog output signal, and various types of analog-to-digital converters The digital converter is connected to convert the analog output signal from the only associated pixel to facilitate high-speed and high-resolution detection/readout operations. The pixel array includes a plurality of pixels arranged in columns and rows (for example, 16×16, 32×32, 64×64 or more), thereby facilitating the detection of incident electrons on a large area. Similar to the general electronic sensor mentioned above, each pixel includes a p-type electron sensitive area, an n-type buried channel layer, a floating diffusion area, and an amplifier circuit, which is configured to generate An analog output signal whose level roughly corresponds to the energy of an incident electron or the number of electrons that enter the pixel (ie, a backscatter or secondary electron). By using multiple analog-to-digital converters (which are each configured to process the output signal from one pixel), the present invention provides a multi-pixel (ie, 4×4 or larger) electronic detector, which implements Operation rates that are substantially higher than those that can be achieved using conventional detector configurations (eg, 100 MHz or higher sampling rate for each pixel). Furthermore, because the output signals from multiple pixels arranged in a matrix (array) are simultaneously converted, the multi-pixel electronic detector of the present invention facilitates the measurement of the received signal during a given detection/readout operation The energy of more than one incident electron, and also facilitates the determination of the path of incident electrons by the position of the detection pixels in the matrix. In one embodiment, the pixels are fabricated on a semiconductor structure separate from the analog-to-digital converters, and the output signal is transmitted from each pixel to its associated analog-to-digital conversion by a corresponding solder ball Device. In a preferred embodiment, the pixels are fabricated on a layer of slightly p-doped epitaxial silicon as part of a sensor circuit, and the analog-to-digital converter and other digital circuits are fabricated together in a first Two semiconductor (for example, silicon) substrates are used as part of a signal processing circuit (for example, as part of an ASIC (dedicated integrated circuit)). Preferably, the thickness of the epitaxial silicon used to form the pixels is between about 40 μm and about 100 μm to allow electrons to drift from the electron sensitive region to the n-type buried channel layer Retention is limited to less than 10 ns while providing good mechanical strength. Depending on the mechanical support provided by the substrate to which silicon is attached, silicon thinner than 40 μm (such as between about 10 μm and about 40 μm) can be accepted. In one embodiment, a pure boron coating is disposed on the electron sensitive surface of the epitaxial silicon. In one embodiment, in addition to the analog-to-digital converter array, the signal processing circuit also includes a processing circuit that is configured, for example, based on digitization received from an associated pixel of one of the sensor circuits The output signal (image data) is used to calculate the approximate energy of an incident electron. In another embodiment, the signal processing circuit also includes a high-speed data transmission circuit for transmitting an image data signal to an external processing system (such as a computer). After manufacturing the sensor circuit and the signal processing circuit, the sensor circuit and the signal processing circuit are connected in a stacked configuration to solder balls connected between each pixel and an associated analog-to-digital converter. In particular, the output signal transmitted from each pixel is connected to a first pad disposed on a surface of the sensor circuit, and from the first pad is connected to the placement by an associated solder ball/solder bump A second pad on the signal processing circuit transmits the output signal from the second pad to the input terminal of an associated analog-to-digital converter. This connection can also provide mechanical support for the sensor circuit. Various control and power signals utilized by the pixels can be transmitted from a control circuit by sharing metal interconnections (signal lines). The control circuit can then be connected to the signal processing circuit by solder bumps or wiring or Another substrate. In a preferred embodiment, the floating diffusion area of each pixel is located in the central area of the pixel, and the lateral size of each pixel is limited to promote sufficient time to collect electrons from the buried type in high-speed data collection The channel layer is transferred to the floating diffusion. By positioning the floating diffusion in the center of each pixel, the path required for any electron to travel through the buried channel layer to the floating diffusion is equal to the maximum lateral (eg, diagonal) size of a pixel half. Limiting the nominal lateral size of each pixel to about 250 μm or less results in an operating rate of up to 100 MHz. In one embodiment, a separate (third) substrate is electrically and/or mechanically connected to one or more of the sensor circuit and the signal processing circuit. The separate substrate may include silicon or a ceramic material, and may include an integrated circuit including high-speed data transfer for processing analog or digital signals from each pixel and for providing image data to an external computer or other system Circuit. The processing functions performed by the integrated circuit may include limiting, summing, gridding, and/or counting data from individual pixels. The integrated circuit preferably includes a high-speed (such as approximately 10 billion bits per second) serial transmitter for transmitting digitized data to a computer. The integrated circuit may include a serial receiver for receiving commands from the computer. The serial receiver can operate at a lower rate than the serial transmitter. The present invention is further directed to a novel electronic sensor pixel, in which a resistive gate and one or more additional gates are used to drive electrons toward the floating diffusion located in the center. The resistive gate is implemented by an amorphous silicon or polysilicon structure disposed on the surface of most pixels. A potential difference applied between an outer periphery and an inner periphery of the resistor gate generates electrons driving the buried channel toward a floating diffusion region (which is preferably located near the center of the pixel to accelerate charge transfer) An electric field. Various additional gates are fabricated between the resistive gate on the front surface of the pixel and the floating diffusion region to guide and control the transfer of charge from the buried channel to the floating diffusion region and allow the floating diffusion region to be reset. The amplifier of the pixel is fabricated in a p-well region on the front surface of the pixel to buffer the signal collected in the floating diffusion region.

[ Related application ] This application claims the priority of US Provisional Patent Application 62/043,410, entitled "Scanning Electron Microscope And Methods Of Inspecting", which was filed on August 29, 2014 and incorporated herein by reference. The invention relates to an improved solution of a sensor used in a semiconductor inspection and inspection system. The following description is presented to enable a person of ordinary skill to make and use the invention, as provided in the context of a specific application and its requirements. As used herein, directional terms (such as "top", "bottom", "above", "below", "up", "up", "down", "below" and "below" "Downward") is intended to provide a relative position (for description) and is not intended to specify an absolute frame of reference. In addition, the phrase "integrated semiconductor structure" is used herein to describe the formation of a single process (such as Czochralski crystal growth, sputtering deposition, plasma vapor deposition or chemical vapor deposition) A continuous semiconductor material (e.g. silicon) substrate that is distinguished from two separate semiconductor structures (e.g. two "wafers" from the same silicon wafer) that have been connected by adhesives, solder or other interconnects. Those skilled in the art will understand the various modifications of the preferred embodiment and can apply the general principles defined herein to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described, but should be given the broadest scope consistent with the principles and novel features disclosed herein. FIG. 1 shows an exemplary scanning electron microscope (SEM) 100, also referred to as an inspection or inspection system, which is configured to inspect or inspect a sample 131, such as a semiconductor wafer, a main mask or a mask . The SEM 100 generally includes: an electron gun (source) 140; an electronic optical device, which includes an upper row 141 and a lower row 142; a platform 130, which is used to support and position a sample 131; and a system computer 160. In one embodiment, the electron gun 140 includes a cathode 101, such as a thermal field emission or Schottky cathode, a single crystal tungsten cathode, or a LaB₆ Cathode; and extraction and focusing electrode 102. The electron gun 140 may further include a magnetic lens (not shown). The electron gun 140 generates a primary electron beam 150 having a desired electron beam energy and electron beam current. The upper row 141 of the electro-optic device includes one or more condenser lenses 107, which reduce the original electron beam to produce a small spot on the sample 131. In general, in order to generate high-resolution images for sample review, the spot size is preferably about 1 nanometer or several nanometers. A sample inspection can use a larger spot size to scan the sample 131 faster. When the spot size is about 100 nm or more, a single condenser lens 107 may be sufficient, but a spot size of tens of nanometers or less usually requires two or more condenser lenses. The condenser lens 107 may include a magnetic lens, an electrostatic lens, or both. The upper row 141 may also include one or more deflectors 105, which allow the original electron beam to scan the entire area of the sample 131. The deflector 105 can be placed on both sides of the condenser lens 107 (as shown in the figure), or the deflector 105 can be placed in the condenser lens 107 (not shown in the figure), or the deflector 105 can be placed on the condenser After the optical lens 107. The deflector 105 may include an electrostatic deflector or a combination of a magnetic deflector and an electrostatic deflector. In an embodiment, there may be no deflector in the uplink 141. All deflectors may be included in the downstream 142 instead. The lower row 142 includes a final (immersion) lens 110 for focusing the original electron beam to a small spot on the sample 131. The final lens 110 may include a magnetic lens (as shown in the figure) or a combination of a magnetic lens and an electrostatic lens (not shown in the figure). To achieve a small spot size at the sample 131, the final lens 110 is placed close to the sample 131 so that the sample is immersed in the magnetic field of the lens. This can reduce the aberration of the electron spot on the sample 131. Downstream 142 also includes deflector 109, which works with deflector 105 (if present) to cause the original electron beam to scan the entire area of sample 131. The sample 131 is placed on a platform 130 to facilitate moving different areas of the sample 131 under the electron column. The platform 130 may include an XY platform or an R-θ platform, and in one embodiment, is configured to support and locate many sample types (such as an unpatterned semiconductor wafer, Once patterned semiconductor wafer, a main mask or a mask). In a preferred embodiment, the platform 130 can adjust the height of the sample 131 during the examination to maintain focus. In other embodiments, the final lens 110 may be adjusted to maintain focus. In some embodiments, a focus or height sensor (not shown) may be mounted on the final lens 110 or close to the final lens 110 to provide a signal to adjust the height of the sample 131 or adjust the focus of the final lens 110. In an embodiment, the focus sensor or height sensor may be an optical sensor. When the original electron beam 150 scans the entire area of the sample 131 by the electron optical device, secondary electrons and backscattered electrons are emitted from the area. The secondary electrons can be collected and accelerated by the electrode 120 and guided to the secondary electron detector 121. An electronic optical device for collecting, accelerating, and/or focusing secondary electrons is described in US Patent No. 7,141,791, entitled "Apparatus and method for e-beam dark-field imaging" by Masnaghetti et al. This patent is incorporated herein by reference. As described in the '791 patent, the electron optics for the secondary electron detector may include descanning optics for at least partially counteracting the effect of the deflector 109 on the trajectory of the secondary electrons. In some embodiments of the present invention, descanning electron optics is unnecessary and can be omitted, because descanning can be substantially achieved by an ASIC (as described herein) included in the secondary electron detector. The secondary electron detector 121 is preferably a solid-state electron detector (such as one of the solid-state electron detectors described herein) and is configured to generate a Image data signal ID2, wherein the image data signal ID2 is transferred to the computer 160 and the image data signal ID2 is used to generate an image of the associated scan sample area, thereby facilitating the visual inspection of a defect D. U.S. Patent No. 7,838,833 for Lent et al. "Apparatus and method for e-beam dark imaging with perspective control" and James et al. "Apparatus and method for obtaining topographical dark-field images in a scanning electron microscope" U.S. Patent No. 7,714,287 describes other electron optical devices and detector configurations and methods for detecting and analyzing secondary electrons that can be used in combination with the systems and methods described herein. These two patents are incorporated herein by reference. The backscattered electrons can be detected by a backscattered electron detector (such as the backscattered electron detectors shown at 122a and 122b), which is one of the solid-state electron detectors described herein Implemented and configured to generate an image data signal ID1 based on the detected backscattered electrons, wherein the data signal ID1 is transferred to the computer 160 and the data signal ID1 is also used to generate an image of the associated scanned sample area. Preferably, the backscattered electron detector is placed as close as possible to the sample 131, such as at position 122a (ie, between the final lens 110 and the sample 131). However, the gap between the sample 131 and the final lens 110 may be small (such as about 2 mm or less), and (for example) a focal point or height sensor requires a gap, so it is practically impossible to detect the backscattered electrons The detector is placed at position 122a. Alternatively, the backscattered electron detector may be placed at a location such as 122b, on the other side of the pole piece of the final lens 110 relative to the sample 131. It should be noted that the backscattered electron detector must never block the original electron beam 150. The backscattered electron detector may have a hole in the middle or may include multiple detectors (such as two, three, or four separate detectors) that are placed in the path of the original electron beam 150 Around so as not to block the path, while efficiently capturing backscattered electrons. The landing energy of the original electron beam 150 on the sample 131 depends on the potential difference between the cathode 101 and the sample 131. In one embodiment, the platform 130 and the sample 131 can be kept close to the ground potential, and the landing energy can be adjusted by changing the potential of the cathode 101. In another embodiment, the landing energy on the sample 131 can be adjusted by changing the potential of the platform 130 and the sample 131 relative to ground. In either embodiment, the final lens 110 and the backscatter electron detectors 122a and/or 122b must all have potentials that are close to each other and close to the potential of the sample 131 and platform 130 (such as about 1000 less than the sample 131 and platform 130 V) To avoid the arc effect on the sample 131. Due to this small potential difference, the backscattered electrons from the sample 131 will only be accelerated by a small amount or not at all as they travel from the sample to the backscattered electron detectors 122a and/or 122b. For some semiconductor samples, the landing energy on sample 131 can be quite low (such as between about 500 eV and about 2 keV) to avoid damage to these samples, so when backscattered electrons land on backscattered electron detection On the devices 122a and/or 122b, the energy of the backscattered electrons will be quite low. Therefore, for the sensitivity of the SEM, it is important that the backscattered electron detectors 122a and 122b generate many electrons from a single low-energy backscattered electron (such as an electron with an energy of about 2 keV or less) -Electric hole pair. Conventional silicon detectors inevitably have a thin oxide (such as a native oxide) coating on the surface of silicon (which prevents most electrons with energies below about 2 keV from reaching silicon), or alternatively , With a thin metal (such as Al) coating on the surface (which scatters and absorbs a significant portion of incident low-energy electrons). In a preferred embodiment, the solid-state electronic detector described herein has a pinhole-free pure boron coating on its surface. A pinhole-free pure boron coating prevents oxidation of silicon and allows efficient detection of low energy electrons (which include electrons with energy less than 1 keV). U.S. Published Patent Application 2013/0264481, entitled "Back-illuminated Sensor With Boron Layer" and applied by Chern et al. on March 10, 2013, is used to manufacture silicon detection with pinhole-free pure boron coating The method of the detector and the design of these detectors. This patent application is incorporated herein by reference. The bubble located in the lower left part of FIG. 1 illustrates a simplified solid-state sensor 123 which is used by one or more of the electron detectors 121, 122a, and 122b to scatter incident back or secondary electrons e_INCIDENT It is converted into a measurable charge completely within a single integrated semiconductor (e.g., epitaxial silicon) structure 124. The sensor 123 includes: a p-type electron sensitive layer 127 configured to respond to each incident electron e entering through a front side surface 127-F_INCIDENT While generating multiple electrons e₁₂₇ ; An n-type buried channel layer 125, which is configured to e₁₂₅ (It means the generated electron e₁₂₅ At least part of it) is transferred to an n+ floating diffusion FD; an amplifier 129 according to a charge (voltage) V collected on the floating diffusion FD_FD An output signal OS is generated. The buried channel layer 125 is disposed on the top surface 127-B of one of the electron sensitive layers 127 to promote electrons generated by the electron sensitive layer 127₁₂₇ Efficient collection, and the floating diffusion FD is disposed in the buried channel layer 125 to facilitate the reception of electrons e₁₂₅ , So that the measured charge (voltage) V_FD And electrons captured by the floating diffusion FD_FD The number is proportional. According to one aspect of the invention, the p-type electron sensitive layer 127, the n-type buried channel layer 125, the n+ floating diffusion region FD and the amplifier 129 are co-manufactured on the integrated semiconductor structure 124 by diffusion dopants, thereby The entire incident electron-to-readout conversion occurs completely within the semiconductor structure 124. A pure boron layer 128 is formed on the bottom surface 127-F of the electron sensitive layer 127, so that the incident electrons e_INCIDENT It passes through the pure boron layer 128 before entering the electron sensitive layer 127. As discussed in detail below, in addition to the sensor 123, each solid-state electronic detector also includes at least one analog-to-digital converter 126, which converts the output signal OS into a digital image data signal IDx (ie, backscatter The signal ID1 in the case of the electronic detector 122a or 122b or the signal ID2 in the case of the secondary electron detector 121 is transmitted to a digital form of the computer 160. For simplicity, the various circuits and systems of SEM 100 are described above in a simplified form, and it should be understood that these circuits and systems include additional features and perform additional functions. For example, although the backscattered electron detectors 122a/122b and secondary electron detector 121 of the SEM 100 are briefly described as including simplified sensors 123 to introduce certain key features of the present invention, it should be understood that The multi-pixel electron detector described below is preferably used to implement the backscattered electron detectors 122a/122b and the secondary electron detector 121. Furthermore, in addition to generating an image of the scanned sample area, the computer 160 may be configured to perform additional functions, such as using the method described below to determine the existence of a defect based on the incident electron energy value indicated by the image data signal and/or Or the type of defect. FIG. 2 illustrates an exemplary method 200 of inspecting or reviewing a sample (such as a semiconductor wafer, a main reticle, or a reticle). The method shown in Figure 2 can be repeated for each area on the sample to be inspected or reviewed. In a review SEM, the area to be reviewed has been previously identified by an optical or SEM inspection as likely to contain a defect or particle. For each area on the sample to be inspected or reviewed, the exemplary method 200 begins at step 201. In step 202, a main clock signal for controlling the timing of the scanning of the original electron beam and the acquisition of image data is generated. In step 204, an electron beam deflection scanning pattern is generated. This electron beam deflection scan pattern generates a voltage and/or current that is transferred to an electron beam deflector (such as the deflectors shown at 105 and 109 in FIG. 1). The pattern may be a raster scan, a serpentine pattern, a square spiral or other patterns covering the area of the sample. A scan pattern may also contain, for example, delayed and dummy scans, where no data is collected to control the charging of the sample surface. In step 206, a first pixel clock signal is generated. The first pixel clock signal is synchronized with the main clock signal. The first pixel clock signal may have the same frequency as the main clock signal, a frequency that is a multiple of the main clock signal, and a frequency that is a fraction of the main clock signal (ie, the frequency of the main clock signal divided by one Integer), or a frequency that is a rational multiple of the frequency of the main clock signal. In step 208, at each period of the first pixel clock signal, the signal collected in the scattered electron detector is read out and digitized back. In step 210, a second pixel clock signal synchronized with the main clock signal is generated. The second pixel clock signal may have the same frequency as the main clock signal, a frequency that is a multiple of the main clock signal, and a frequency that is a fraction of the main clock signal (ie, the main clock signal frequency divided by one Integer), or a frequency that is a rational multiple of the frequency of the main clock signal. The second pixel clock signal may have the same frequency as the first pixel clock signal. In one embodiment, the first pixel clock signal is used for both the first pixel clock signal and the second pixel clock signal, and no separate second pixel clock signal is generated. In step 212, at each cycle of the second pixel clock signal (or the first pixel clock signal (if the second pixel clock signal is not used)), the readout and digitization in the secondary electron detector Collected signals. In step 214, the digitized backscatter and secondary electron signals are used to determine the presence of one or more defects in the scan area. A defect may include the presence of material that should not be there (such as a particle), lack of material that should be there (such as an over-etching condition may occur), or a deformed pattern. In an optional step 216, the defect type or the material type of the defect can be determined according to the defects found in step 214. For example, high atomic number elements generally scatter a fraction of the incident electrons that are larger than low atomic number elements. The backscattered electron signal can be used to infer the presence of a high atomic number element (such as a metal). In step 216, when reviewing an area that has previously been inspected, the previous inspection data (optical and/or electron beam) can be used in combination with the digitized backscatter and secondary electron signals to better determine the defect or material type. In one embodiment, steps 214 and 216 may be combined into a single step that simultaneously determines the existence and type of a defect. Repeat method 200 from the beginning for each area on the sample that can be examined or inspected. FIG. 3a illustrates an exemplary simplified multi-pixel electronic detector 300 used in a review SEM or other SEM system (such as SEM 100 shown in FIG. 1). The electronic detector 300 generally includes a sensor circuit 310 and a signal processing circuit 320. In the preferred embodiment shown in FIG. 3a, the sensor circuit 310 is fabricated on a silicon structure (wafer) 311, and the signal processing circuit 320 is fabricated on a separate silicon structure for reasons that will be understood below. (Wafer) 321. In an alternative embodiment (not shown in the figure), both the sensor circuit and the signal processing circuit are fabricated on the same silicon wafer. Referring to the lower part of FIG. 3a, the sensor 310 includes 16 pixels 315-11 to 315-44 arranged in a four column×four row (4×4) array. For the purpose of description, in FIG. 3a, the "rows" of pixels are aligned in an arbitrary designated X-axis direction, whereby pixels 315-11 to 315-14 form a first column, and pixels 315-21 to 315-24 form In a second column, pixels 315-31 to 315-34 form a third column, and pixels 315-41 to 315-44 form a fourth column. Similarly, the "rows" of pixels are aligned in the Y-axis direction shown in FIG. 3a, whereby pixels 315-11 to 315-41 form a first row and pixels 315-12 to 315-42 form a first row In two rows, pixels 315-13 to 315-43 form a third row, and pixels 315-14 to 315-44 form a fourth row. In practical applications, it is expected that the sensor circuit includes an array of 16×16, 32×32, 64×64 or more pixels, where the pixels of these larger arrays include a simplified 4×4 array similar to that described below Characteristics of characteristics. Furthermore, the number of pixels in each column/row of the array need not be a power of 2, and the number of pixels in each column need not be equal to the number of pixels in each row. In one embodiment (for example, in the case of the backscattered electron detector 122a or 122b shown in FIG. 1), the sensor 310 includes a hole (not shown) in the middle of the sensor to allow The original electron beam passes through the sensor. Although the pixels 315-11 to 315-44 are depicted as having a square shape, the pixels may also be rectangular or hexagonal. According to one aspect of the present invention, each pixel of the sensor circuit 310 includes an electronic sensitive structure similar to the electronic sensitive structure, the buried channel structure, the floating diffusion structure, and the amplifier circuit structure described above with reference to FIG. 1, Buried channel structure, floating diffusion structure and amplifier circuit structure. For example, referring to pixels 315-41 in FIG. 3a, each pixel generally includes a p-type electron sensitive region 312A, an n-type buried channel layer 316, a floating diffusion FD, and an amplifier 317. The p-type electron sensitive region 312A is formed by a portion of the epitaxial layer 312 located below the pixels 315-41, and operates in the manner described above with reference to FIG. 1 to generate multiple electrons in response to incident electrons. The buried channel layer 316 is formed of an n-type dopant diffused into the epitaxial layer 312 above the electron sensitive region 312A, and is used to transfer electrons generated by the electron sensitive region 312A to the floating diffusion region FD. The floating diffusion FD (for illustrative purposes, a schematic capacitor signal is used to depict the floating diffusion FD) is formed by diffusing into one of the n+ dopants in the buried channel layer 316 and used to collect the electron sensitive region 312A At least part of the generated plurality of electrons, thereby generating a corresponding charge (voltage) in the manner described above with reference to FIG. 1. The amplifier 317 includes transistors M1, M2, and M3, and is used to generate an associated output signal OS41 whose voltage level is determined by one of the electrons collected on the floating diffusion FD in any given readout operation Number determination. Each pixel also includes a reset transistor RT, which is used to reset the voltage level of the pixel floating diffusion FD after each readout operation. The sensor circuit 310 is depicted in a cross-sectional manner in FIG. 3a to illustrate a preferred embodiment, in which pixels 315-11 to 315-44 are fabricated on a thin film structure including an epitaxial layer 312 and a boron layer 313. In one embodiment, the substrate 311 is a p+ (ie, highly p-doped) substrate, and the epitaxial layer 312 is a p-epitaxial layer (ie, a layer with a low concentration of p-dopant). Preferably, one thickness T of the epitaxial layer 312 is between about 40 μm and about 100 μm to keep the time taken for electrons to drift from the electron sensitive region to the buried channel layer to be limited to less than about 10 ns, At the same time provide good mechanical strength. Depending on the mechanical support provided by the substrate 311, the epitaxial layer 312 can be made thinner than 40 μm, such as between about 10 μm and about 40 μm. After forming the epitaxial layer 312, one or more additional layers (not shown) are formed on the epitaxial layer 312 (eg, gate oxide layer, silicon nitride gate layer, and one or more dielectric layers) , And one or more doped regions are formed in the epitaxial layer 312 (eg, n-type buried channel portion 316, n+ floating diffusion region FD, channel region associated with a reset transistor RT, and an amplifier 317 And a doped region associated with a circuit element (not shown in the figure) in front of the formation of the control circuit 318 (which is disposed in the peripheral region of the pixel array). Forming various pixel transistors and front-side circuit elements includes implanting or doping a portion of the front side of the epitaxial layer, and may involve patterning the gate layer. Next, the portion of the substrate 311 disposed below the pixels 315-11 to 315-44 is removed (thinned) to expose the electron sensitive (front side) surface 312-ES, and then the boron layer 313 is formed on the electron sensitive surface 312 -ES. For example, the co-owned and co-pending U.S. Published Patent Application 2013-0264481 with the name "Back-illuminated Sensor With Boron Layer" and applied by Chern et al. on March 10, 2013 is depicted in Figure 3a. The additional details related to the formation of the thin film structure of this case are incorporated herein by reference. FIG. 3b is a simplified diagram showing additional details of the exemplary pixels 315-41 of FIG. 3a. Specifically, the amplifier 317 includes a first NMOS transistor M1 having: a drain terminal connected to a voltage source VOD; a gate terminal connected to the floating diffusion FD and stored in the floating diffusion Charge control on the FD; and a source terminal connected to the drain terminal of a second NMOS transistor M2 and the gate terminal of a third NMOS transistor M3. The gate and source terminals of transistor M2 are connected to ground, and the drain terminal of transistor M3 is connected to the voltage source VOD, whereby the output terminal of amplifier 317 is formed by the source terminal of transistor M3. The pixels 315-41 also include an NMOS reset transistor RT, which has: a source terminal connected to the floating diffusion FD; a gate terminal controlled by a reset control signal RG; and a drain terminal, It is connected to a reset voltage RD. During the operation of the pixels 315-41, each detection/readout cycle starts by resetting the floating diffusion FD to the voltage RD by triggering the reset transistor RT, then waits for a predetermined detection period, and then outputs the output signal OS41 sampling. If 0 incident (ie, backscattered or secondary) electrons enter the electron sensitive area of pixels 315-41 during the detection period, the voltage levels on the floating diffusion FD and the output signal OS41 are reset during readout There is no significant change in the value. If one or more incident (ie, backscattered or secondary) electrons enter the electron sensitive area of the pixels 315-41 during the detection period, the voltage level on the floating diffusion FD changes (becomes more negative) and The number of incident electrons is proportional to the amount of energy (which is indicated by the number of electrons accumulated in the floating diffusion FD), whereby the voltage level of the output signal OS41 during readout provides the period during which the detection/readout cycle The approximate energy level of the detected incident electrons (or the sum of energies (if multiple electrons are incident during the detection/readout cycle)). When operating at a 100 MHz operating rate, 100 million detection/readout cycles are performed on each pixel every second. According to a preferred embodiment of the present invention depicted in FIG. 3b, the floating diffusion area of each pixel is located in a central area of its pixels, and the nominal lateral size of each pixel is about 250 μm or less to facilitate During each detection/readout cycle, electrons are transferred to the floating diffusion area. Referring temporarily to FIG. 3a, the lateral size is measured in the X-Y plane coplanar with the silicon structure 311, and the lateral size indicates the area occupied by each pixel. Referring to FIG. 3b, the floating diffusion FD is located in a central region C (FIG. 4a) of the area occupied by the pixels 315-41, where the width of the pixels 315-41 is indicated by the width dimension X1, and the length of the pixels 315-41 is determined by the size Y1 indication. According to the presently preferred embodiment, both sizes X1 and Y1 are about 250 μm or less to facilitate high-speed readout operations. Because of the drift speed of electrons in silicon, when it is desired to read out pixels 315-41 at a data rate of about 100 MHz or higher, the lateral dimension of each pixel preferably does not exceed about 250 μm, so that Drive electrons to the floating diffusion FD in the center within ns or less. For lower rate operation, pixels larger than 250 μm are acceptable. For operation at rates significantly higher than 100 MHz, pixel sizes smaller than 250 μm are preferred. Referring to the upper part of FIG. 3a, the analog-to-digital converters 325-11 to 325-44 are manufactured on the semiconductor substrate 321 together with the optional signal processing circuit 328-1 and the optional signal transmission circuit 328-2 according to a known technique . In one embodiment, to facilitate a one-to-one signal connection between pixels 315-11 to 315-44 and the analog-to-digital converters 325-11 to 325-44 discussed below, the analog-to-digital converter 325- 11 to 325-44 are arranged in a pattern substantially in mirror image with the array pattern (matrix) formed by the pixels 315-11 to 315-44. The digital values generated by the analog-to-digital converters 325-11 to 325-44 are transmitted by the conductor 329 to the processing circuit 328-1, which is configured to be associated, for example, based on one of the self-sensor circuits The digitalized output signal (image data) received by the pixel calculates the approximate energy of an incident electron. For example, the selected high-speed data transmission circuit 328-2 is used to transmit the image data signal ID to an external processing system (such as a computer). In one embodiment, in addition to the array of analog-to-digital converters 325-xx, the signal processing circuit 320 includes a processing circuit 328-1 configured to, for example, associate pixels based on one of the self-sensor circuits The received digital output signal (image data) is used to calculate the approximate energy of an incident electron. In another embodiment, the signal processing circuit 320 also includes a high-speed data transmission circuit 328-2, which is used to transmit an image data signal ID to an external processing system (eg, a computer). Referring again to the lower part of FIG. 3a, the output signals OS11 to OS44 generated by the pixels 315-11 to 315-44, respectively, are transmitted to a correlation disposed on the signal processing circuit 320 by an associated conduction path (indicated by a dotted line). Connect analog-to-digital converters 325-11 to 325-44. For example, the pixel 315-11 transmits the output signal OS11 to the analog-to-digital converter 325-11 through a dedicated conduction path, the pixel 315-12 directly transmits the output signal OS12 to the analog-to-digital converter 325-12, etc. . In the preferred embodiment described below with reference to FIG. 3c, the output signals OS11 to OS44 may be metal pads, solder balls/solder bumps, or similar structures (which provide individuality between each pixel and its associated analog-to-digital converter) Signal path) transmission. As explained herein, each pixel has multiple signals or electrical connections, such as gates, control signals, power supplies, and ground. For a practical and cost-effective assembly, the interconnect density is too high to connect each of these signals to each pixel individually. Preferably, most or all of these signals are connected together between adjacent pixels and brought to a convenient location, such as near the edge of a sensor in which an external electrical connection can be formed. For example, as indicated in FIG. 3a, signals RD, RG, and VOD are transmitted by a metal conductor (signal line) 319 from a control circuit area 318 to pixels in each column. In an actual device, there may be more than three signals connected together between pixels, but the three signals are shown here to illustrate the principle. Wiring, solder balls or solder bumps (as described below with reference to FIG. 3c) or other techniques may be used to form external connections to signals such as RD, RG, and VOD. As shown in FIG. 3a, the connections between signals can be formed mainly or exclusively in a direction such as the horizontal direction shown to simplify interconnection and allow only a single metal layer to be used. For example, one sufficiently large area outside the active area of the sensor or two or more metal layers can be used to easily form interconnects in two dimensions if additional cost can be adjusted. Compared with the common signal line of the sensor circuit 310, as indicated in the upper part of FIG. 3a, the various types of ratio-to-digital converters 325-11 to 325-44 of the signal processing circuit 320 are through a separate conductor (signal line) 329 is coupled to the processing circuit 328-1 to maximize data transfer and processing. FIG. 3c illustrates an exemplary electronic detector 300A including an electronic sensor 310A, an ASIC (signal processing circuit) 320A, and a substrate 301. The substrate 301 provides mechanical support to the electronic detector 300A and allows external electrical connection to the electronic detector 300A (not shown in the figure). The substrate 301 may include silicon or a ceramic material. The electronic sensor 310A and the ASIC 320A are fabricated on separate silicon substrates (die or wafer), and then these separate silicon substrates are stacked on top of each other, as shown in the figure. Alternatively, the electronic sensor 310A and the ASIC 320A may be placed on opposite sides of the substrate 301 or placed side by side on the substrate 301 (not shown in the figure). The electronic sensor 310A is preferably a multi-pixel electronic sensor similar to the multi-pixel electronic sensor depicted in FIGS. 3a and 3b, and even more preferably includes, for example, the following (for example) with reference to FIG. 4a And the pixels described in FIG. 4b. During operation, the electronic detector 300A is positioned so that the electronically sensitive surface 312-ES faces a sample or other electron source, whereby the detected electrons are incident on the electronically sensitive surface 312-ES and are treated as described herein Detect. The electronic sensor 310A is electrically connected to the ASIC 320A through solder balls or solder bumps 306. In a preferred embodiment, an associated solder ball/solder bump 306 transmits the output signal generated by each pixel 315 of the electronic sensor 310A to an associated analog-to-digital converter 325 of the ASIC 320A. For example, an associated conductor transmits the output signal OS11 generated by the pixel 315-11 to a first pad 309 disposed on the lower surface of the sensor 310A, and the associated solder ball/solder bump 306-11 will The output signal OS11 is transmitted from the first pad 309 to a second pad disposed on the ASIC 320A, and the output signal OS11 is transmitted from the second pad to the input terminal of the associated analog-to-digital converter 325-11. One or more solder balls/solder bumps 306 may also be used to transmit signals from the ASIC 320A (eg, from the circuit 328) to the control circuit 318 of the sensor 310A. These balls or bumps also provide mechanical support to the electronic sensor 310A and provide thermal conductivity to the electronic sensor 310A. Solder balls or solder bumps may be used instead to mount the electronic sensor 310A directly to the substrate 301 (not shown in the figure). Metal pads may also be provided on the electronic sensor 310A to enable wiring to provide electrical connection to the electronic sensor 310A (eg, to the surface 312-ES of the electronic sensor 310A). The ASIC 320A may be directly mounted to the substrate 301 (as shown in the figure), or may be mounted and electrically connected to the substrate 301 by solder balls or solder bumps (not shown in the figure). If the ASIC 320A includes TSVs, solder balls or solder bumps can be used on both sides of the ASIC 320A. Metal pads 307 and 327 and/or wiring 339 may be used to form an electrical connection between ASIC 320A and substrate 301. A similar wiring connection may be formed between the sensor 310A and the substrate 301, or all connections between the substrate 301 and the sensor 310A may be formed through the ASIC 320A. The ASIC 320A may include a single ASIC or two or more ASICs. For example, in one embodiment, the ASIC 320A may include two ASICs, one ASIC mainly contains analog functions and the other ASIC mainly contains digital functions. Additional integrated circuits (such as an optical fiber transmitter or an optical fiber receiver (not shown)) can also be mounted on the substrate 301. The ASIC 320A preferably includes an analog-to-digital converter 325 configured to digitize the output signal from the pixel 315 of the electronic sensor 310A. In one embodiment, the ASIC 320A includes an analog-to-digital converter 325 for each pixel 315 so that all pixels 315 can be digitized in parallel at a high speed (such as at a rate of 100 MHz or higher). Each pixel 315 can use a high digitization rate (such as 100 MHz or higher) to detect at most several electrons per clock cycle. Therefore, each type of digital-to-digital converter 325 may only require 8, 6 or more Less bits. It is easier to design a converter with a smaller number of bits to operate at high speed. An analog-to-digital converter with a smaller number of bits can occupy a small area of silicon so that an ASIC can actually have a larger number, such as 1024 or greater. ASIC 320A preferably implements part of the method shown in FIG. 2. For example, when the electron detector 320A is used as a backscattered electron detector, the ASIC 320A may implement step 208, or when the electron detector is used as a secondary electron detector, the ASIC 320A may implement step 212 . The ASIC 320A may further incorporate a circuit to generate the first pixel clock signal or the second pixel clock signal described in FIG. 2, or may receive a pixel clock signal from an external circuit. When the electron detector 300A is used as a secondary electron detector, the ASIC 320A can implement a secondary electron solution similar to the secondary electron solution scan performed by the electron optical device in the '791 patent cited above. scanning. The ASIC 320A may sum the signals from a group of pixels (which correspond to secondary electrons emitted from the sample to an angular range) and output the sum as a signal. As the electron beam deflection changes, the ASIC 320A can add up a different group of pixels with a changed deflection that roughly corresponds to the same angular range. Since the same main clock is used to generate or synchronize the electron beam deflection and the first pixel clock and the second pixel clock are generated or synchronized, ASIC 320A has to adjust which group of pixels are added together to combine with the electron Timing information required for beam deflection scanning synchronization. When the electron current is low and the pixel clock rate is high enough so that the average number of electrons per pixel is significantly less than 1, the charge collected in a single pixel in a single period of the pixel clock cycle can be used to determine whether it is in the An electron is detected in the pixel during the clock cycle, and if it has been detected, it is determined that one of the electrons has similar energy. The boron coating on the surface of the electronic sensor needs to achieve this capability. Without a boron coating, when the incident electron energy is less than about 1 keV, little or no electrons are generated per incident electron. With a boron coating about 5 nm thick, about 100 electrons are generated for every 1 keV of incident electrons. If the capacitance of the floating diffusion is small enough to generate more than about 10 μV per electron, this signal can be detected to be higher than the noise level. In an embodiment, the capacitance of the floating diffusion is small enough so that the floating diffusion generates more than about 20 μV per electron. For these low-level signals, it is important to couple each pixel to the corresponding analog-to-digital converter by a path as short as possible to keep the noise level low and the stray capacitance low. Attaching the electronic sensor directly to the ASIC allows a very short path from each pixel to one of the corresponding analog-to-digital converters. When an individual electron can be detected, the ASIC 320A can use the signal level to determine the approximate energy of one of the electrons. The ASIC 320A can further limit, count or square the incident electrons according to the energy of the incident electrons to detect or classify one or more types of defects or materials on the sample. 4a and 4b are respectively an exploded perspective view of a simplified pixel 400 of an electronic sensor (such as the sensor 310 described above with reference to FIG. 3a) according to another exemplary specific embodiment of the present invention and Combination perspective. Similar to the pixels described above, the pixel 400 preferably has a size (nominal lateral dimension) between about 200 μm and about 250 μm. 4a, similar to the pixel features mentioned above, the pixel 400 includes: a p-type electron sensitive layer 457A; an n-type buried channel layer 455, which is disposed above the p-type electron sensitive layer 457A; An n+ floating diffusion FD, which is formed in the n-type buried channel layer 455; an amplifier 410; and an optional pure boron layer 460, which is disposed under the p-type electron sensitive layer 457A. The buried channel layer 455 and the electron sensitive layer 457A are disposed in an epitaxial silicon layer 457 so that an upper layer of the buried channel layer 455 coincides with a top (first) surface 457-S1 of one of the epitaxial silicon layer 457 (The top (first) surface 457-S1 of the epitaxial silicon layer 457 is formed), and the electron sensitive layer 457A includes a bottom (electronic sensitive) surface 457-S2 disposed on one of the buried channel layer 455 and the epitaxial silicon layer 457 A part of the epitaxial silicon layer 457. The epitaxial silicon layer 457 has a thickness preferably between about 10 μm and about 100 μm, and is slightly p-doped so that in one embodiment, the resistivity is between about 10 Ω·cm to about 2000 Ω·cm between. A thicker epitaxial layer provides greater mechanical strength, but can generate greater dark current. A layer thicker than about 20 μm or about 30 μm requires a lower doping level (higher resistivity) to maintain a fully depleted state in the bulk of silicon. A doping level that is too low is not preferable because it will result in a higher dark current. The buried channel layer 455 is created under the top surface 457-S1 of the epitaxial silicon layer 457 by n-type doping diffusion using known technology. The doping concentration of the buried channel layer 455 must be an order of magnitude greater than the doping concentration in the epitaxial silicon layer 457, so that the epitaxial silicon layer 457 is completely depleted during operation. In a preferred embodiment, the concentration of the n-type dopant in the buried channel layer 455 is about 10¹⁶ cm^-3 Up to about 5×10¹⁶ cm^-3 between. The floating diffusion FD includes a relatively small n+ doped region disposed in the buried channel layer 455, which is configured to collect electrons generated in the pixel 400 in response to incident backscatter or secondary electrons. In a preferred embodiment, the floating diffusion FD has a nominal lateral size between about 1 μm and about 5 μm, and the concentration of the n-type dopant in the floating diffusion FD is about 10¹⁹ cm^-3 Up to about 10^{twenty one} cm^-3 between. A connection to the floating diffusion FD is formed using known techniques to transfer stored charge to the amplifier 410. The pure boron layer 460 is preferably deposited on the back surface or bottom surface 457-S2 of the epitaxial silicon layer 457. The boron layer 460 is preferably between about 2 nm to about 10 nm thick, such as one of about 5 nm thick. As explained in US Patent Application 13/792,166 (as cited above), during the boron deposition process, some boron diffuses a few nanometers into the epitaxial silicon layer 457 to form a thin layer adjacent to the pure boron layer 460 Very highly doped p+ layer. This p+ layer is important for optimal operation of the sensor. This p+ layer generates an electric field that drives electrons towards the buried channel 455, reduces dark current from the backside of the epitaxial silicon layer 457, and increases the conductivity of the silicon surface to allow the sensor to respond to high incident electron current and low current run. In one embodiment, during the deposition of the pure boron layer 460, additional boron is allowed to diffuse into the silicon. This can be done by one of several methods. In an exemplary method, a boron layer thicker than the final desired thickness is deposited (for example, when a final thickness of 5 nm is required, a 6 nm to 8 nm layer can be deposited), and then by keeping the sensor in the deposition A temperature or a higher temperature (such as between about 800°C and about 950°C) for several minutes to allow boron to diffuse into the silicon epitaxial layer 457. In another exemplary embodiment, a boron layer with a thickness of several nanometers can be deposited on the silicon, then boron can be driven at the deposition temperature or a higher temperature, and then the final desired thickness of boron (such as 5 nm). According to one aspect of this embodiment, the amplifier 410 is formed in and above an elongated p-well region 459, the p-well region 459 extends vertically from the top surface 457-S1 into the electron sensitive layer 457A, and It extends outward from a point adjacent to the central region C of the pixel (ie, toward the outer peripheral edge 455-OPE of the n-type buried channel layer 455). It should be noted that the p-well region 459 is shown separated from the silicon epitaxial layer 457 in FIG. 4a for descriptive purposes, but in fact, the p-well region 459 includes one of the p-type doped regions of the silicon epitaxial layer 457. In alternative embodiments, the p-well 459 is completely contained within the square peripheral boundary of the pixel 400, or extends across the peripheral boundary (eg, into an adjacent pixel). In one embodiment, the p-well 459 is formed by implanting boron with a concentration substantially higher than the dopant concentration in the silicon epitaxial layer 457, and then the n-type channels of various transistors of the amplifier 410 are made The region 412 is formed in the p-well 459, whereby the p-well 459 is used to prevent electrons from directly migrating from the epitaxial silicon layer into the channel region 412. In one embodiment, the p-well extends below the channel region of the floating diffusion region and the pixel reset transistor (discussed below with reference to FIG. 7) to prevent electrons from directly migrating from the epitaxial silicon layer into the floating diffusion region. As indicated in Figure 4a, one or more dielectric layers 454 cover the buried channel. The dielectric layer 454 may include a single silicon dioxide layer, a silicon nitride layer on top of the silicon dioxide layer, or a silicon oxide layer on top of the silicon nitride layer on top of the silicon dioxide layer. The thickness of individual layers may be between about 20 nm and about 50 nm. According to another aspect, the pixel 400 further includes a resistive gate 451 including one or more polysilicon or non-crystalline silicon disposed on the dielectric layer(s) 454 and configured to cover most of the upper surface 457-S1 Crystal silicon gate structure 470. As indicated in FIG. 4a, the resistive gate 451 includes an outer peripheral edge 451-OPE that is substantially aligned with the periphery of the pixel 400 (ie, substantially aligned with the outer peripheral edge 455-OPE of the buried channel layer 455 Quasi), and defines a central opening 451-CO, such that an inner peripheral edge 451-IPE of the resistive gate 451 (ie, the inner edge of the gate structure 470) substantially surrounds the central pixel region C and is transverse to the central pixel region C Spaced apart (as indicated in Figure 4b). In one embodiment, the gate structure 470 includes polysilicon, which has a relatively light doping level (eg, having a resistivity higher than about 30 Ω/cm), so that the inner peripheral edge 451-IPE When a reduced potential difference is applied to the outer peripheral edge 451-OPE, the resistive gate 451 generates an associated electric field that makes the buried channel layer 455 in the manner described below with reference to FIGS. 5a and 5b The electron bias is directed toward the central area C of the pixel. To facilitate the operation of the resistive gate 451 so that electrons are biased from all peripheral lateral regions of the pixel 400 toward the central region C to be collected by the floating diffusion FD, the resistive gate 451 also includes along and adjacent to the outer peripheral edge 451-OPE And the inner peripheral edges 451-IPE are arranged on the gate structure 470 of the elongated conductors (such as metal wires) 471 and 472. As described below, a negative potential relative to one of the elongated conductors 472 is applied to the elongated conductor 471, such as a voltage of -5 V. The resulting potential difference between conductors 471 and 472 produces a reduced potential in one of the gate structures 470 in a substantial radial direction (ie, between the inner peripheral edge 451-IPE and the outer peripheral edge 451-OPE), the reduced The small potential drives the electrons in the buried channel (see FIG. 4b) toward the floating diffusion FD. An additional connection to the gate structure 470 may be provided between the conductors 471 and 472 and maintain a potential intermediate between the potentials applied to the conductors 471 and 472 in order to modify the potential gradient in the resistive gate 451. Additional details regarding the composition of the resistive gate 451 can be found in US Patent Application 11/805,907, entitled "Inspection System Using BackSide Illuminated Linear Sensor" and filed by Armstrong et al. on May 25, 2007. The entire text of this patent application is incorporated herein by reference. According to another aspect, the pixel 400 further includes one or more optional additional gate structures, which are disposed between the resistive gate 451 and the floating diffusion FD to further drive electrons onto the floating diffusion FD or control when Collect/accumulate such electrons on the floating diffusion FD. For example, the pixel 400 includes a C-shaped highly doped poly gate structure 453, which is disposed on the dielectric layer 454 and the inner peripheral edge 451-IPE of the resistive gate 451. A constant or switching voltage can be applied to the gate structure 453 to control and ensure that charge is efficiently transferred from the portion of the buried channel layer 455 under the resistive gate 451 to the floating diffusion FD. In one embodiment described below with reference to FIGS. 5a and 5b, the gate structure 453 is used as a summing gate, a low voltage (such as 0 V (relative to the bottom surface 457-S2 or boron layer is applied during reset 460) is applied to the summing gate, and a high voltage (such as 10 V) is applied to the summing gate during readout. In addition to the summing gate 453, one or more additional gates (such as (A buffer gate, a transfer gate, and an output gate) can also be formed by an associated additional gate structure placed between the resistive gate 451 and the floating diffusion FD. These gates are already known in CCD technology It is well known and can be operated in a similar manner in this electronic sensor. See, for example, "Scientific Charge-Coupled Devices" by JR Janesick, SPIE Press, 2001, pages 156 to 165. Figure 4b shows a simplified pixel 400 in a part of the combined state. As indicated in the figure, most of the pixel 400 (ie, most of the top surface 457-S1) is covered by the amorphous silicon or polysilicon gate structure 470 forming the resistive gate 451. For illustration purposes, the exposed area above the p-well area 459 (indicated by the dotted frame) is indicated as empty, but in fact, the exposed area includes various types of transistors associated with the amplifier 410 and a reset transistor RT Connection structure and gate. An exemplary layout of these structures and gates is provided below with reference to FIG. 7. In one embodiment (not shown), the sum gate 453 overlaps the inner peripheral edge 451-IPE of the resistive gate 451 (ie, extends over the inner peripheral edge 451-IPE of the resistive gate 451 and is formed by a It is suitable for insulator separation to keep the inner peripheral edge 451-IPE of the sum gate 453 and the resistance gate 451 electrically isolated). This overlapping configuration prevents the fringing electric field in the silicon below the gap between the two gate structures. These fringe fields can trap electrons in buried channels or cause electrons to move in unexpected directions. 5a and 5b show a simplified cross-sectional view of a pixel 400 during an exemplary detection/readout cycle (operation), where FIG. 5a depicts resetting the floating diffusion to a reset voltage (ie, OS₄₀₀ Equal to a reset voltage level V_RST ) At a time T0 or resetting the floating diffusion to the pixel 400 at an instant time T0 immediately after the reset voltage, and FIG. 5b depicts the readout of the output signal OS in the manner described above₄₀₀ Time (ie, OS₄₀₀ Is equal to a voltage level V determined by the number of electrons accumulated on the floating diffusion FD between time T0 and T1_FD Time) one of the pixels 400 at a subsequent time T1. It should be noted that the individual layers shown in FIGS. 5a and 5b are not drawn to scale, but are enlarged to show these individual layers more clearly. Referring to FIG. 5a, the back surface coated with the pure boron layer 460 is preferably maintained to have a potential similar to the outer edge of the resistance gate (such as 0 V in this example). Since the boron is conductive and the silicon directly under the pure boron layer 460 is highly doped with boron, the back surface can be sufficiently conductive so that a low enough impedance path is provided at one or several locations connected to it The incident current (such as a current of about 10 nA to about 50 nA) operates the sensor. The electric field formed by this equipotential difference drives electrons (such as E460) generated in the epitaxial silicon (electron sensitive) region 457A by backscattering or secondary electrons incident on the sensor through the pure boron layer 460 toward the buried channel 455, as shown by the arrow on the electronics. A potential difference is applied by the conductors 471 and 472 to the resistive gate 451 between the outer edge of the pixel 400 and the inner edge of the gate structure 470. In one example, 0 V is applied to the outer edge by conductor 471, and 5 V is applied to the inner edge by conductor 472, as shown in the figure. The resulting potential difference in the gate structure 470 generates an electric field that drives electrons (such as E451) disposed in the buried channel 455 toward the center of the pixel 400 (ie, causes these electrons to move toward the floating diffusion FD). In the example depicted in FIGS. 5a and 5b, the summing gate 453 is used to control the electrons and drive them into the floating diffusion FD. For example, as indicated in FIG. 5a, when the transfer of electrons to the floating diffusion FD is blocked (for example, during reset), the voltage applied to the summing gate is significantly lower than the voltage applied to the conductor 472, thereby The electric field prevents electrons from easily flowing to the floating diffusion FD and causes the electrons to accumulate in the buried channel 455 under 472 (as indicated by electron E451). Conversely, as indicated in FIG. 5b, when transferring electrons to the floating diffusion FD (for example, just before readout), the summing gate 453 receives a relatively high positive potential (relative to the application to the conductor 472 A voltage of, for example, 10 V, relative to 5 V applied to the conductor 472, as shown in the figure) to cause electrons (such as E453) under the conductor 472 to move toward the floating diffusion FD. Since the floating diffusion FD acts as a capacitor, the voltage V on the floating diffusion FD during reading_FD It becomes more negative as more charges (electrons) accumulate. For small signals, the voltage V_FD The change is proportional to the accumulated charge (ie, the capacitance of the floating diffusion FD is substantially constant), but as the amount of charge increases, the capacitance change and voltage increase are no longer linear. Although operation in a linear system is generally preferred, in one embodiment, operation in a nonlinear system can be used to compress a high dynamic range signal. Since the sensitivity (charge-to-voltage conversion rate) and rate depend on the capacitance of the smaller floating diffusion FD, it is generally preferable to keep the floating diffusion FD as small as practical and to make the structure connected to the floating diffusion FD ( It includes resetting the size of the channel of the transistor and the connection to the gate of transistor M1 (and therefore the capacitance) to a minimum. It should be noted that the voltage values quoted in the examples above are only examples. Different values can be used, and the optimal value depends on many factors including the desired rate of operation of the sensor, the geometry of one or more gates, the doping profile, and the thickness of the dielectric layer(s) 454. It should also be noted that it is often convenient to define the back side of a sensor (ie, the electronically sensitive side) as 0 V (note that if the electronic detector is floated at a potential other than ground, this voltage Can be away from ground potential), and conductor 471 will preferably be connected to a similar potential. In an alternative embodiment, instead of switching the voltage across the reset transistors and various gates of each pixel, the reset transistors and various gates are kept at a fixed potential so that the epitaxial silicon (electronically sensitive) region 457A The generated electrons can continuously flow to the floating diffusion FD. In this mode, the voltage on the reset gate RG (Figure 3b) must be maintained to cause the reset transistor RT to be in a high resistance, partially conductive state (such as a channel between approximately 500 kΩ and several MΩ Resistance) instead of "cutting off" (which corresponds to a channel resistance of hundreds of MΩ or higher) or "turning on" (which corresponds to a channel resistance of several kΩ or lower). In this embodiment, one or several gates between the inner peripheral edge of the resistive gate 451 and the floating diffusion FD must be kept to have successively higher voltages (all higher than the voltage of the conductor 472), so that the buried type The electrons in the channel 455 will be driven toward the floating diffusion FD. For example, if the conductor 472 has a potential of 5 V, the summing gate 453 can be kept at a voltage of 6 V. If there is another gate (not shown in the figure) between the inner peripheral edge of the resistance gate 451 and the sum gate 453, the other gate (for example) can be kept at 6 V and the sum gate The 453 remains at 7 V. The reset drain RD must be kept at a positive voltage significantly greater than one of the innermost gates (such as the summed gate 453) in order to keep the floating diffusion FD at a significantly high potential relative to one of all gates to attract the buried type The electron in the channel. For example, the reset drain RD can be kept at 15 V. It should be easy to understand that resetting the channel of the transistor RT and the capacitance of the floating diffusion FD forms an RC time constant that determines how quickly a voltage on the floating diffusion FD decays back to reset after electrons reach the floating diffusion FD Drain RD voltage. For example, if the analog-to-digital converter samples each pixel at 100 MHz (ie, every 10 ns), an RC time constant of about 20 ns or about 30 ns may be appropriate. In this example, if the capacitance of the floating diffusion is about 10 fF, the voltage of the reset gate RG should be set so that the resistance of the channel of the reset transistor RT is about 2.5 MΩ to give a time constant of about 25 ns . This embodiment can be performed by the sensors disclosed herein because each pixel is connected to its own analog-to-digital converter. In a conventional two-dimensional CCD or CMOS image sensor, charge needs to be stored and the charge is continuously read out when the number of analog-to-digital converters is less than the number of pixels. In addition, conventional CMOS image sensors use transistors and gates with surface channels instead of buried channels. Compared with buried channels, surface channels generate noise and cannot transfer small charges without loss. FIG. 6 shows a simplified plan view of a portion of pixel 400A, and in particular, shows a floating diffusion FD utilized by pixel 400A, an amplifier 410A, and a reset transistor RT according to an exemplary particular embodiment of the present invention. One of the exemplary layouts. In one embodiment, the pixel 400A is substantially the same as the pixel 400 described above (ie, where the floating diffusion FD is located in a central area of the pixel 400A), therefore, for simplicity, the unillustrated pixel 400A is omitted示段。 Show part. In FIG. 6, the doped region (for example, the floating diffusion FD) is indicated by a dot-shaped hatched region, the conductive structure (for example, polysilicon or metal) is indicated by the diagonal region, and the vertical metal via is indicated by the box containing the "X" symbol . It should be noted that the various amplifier polysilicon or metal structures are separate (ie, not contiguous), and standard techniques are used to pattern and interconnect the various amplifier polysilicon or metal structures. In this example, the reset transistor RT is placed directly under the floating diffusion FD, and the amplifier 410A includes transistors M1, M2, and M3 connected and operating in a manner similar to that described above with reference to FIG. 3b . For clarity, additional connections and vias associated with the structure shown in FIG. 6 are omitted. Referring to the upper part of FIG. 6, the floating diffusion FD is arranged adjacent to the p-well region 459A, which is formed in the manner described above and includes the transistor M1 to the reset transistor RT and the amplifier 410A Various n-type channel regions associated with M3. For example, the reset transistor RT includes an N-type channel region 412A_RT It is placed in the p-well region 459A directly under the floating diffusion FD and connected to the floating diffusion FD and receives the reset voltage RD, and includes a gate structure controlled by the reset gate signal RG. Transistor M1 includes an N-type channel region 412A located immediately below reset transistor RT in p-well region 459A_M1 And includes: a gate structure connected to the floating diffusion FD; a drain structure connected to the system voltage VOD; and a source structure connected to a drain structure of the transistor M2 and the transistor M3 One gate structure. Transistor M2 includes an N-type channel region 412A located immediately below transistor M1 in p-well region 459A_M2 And includes a gate structure and a source structure connected to ground. Transistor M3 includes an N-type channel region 412A located immediately below transistor M2 in p-well region 459A_M3 And includes: a drain structure connected to the system voltage VOD; and a source structure used in a configuration similar to the configuration shown and described with reference to FIG. 3c by a metal pad or solder ball / Solder bump 406 and output signal OS of one of the pixels 400A_400A To an associated analog-to-digital converter. It should be noted that the metal pad for the OS may be located at a position away from the center of the pixel 400A, and in one embodiment, may cover a portion of one or more adjacent pixels. In one embodiment, the reset transistor RT is controlled to use a reset gate voltage RG having a sufficiently large positive value to discharge the floating diffusion FD to the reset voltage RD to turn on the reset transistor RT. The RD should have a positive value greater than the voltage applied to various pixel gates (such as the resistive gate 451 and the sum gate 453 described above with reference to FIGS. 4a and 4b). For example, referring to the example shown in FIG. 5b (where 10 V is used to control the summing gate 453), the reset drain voltage RD may have a voltage value between about 15 V and about 20 V. The reset transistor RT needs to be turned on periodically to discharge the electrons that have accumulated in the floating diffusion FD. When the incident electron current that hits the pixel is small, there is no need to discharge the floating diffusion area each time the pixel is read out (resetting the floating diffusion area). When the incident current is high, it is necessary to reset the floating diffusion FD in every pixel clock cycle. FIG. 7 shows a partially simplified example sensor 700 configured according to another embodiment of the present invention, and depicts an alternative layout pattern in which the p-well area 759-1 of the pixel 740-1 extends to an otherwise adjacent pixel In the space occupied by 740-2, at least one control signal utilized by the pixel 740-1 is connected to a signal line 719-21 across a neighboring pixel 740-2. The p-well region and signal line discussed in this example are formed and operated in a manner similar to the p-well region 459 and signal line 319 discussed in additional detail above with reference to FIGS. 4a and 3a, respectively. It should be noted that the metal wiring harnesses 719-1 and 719-2 extend over all other structures and are separated from the underlying polysilicon structure (such as the resistive gate 770-1) by a borophosphosilicate glass layer or other dielectric materials, And through the metal via (not shown in the figure) to connect to the underlying structure. It should also be noted that, for clarity and conciseness, some structures of the pixels 740-1 and 740-2 described above are omitted in FIG. 7. As mentioned above, in addition to the central area (ie, used to allow access to the floating diffusion area) and the area in which a p-well is formed, it is used to generate a resistive gate in each pixel (and any The amorphous or poly gate structure of the additional gate, such as the sum gate 453), substantially completely covers the pixel area. In the example described above with reference to FIGS. 4a and 4b, the p-well region 459 is completely disposed within the square boundary of each pixel, and therefore, the resistance gate and the summing gate completely extend around the remaining periphery of the pixel 400. However, in some cases, the M3 amplifier transistor needs to cause it to extend beyond the width of one of the lower pixel boundaries. To accommodate the extended M3 transistor shape, the pixel of the sensor 700 is configured to share a portion of its space with an adjacent pixel. Specifically, in order to provide space for both its own elongated p-well region 759-1 and the portion of the p-well region 759-0 extending downward from the upper pixel (not shown in the figure), the resistance of the pixel 740-1 The gate structure 770-1 is formed into a substantially "H" pattern. Similarly, the resistance gate structure 770-2 of the pixel 740-2 is formed in the same "H"-shaped pattern to accommodate the portion below the p-well 751-1 and the portion above the p-well region 759-1. As also discussed above, the pixels in each column of the sensor 700 share a common signal line that extends along the entire column to a peripheral positioning control circuit (not shown). In the case shown in FIG. 7, the signal harness 719-1 extends over the column including the pixel 740-1, and the signal harness 719-2 extends over the column including the pixel 740-2. Due to the extension of the p-well region into adjacent pixels, in some cases, the signal connection from the signal harness extending over an adjacent pixel is efficiently provided. For example, the signal line 719-21 is connected to a transistor structure (not shown in the figure) disposed in the p-well region 759-1 through the conductor 719-21A, thereby connecting a signal (for example, 0 V/ground) from The signal harness 719-2 passing over the adjacent pixel 740-2 is provided to the pixel 740-1. Similarly, the signal line 719-11 of the signal harness 719-1 provides a signal to a transistor structure (not shown in the figure) disposed in the p-well region 759-0. FIG. 7 also depicts one of the preferred positions of the solder bumps/solder balls 7061 and 706-2 in the pixels 740-1 and 740-2 (ie, in the lower left quarter of each pixel area). It should be noted that the size of the solder bumps/solder balls 7061 and 706-2 in pixels 740-1 and 740-2 are substantially accurate for a 250 μm nominal lateral (eg diagonal) pixel size and a Standard solder bumps/solder balls. In alternative embodiments having pixels of different sizes or solder balls or solder bumps of different sizes, the relative sizes of the pads and pixels may be significantly different from the relative sizes depicted in FIG. 7. In one embodiment, the electronic detector described herein can also detect X-rays. If one of the X-rays emitted by the sample has sufficient energy (such as an energy of about 1 keV or higher), it can generate enough electrons when it is absorbed in the electronic sensor to be detected. The system and method described in this article can be used with any of the systems and methods described in the following: The name is "Tilt-Imaging Scanning Electron Microscope" and was applied by Jiang et al. on March 18, 2013 U.S. Published Patent Application 2014/0151552; U.S. Published Patent Application 2013/0341504 named "Auger Elemental Identification Algorithm" and filed by Neill et al. on June 7, 2013; named "Charged-particle energy analyzer" and U.S. Published Patent Application 2011/0168886 filed by Shadman et al. on March 17, 2011; and entitled "Use of design information and defect image information in defect classification" and by Abbott et al. on February 16, 2009 US published patent application 2010/0208979. All such applications are incorporated herein by reference. The various embodiments of the structure and method of the present invention described above merely illustrate the principles of the present invention and are not intended to limit the scope of the present invention to the specific embodiments described. For example, the size, shape, and layout of structures within a pixel can be significantly different from the size, shape, and layout shown herein. For example, an amplifier in a single pixel may include one, two, or three stages. More or fewer gates can be used to control the transfer of charge to the floating diffusion. The ASIC in the electronic detector may further include an FPGA or a digital signal processor to implement algorithms for processing or analyzing signals from the detector. The ASIC may also include a serial transmitter circuit and/or a serial receiver circuit to send data to an image processing computer and/or receive commands. Therefore, the scanning electron microscopes, sensors, and methods described herein are not intended to be limited to the specific embodiments shown and described, but should be given the most consistent with the principles and novel features disclosed herein Wide range.

100‧‧‧ scanning electron microscope (SEM) 101‧‧‧ cathode 102‧‧‧ extraction and focusing electrode 105‧‧‧ deflector 107‧‧‧ condenser lens 109‧‧‧ deflector 110‧‧‧ final (immersion ) Lens 120‧‧‧Electrode 121‧‧‧Secondary electron detector 122a‧‧‧Backscatter electron detector 122b‧‧‧Backscatter electron detector 123‧‧‧Solid state sensor 124‧‧‧Integration Semiconductor structure 125‧‧‧n-type buried channel layer 126‧‧‧ analog-to-digital converter 127‧‧‧p-type electronic sensitive layer 127-B‧‧‧top surface 127-F‧front surface/bottom surface 128 ‧‧‧ Pure boron layer 129‧‧‧Amplifier 130‧‧‧ Platform 131‧‧‧Sample 140‧‧‧Electronic gun/electron source 141‧‧‧Up 142‧‧‧Down 150‧‧‧Electron beam 160‧‧‧ System computer 200‧‧‧Method 201‧‧‧Step 202‧‧‧Step 204‧‧‧Step 206‧‧‧Step 208‧‧‧Step 210‧‧‧Step 212‧‧‧Step 214‧‧‧Step 216‧‧ ‧Step 300‧‧‧Multi-pixel electronic detector 300A‧‧‧Electronic detector 301‧‧‧Substrate 306‧‧‧Solder ball/solder bump 306-11‧‧‧Solder ball/solder bump 307‧‧ ‧Metal pad 309‧‧‧First pad 310‧‧‧Sensor circuit/sensor 310A‧‧‧Electronic sensor 311‧‧‧Silicon structure (chip)/substrate 312‧‧‧Epitaxial layer 312A‧ ‧‧P-type electronic sensitive area 312-ES‧‧‧Electronic sensitive (front side) surface 313‧‧‧Boron layer 315‧‧‧ pixels 315-11 to 315-14‧‧‧ pixels 315-21 to 315-24‧‧ ‧Pixel 315-31 to 315-34‧‧‧Pixel 315-41 to 315-44‧‧‧Pixel 316‧‧‧n-type buried channel layer 317‧‧‧Amplifier 318‧‧‧Control circuit/Control circuit area 319‧‧‧Metal conductor/Signal line 320‧‧‧Signal processing circuit 320A‧‧‧Integrated integrated circuit (ASIC)/Signal processing circuit 321‧‧‧Silicon structure (chip)/Semiconductor substrate 325‧‧‧Analog digital Converter 325-11 to 325-14 ‧‧‧ Analog to Digital Converter 325-21 to 325-24 ‧‧‧ Analog to Digital Converter 325-31 to 325-34 ‧‧‧ Analog to Digital Converter 325-41 To 325-44‧‧‧Analog to digital converter 327‧‧‧Metal pad 328‧‧‧ Circuit 328.1‧‧‧ Signal processing circuit 328-2‧‧‧Data transmission circuit 329‧‧‧Conductor 339‧‧‧ Wiring 400‧‧‧Pixel 400A‧‧‧Pixel 406‧‧‧ solder ball/solder bump 410‧‧‧ amplifier 410A‧‧‧ amplifier 412‧‧‧n-type channel area 412A _M1 ‧‧‧N Type channel area 412A _M2 ‧‧‧N type channel area 412A _M3 ‧‧‧N type channel area 412A _RT ‧‧‧N type channel area 451‧‧‧Resistance gate 451-CO‧‧‧Central opening 451-IPE‧‧ ‧Inner peripheral edge 451-OPE‧‧‧Outer peripheral edge 453‧‧‧Gate structure/total gate 454‧‧‧Dielectric layer 455‧‧‧n-type buried channel layer 455-OPE‧‧‧Outer Peripheral edge 457‧‧‧ epitaxial silicon layer 457A‧‧‧p-type electronic sensitive layer 457-S1‧‧‧top (first) surface/upper surface 457-S2‧‧‧bottom (electronic sensitive) surface 459‧‧‧ P-well area/P-well area 459A‧‧‧P-well area 460‧‧‧Pure boron layer 470‧‧‧Gate structure 471‧‧‧Conductor 472‧‧‧Conductor 700‧‧‧Sensor 7061‧‧‧‧ Solder bump/solder ball 706-2‧‧‧ Solder bump/solder ball 719-1‧‧‧Metal wire harness/signal wire harness 719-2‧‧‧Metal wire harness/signal wire harness 719-11‧‧‧Signal wire 719- 21‧‧‧signal line 719-21A‧‧‧conductor 740-1‧‧‧pixel 740-2‧‧‧pixel 759-0‧‧‧p well area 759-1‧‧‧p well area/p well 770- 1‧‧‧Resistance gate structure 770-2‧‧‧Resistance gate structure C‧‧‧Central area D‧‧‧Defect e ₁₂₅ ‧‧‧Electronic e _{127 ‧‧‧Electronic} e _{FD ‧‧‧Electronic} e _INCIDENT ‧ ‧‧Electron E451‧‧‧Electronic E453‧‧‧Electronic E460‧‧‧Electronic FD‧‧‧Floating diffusion area ID1‧‧‧Image data signal ID2‧‧‧Image data signal IDx‧‧‧Digital image data signal M1‧ ‧‧Transistor M2‧‧‧Transistor M3‧‧‧Transistor OS‧‧‧Output signals OS11 to OS14‧‧‧Output signals OS21 to OS24‧‧‧Output signals OS31 to OS34‧‧‧Output signals OS41 to OS44‧ ‧‧ Output signal OS ₄₀₀ ‧‧‧ Output signal OS _400A ‧‧‧ Output signal RD‧‧‧Signal/Reset voltage/Reset drain RG‧‧‧Reset control signal/Reset gate RT‧‧‧Reset Set transistor T‧‧‧thickness V _FD ‧‧‧ charge/voltage V _RST ‧‧‧ reset voltage level VOD‧‧‧signal/voltage source/system voltage X1‧‧‧ width dimension Y1‧‧‧ dimension

FIG. 1 illustrates an exemplary SEM incorporating a backscattered electron detector and a secondary electron detector according to an embodiment of the invention. FIG. 2 illustrates an exemplary method of inspecting or reviewing a sample. 3a, 3b and 3c illustrate the key aspects of an exemplary solid-state electronic detector (which includes multiple pixels with one output per pixel) according to one embodiment of the invention. 4a and 4b illustrate an exploded and combined front perspective view/top perspective view of a single pixel electronic sensor according to an exemplary specific embodiment of the present invention. 5a and 5b are simplified cross-sectional views showing the pixel of FIG. 4b during operation. 6 is a simplified plan view showing an exemplary layout of an amplifier utilized by a pixel according to an alternative embodiment of the present invention. 7 is a simplified plan view showing a pixel layout according to another alternative embodiment of the present invention.

100: Scanning electron microscope (SEM)

101: cathode

102: extraction and focusing electrode

105: deflector

107: Condenser lens

109: deflector

110: final (immersion) lens

120: electrode

121: Secondary electron detector

122a: backscattered electron detector

122b: backscattered electron detector

123: solid state sensor

124: Integrated semiconductor structure

125: n-type buried channel layer

126: Analog to digital converter

127: p-type electronic sensitive layer

127-B: top surface

127-F: front surface/bottom surface

128: pure boron layer

129: Amplifier

130: platform

131: Sample

140: electron gun/electronic source

141: Upstream

142: Down

150: original electron beam

160: system computer

C: Central area

D: Defect

e ₁₂₅ : Electronics

e ₁₂₇ : Electronics

e _FD : Electronics

e _INCIDENT : incident electron

FD: floating diffusion area

ID1: image data signal

ID2: image data signal

IDx: digital image data signal

OS: output signal

V _FD : charge/voltage

Claims (21)

A method for checking a sample, which includes: generating a main clock signal; generating an electron beam deflection scan synchronized with the main clock signal; generating a first pixel clock signal synchronized with the main clock signal; generating An original electron beam and focusing the original electron beam on a sample; using the electron beam deflection scan to cause the original electron beam to scan an area of the sample; collecting backscattered electrons from the sample in a first multi-pixel electron In the detector; in each period of the clock signal of the first pixel, the first digitized back is generated by digitizing a first output signal generated by each pixel of the first multi-pixel electronic detector Scattered signals; and using the first digitized backscattered signals to determine whether there is a defect in the area of the sample, wherein collecting backscattered electrons includes causing the backscattered electrons to pass through the first multi-pixel electron detector A pure boron layer on an electron-sensitive surface, and each of the electrons of the first multi-pixel electron detector includes a p-type electron-sensitive layer and an n-type buried layer disposed on the electron-sensitive layer An in-channel layer, an n+ floating diffusion region disposed in the buried channel layer, and an amplifier coupled to the floating diffusion region. The method of claim 1, further comprising: generating a second pixel clock signal synchronized with the main clock signal; collecting secondary electrons from the sample in a second multi-pixel electronic detector; In each period of the clock signal of the second pixel, the second multi-pixel A second output signal generated by each pixel of the electronic detector to generate a second digitized backscatter signal; and using the first digitized backscatter signal and the second digitized backscatter signal to determine the sample Whether there is a defect in this area. The method of claim 2, wherein collecting secondary electrons includes causing the secondary electrons to pass through a second pure boron layer formed on an electron sensitive surface of the second multi-pixel electron detector. The method of claim 3, wherein the first pixel clock signal and the second pixel clock signal are generated at the same frequency. The method of claim 1, further comprising determining an approximate energy of a backscattered electron from the first digitized backscattered signals. The method of claim 5, further comprising determining a type or a material of the defect in the area of the sample. The method of claim 1, wherein generating and focusing the original electron beam includes directing the original electron beam to one of an unpatterned semiconductor wafer, a patterned semiconductor wafer, a main mask, and a mask on. A method for checking a sample, which includes: generating an original electron beam and focusing the original electron beam on the same sample; Collecting backscattered electrons from the sample in a first multi-pixel electronic detector; by digitizing an output signal generated by each pixel of the first multi-pixel electronic detector to generate a first digitized back Scattered signals; and using the first digitized backscattered signals to determine whether a defect exists in a region of the sample, wherein each pixel of the first multi-pixel electron detector includes: a p-type electron sensitive layer, It is configured to generate multiple electrons in response to incident electrons entering the electron sensitive layer through a first surface of the electron sensitive layer; an n-type buried channel layer disposed on one of the electron sensitive layers On the second surface and configured to collect at least some of the plurality of electrons generated by the electron sensitive layer; an n+ floating diffusion region, which is disposed in the buried channel layer and configured to accumulate At least some of the electrons collected by the buried channel layer, such that a voltage change of the floating diffusion is proportional to the number of the electrons accumulated on the floating diffusion; and an amplifier, which is operated by It is configured to generate the output signal according to the voltage of the floating diffusion. The method of claim 8, wherein collecting backscattered electrons includes causing the backscattered electrons to pass through a pure boron layer on an electron sensitive surface of the first multi-pixel electron detector. The method of claim 8, further comprising: using a second multi-pixel electron detector to collect secondary electrons from the sample; by digitizing each pixel generated by the second multi-pixel electron detector One second Outputting a signal to generate a second digitized backscatter signal; and using the first digitized backscatter signal and the second digitized backscatter signal to determine whether there is a defect in the sample. The method of claim 10, wherein collecting secondary electrons includes causing the secondary electrons to pass through a second pure boron layer formed on an electron sensitive surface of the second multi-pixel electron detector. The method of claim 8, further comprising determining an approximate energy of a backscattered electron from the first digitized backscattered signals. The method of claim 12, further comprising determining a type or a material of the defect in the area of the sample. The method of claim 8, wherein generating the first digitized backscattered signals includes using a plurality of analog-to-digital converters, wherein one of the plurality of analog-to-digital converters is operatively coupled to receive An associated output signal generated by an associated pixel of a first multi-pixel electronic detector. A method for checking a sample, which includes: generating a main clock signal; generating an electron beam deflection scan synchronized with the main clock signal; generating a first pixel clock signal synchronized with the main clock signal; generating An original electron beam and focus the original electron beam on the same copy; Using the electron beam deflection scan to scan the original electron beam over a region of the sample; collecting backscattered electrons from the sample in a first multi-pixel electron detector; each at the first pixel clock signal During the cycle, a first digitized backscatter signal is generated by digitizing the signal in each pixel of the first multi-pixel electronic detector; and the first digitized backscatter signal is used to determine the sample of the sample Whether there is a defect in the area, where collecting backscattered electrons includes: using a first multi-pixel electron detector, the first multi-pixel electron detector includes a pure boron layer on its electronically sensitive surface, and the first Each of the electrons of a multi-pixel electron detector includes a p-type electron sensitive layer, an n-type buried channel layer disposed on the electron sensitive layer, and one of the buried channel layers n+ floating diffusion and an amplifier coupled to the floating diffusion. The method of claim 15, further comprising: generating a second pixel clock signal synchronized with the main clock signal; collecting secondary electrons from the sample in a second multi-pixel electronic detector; In each cycle of the second pixel clock signal, a second digitized backscatter signal is generated by digitizing the signal in each pixel of the second multi-pixel electronic detector; and using the first digits The backscattered signal and the second digitized backscattered signals determine whether there is a defect in the area of the sample. The method of claim 16, wherein the second multi-pixel electron detector includes a pure boron layer on its electronically sensitive surface. The method of claim 16, wherein the first pixel clock signal and the second pixel clock signal have the same frequency. The method of claim 15, further comprising: determining an approximate energy of a backscattered electron from the first digitized backscattered signals. The method of claim 19, further comprising: determining a type or a material of the defect in the area of the sample. The method of claim 15, wherein the sample includes one of an unpatterned semiconductor wafer, a patterned semiconductor wafer, a main mask, and a mask.

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