WO2011109425A1 - Silicon-on-insulator direct electron detector for low voltage electron microscopy - Google Patents

Silicon-on-insulator direct electron detector for low voltage electron microscopy Download PDF

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Publication number
WO2011109425A1
WO2011109425A1 PCT/US2011/026730 US2011026730W WO2011109425A1 WO 2011109425 A1 WO2011109425 A1 WO 2011109425A1 US 2011026730 W US2011026730 W US 2011026730W WO 2011109425 A1 WO2011109425 A1 WO 2011109425A1
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Prior art keywords
detector
electronic circuitry
insulating layer
semiconductor
high resistivity
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PCT/US2011/026730
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French (fr)
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Peter Denes
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The Regents Of The University Of California
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/244—Detectors; Associated components or circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/26—Electron or ion microscopes; Electron or ion diffraction tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/244—Detection characterized by the detecting means
    • H01J2237/2441—Semiconductor detectors, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/244—Detection characterized by the detecting means
    • H01J2237/24455—Transmitted particle detectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/244—Detection characterized by the detecting means
    • H01J2237/2446—Position sensitive detectors
    • H01J2237/2447—Imaging plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures

Definitions

  • the present invention relates to the field of semiconductor detector electronics, and particularly relates to semiconductor detector electronics for direct detection of electrons for low voltage electron microscopy.
  • TEM detectors are based on a scintillating phosphor film which is fiber optically coupled to a CCD (charge-coupled device). Electrons strike the phosphor and are converted to visible photons. These photons are then conveyed to the CCD by the fiber optic array, where they are re-converted, to electron/hole pairs, and read out as charge.
  • CCD charge-coupled device
  • Such detectors suffer several problems. Spatial resolution is a strong function of energy due to the multiple Coulomb scattering of the incident electron. Electrons are detected by entering a material and transferring energy through ionization. At energies of interest for transmission electron microscopy (-60 - 400 keV) primary electrons undergo multiple scattering as they enter the detecting material, thus limiting spatial resolution. For example, at 100 keV, in a thick detector (> 100 ⁇ ) the Point Spread Function (PSF) will be about 70 ⁇ . The PSF may be thought of as the radius of a sphere that will be filled on average by electrons in a given energy range.
  • PSF Point Spread Function
  • a second problem occurs in that the readout speed of a conventional 4-port CCD is limited.
  • a third problem results in that the detection mechanism relies on two conversion steps - electron-to- photon excitation in the scintillating phosphor and photon-to-electron excitation in the CCD - with a resulting loss of sensitivity.
  • a top layer consists of metal interconnects and insulating dielectric (typically Si0 2 ).
  • a next layer is moderately high-resistivity silicon, into which implanted regions are grown.
  • a bottom layer is a low-resistivity substrate. The first two layers are roughly 10 ⁇ thick each, and the substrate is generally several hundred ⁇ thick. High energy electrons enter the detector from the front side (the interconnect layer) and then pass through the entire detector, with ionization charge collected on the N-weil implant.
  • CMOS active pixel sensors are unable to use complementary transistors, thus limiting the functionality of on-chip circuits. Furthermore, this type of detector works well at higher energies (e.g., > 200 keV), but has limitations at lower energies. However, lower electron energies (e.g., ⁇ 120 keV, and even below 60 keV) are of interest for imaging biological samples, where the electron energy is below the displacement damage threshold.
  • a detector of low energy electrons includes a semiconductor detector having a first surface bottom side and an opposing second surface top side.
  • the semiconductor detector includes a high resistivity substrate and. a low resistivity n-doped. first surface bottom side.
  • An insulating layer is disposed on the second surface topside of the high resistivity substrate, a plurality of ohmic contacts are formed at selected, locations on the insulating layer opposite the high resistivity' substrate, and a second, semiconductor layer is disposed on the insulating layer.
  • Electronic circuitry is formed in the second semiconductor layer, electronically conductive channels are formed between the plurality of ohmic contacts and the electronic circuitry, and at least one contact to the electronic circuitry is formed for applying a second voltage to the topside of the semiconductor detector.
  • At least one interlayer dielectric is formed and patterned on the electronic circuitry, and at least one patterned metallic layer is formed on the interlayer dielectric patterned for forming interconnections in the electronic circuitry and for connection to an external signal processor.
  • a method of detecting low energy electrons in an electron beam microscope which includes an electron microscope and a direct electron detector at a back focal plane of an objective lens of the electron beam microscope.
  • the direct electron detector described, above, is a semiconductor detector having a first surface bottom side and. an opposing second, surface top side, where the low energy electron beam is incident on the first surface bottom side.
  • the semiconductor detector includes a high resistivity substrate, a low resistivity n-doped first surface bottom side, an insulating layer on the second surface topside of the high resistivity substrate, a plurality of ohmic contacts formed at selected locations on the insulating layer opposite the high resistivity substrate, a second semiconductor layer on the insulating layer, electronic components formed in the second semiconductor layer, electronically conductive channels formed between the plurality of ohmic contacts and the electronic components, at least one contact to the electronic circuitry for applying a second voltage to the topside of the semiconductor detector, at least one interlayer dielectric formed and patterned on the electronic circuitry; and at least one metallic layer formed on the interlayer dielectric patterned for forming interconnections in the electronic circuitry and for connection to an external signal processor.
  • FIGURE 1 shows a transmission electron microscope according to an embodiment of the present invention.
  • FIGURE 2 shows a silicon-on-insulator direct electron detector according to an embodiment of the present invention
  • FIGURE 3 shows a portion of a silicon-on-insulator direct electron detector with electron-hole pairs produced in response to an incident high energy electron according to an embodiment of the present invention.
  • a direct electron detector formed from an array of detector elements (e.g., pixels) may be used in an electron microscope, to obtain high resolution and fast image readout, with a high signal-to-noise ratio.
  • Silicon-on-Insuiator is a well established technique for electronics manufacturing, in which the CMOS electronic circuitry is formed in and/or on a semiconductor layer separated from the substrate by an insulating layer.
  • the substrate can be made from high-resistivity silicon, and conductive implants and contact vias through the insulating oxide are possible.
  • Such a detector is advantageous for low energy electron beams (e.g., ⁇ 40 keV) as the electron beam enters the back side (substrate side) of the SOI detector, and deposits all of its charge in a small distance.
  • CMOS Active Pixel Sensors APS cannot work for such low energy electrons because they do not penetrate the top electronic layer.
  • FIG. 1 shows an embodiment of a transmission electron microscope (TEM) 100 in accordance with the present invention.
  • the TEM 100 includes an electron beam generator 102 which produces a diverging beam 114 of electrons.
  • the beam 1 14 is focused by a first electromagnetic focusing lens 110 to focus the beam 1 14 onto a sample 108 placed at the back field plane of the beam 114.
  • the sample 108 is supported by a sample holder 104.
  • the beam passes through an objective electromagnetic lens 1 12 for imaging on a direct electron detector 106, which has two-dimensional array pixel-type circuitry (not shown).
  • the pixel elements of the detector 106 may be read, for example, in a scanned raster or other mode to a signal processor 1 16, for processing and/or storage of the image.
  • Methods and structures for reading an image from an imaging array to a signal processor 116 are w r eli known in the art, and are not an aspect of the present invention.
  • the detector 106 is a chip that includes a relatively thick substrate 202, which is also referred to as the handle wafer.
  • the thickness of the substrate 202 may be approximately 20-400 ⁇ , depending on the energy of the electron beam.
  • the thickness of the substrate 202 may be selected so that it is sufficiently thick to generate electron-hole pairs, but not so thick that scattering of electrons dominate the measurements by adversely increasing the PSF.
  • Substrate 202 is preferably high-resistivity silicon, but other materials, such as insulating germanium, and the like, may be used.
  • the substrate 202 may be preferably lightly doped n-type silicon, since ionizing radiation applied to p-type silicon changes the p- type to n-type. Therefore, maintaining n-type behavior throughout is preferred. In operation, the substrate 202 is fully depleted, and therefore insulating, allowing more ionization induced charge to be collected, which increases the signal-to-noise-ratio, reduces or eliminates lateral diffusion, which beneficially reduces the observed PSF.
  • the detector includes, in addition to the substrate 202, at least a layer of insulator 204 (e.g., an oxide such as Si0 2 ), and an electronic layer 206 (e.g., fabricated in Si) for forming signal processing and/or conditioning circuitry (not shown, but conventionally recognized in the art) for responding to the ionized electrons produced by an incident electron for imaging in a two dimensional array.
  • the electronic layer 206 may also include various interlayer dielectrics and metalizations (also not shown) for interconnecting the circuitry in the electronic layer 206 and. to enable providing signal information off-chip to the signal processor 1 16 for further signal processing.
  • the process described therein is notable for producing very low power consumption devices, and having low capacitance due to isolation from each other and the substrate 202 resulting from an insulating layer 204, as described below, which enables higher speeds than are found in conventional CCD devices fabricated using CMOS.
  • a variety of devices may be designed and fabricated in this way, including analog and digital. Circuitry formed using the process described therein are well known in the art and. do not form an aspect of the invention.
  • An insulating layer 204 is formed (by one of several growth processes) on one side of the substrate 202, referred herein as the top side.
  • the insulating layer 204 is an oxide SiO 2 , SiO, or a combination, but other insulating materials known in the art may be formed, on the substrate 202. In further discussion, for convenience, the insulating layer will be assumed to be SiO 2 without loss of generality.
  • the insulating layer 204 may be on the order of approximately 200 nm, but may be thinner or thicker.
  • the opposite, or bottom side of the substrate 202 is heavily n-doped to form a thin conductive layer 208 to which a voltage V 1 may be applied.
  • selected areas of the oxide insulating layer 204 are implanted to form implants in the silicon substrate 202.
  • the n+ implanted contacts 213 may be formed to encircle the periphery of the chip forming the detector 106, to which a voltage V 2 may be applied.
  • V 1 - V 2 This allows a voltage difference V 1 - V 2 to be applied between the conductive layer 208 on the bottom side of the substrate 202 and n+ implanted contacts 213 in electrical connection with an electronic layer 206 (described below) via an n+ implanted via 217 in the insulating layer 204 above the top side of the substrate 202 to generate an electric field that is relatively normal to the top side and conductive layer 208. Consequently, ionized electrons and holes drift along the field direction, and do not spread to contribute to broadening of the PSF.
  • the electronic layer 206 of the detector 106 is typically a second silicon wafer that is joined to the insulating layer 204 of the substrate 202.
  • a glass layer e.g., oxide, such as SiO 2
  • the glass layer on the second wafer may be approximately 50-200 nm thick.
  • Anodic bonding is one method well known in the semiconductor industry.
  • p+ ion implanted vias 216 through the glass layer provides conduction paths from the p ⁇ implanted contacts 212 to component circuitry formed in the silicon electronic layer 206 of the second wafer.
  • the silicon wafer may be typically thinned (to obtain the low power/low junction capacitance characteristics), and circuit formation processing on the exposed silicon second wafer surface then proceeds. Control of the electronic layer 206 thickness is an important aspect of the process.
  • SIMOX Separation by Implanted Oxygen
  • the SIMOX process uses a high-current oxygen-ion impianter to implant ions in the wafer surface at energies in the range of 50-200 keV. This step is followed by a high-temperature (>1300°C) anneal in an inert ambient containing some oxygen over an extended period, of several hours.
  • the wafers produced have a high-quality thin (e.g...
  • one or more layers of metal may be formed and patterned to make interconnections to devices, apply the bias field across the substrate 202, and read the states of the circuitry under the effect of charge accumulated at the p+ implanted contacts 212 due to high energy electrons penetrating and ionizing the substrate 202.
  • FIGURE 3 shows a portion 300 of a sificon-on-insulator direct electron detector with a plurality of ionization pairs of holes 304 and. electrons 306 produced in response to an incident electron beam 302 passing into the substrate 202 of the detector 106 from the first bottom side.
  • the electron beam is incident from above.
  • the detector is illustrated in an upside down representation, so that the electron beam is shown incident from below.
  • ionized electrons will be swept toward the relative positive electrode(s) and hole will be swept in the opposite direction.
  • the liberated charges of the pertinent polarity are accumulated at one or more of the p+ implanted contacts 212, depending on the trajectory of the incident electron, whereupon it is conditioned by circuitry in the electronic layer 206 for readout to the signal processor 1 16.
  • a single low energy electron is detected as a cascade of liberated holes and pairs with spatial resolution determined primarily by the pitch an array of the p+ implanted contacts 212 connected to corresponding component circuitry of the electronic layer.
  • the detector medium the high resistivity silicon of the substrate 202 faces the incident electron beam, while the electronic layer is on the opposite side of the substrate 202.
  • This separation of the readout circuitry of the electronic layer 206 from the detection medium i.e., the substrate 202) enables significant flexibility in the design and fanction of the circuitry in the electronic layer.
  • the circuitry may provide analog and/or digital on-chip capability. Because detector is based on SOI technology, the individual circuit elements can be electrically isolated from each other (reducing leakage currents and inter-device capacitive coupling), enhancing speed, reducing power consumption and relative noise.
  • the fiber optic and the phosphor are eliminated, further improving signal-to-noise and reducing backscatter increase in the PSF.
  • the thickness of the detector 106 substrate 202 may be selected so that the incident electron is substantially stopped, and all such electrons are absorbed in the substrate 202.
  • the thickness of the detector 106 substrate 202 may be selected so that the incident electron is substantially stopped, and all such electrons are absorbed in the substrate 202.
  • a higher energy electron may cause neighboring pixel elements to detect the same electron simultaneously, whereas two lower energy electrons may be discriminated on a time-of-arrival basis.
  • the ability to build high-speed circuitry in SOI makes this discrimination possible.
  • CMOS active pixel sensors APS

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Abstract

A detector of high energy electrons includes a semiconductor detector having a first surface bottom side and an opposing second surface top side. The semiconductor detector includes a high resistivity substrate and a low resistivity n-doped first surface bottom side for applying a first voltage. An insulating layer is disposed on the second surface topside of the high resistivity substrate, a plurality of ohmic contacts are formed at selected locations on the insulating layer opposite the high resistivity substrate, and a second semiconductor layer is disposed on the insulating layer. Electronic circuitry is formed in the second semiconductor layer, electronically conductive channels are formed between the plurality of ohmic contacts and the electronic circuitry, and at least one contact to the electronic circuitry is formed for applying a second voltage to the topside of the semiconductor detector. At least one interlayer dielectric is formed and patterned on the electronic circuitry.

Description

SILICON-ON-INSULATOR DIRECT ELECTRON DETECTOR FOR LOW
VOLTAGE ELECTRON MICROSCOPY
RELATED APPLICATIONS
[0001] The application claims priority to U.S. Provisional Patent Application Serial No. 61/309,105. filed March 1 , 2010, which is herein incorporated by reference in its entirety.
STATEMENT OF GOVERNMENT SUPPORT
[0002] This invention was made with government support under Contract No. DE-AC02- 05CH 11231 awarded by the U.S. Department of Energy. The government has certain rights in this invention.
FIELD OF THE INVENITON
[0003] The present invention relates to the field of semiconductor detector electronics, and particularly relates to semiconductor detector electronics for direct detection of electrons for low voltage electron microscopy.
BACKGROUND OF THE INVENTION
[0004] Traditional digital transmission electron microscopy (TEM) detectors are based on a scintillating phosphor film which is fiber optically coupled to a CCD (charge-coupled device). Electrons strike the phosphor and are converted to visible photons. These photons are then conveyed to the CCD by the fiber optic array, where they are re-converted, to electron/hole pairs, and read out as charge.
[0005] Such detectors suffer several problems. Spatial resolution is a strong function of energy due to the multiple Coulomb scattering of the incident electron. Electrons are detected by entering a material and transferring energy through ionization. At energies of interest for transmission electron microscopy (-60 - 400 keV) primary electrons undergo multiple scattering as they enter the detecting material, thus limiting spatial resolution. For example, at 100 keV, in a thick detector (> 100 μηι) the Point Spread Function (PSF) will be about 70 μηι. The PSF may be thought of as the radius of a sphere that will be filled on average by electrons in a given energy range. Although thin phosphor layers can be used, at higher energies, multiple scattering in the fiber optic array causes a significant number of electrons to backscatter into the phosphor, having the effect of increasing the PSF. A second problem occurs in that the readout speed of a conventional 4-port CCD is limited. A third problem results in that the detection mechanism relies on two conversion steps - electron-to- photon excitation in the scintillating phosphor and photon-to-electron excitation in the CCD - with a resulting loss of sensitivity.
\ 0006] Another type of electron detector for use in electron microscopy is based on CMOS active pixels. A top layer consists of metal interconnects and insulating dielectric (typically Si02). A next layer is moderately high-resistivity silicon, into which implanted regions are grown. A bottom layer is a low-resistivity substrate. The first two layers are roughly 10 μηι thick each, and the substrate is generally several hundred μπι thick. High energy electrons enter the detector from the front side (the interconnect layer) and then pass through the entire detector, with ionization charge collected on the N-weil implant. Because the high-resistivity region is near the entrance of the detector, multiple Coulomb scattering limits the size of the charge cloud in the region to a few microns for energies above 200 keV. Multiple scattering causes a large spatial distribution of electron ionization in the substrate, but since the substrate is heavily doped, electron-hole pairs created there by ionization recombine, and are not collected. [0007] CMOS active pixel sensors are unable to use complementary transistors, thus limiting the functionality of on-chip circuits. Furthermore, this type of detector works well at higher energies (e.g., > 200 keV), but has limitations at lower energies. However, lower electron energies (e.g., < 120 keV, and even below 60 keV) are of interest for imaging biological samples, where the electron energy is below the displacement damage threshold.
SUMMARY OF THE INVENTION
[0008] By way of this present invention, an improved detector and. method for use with an electron microscope is provided for detecting a low energy electron beam. In an embodiment, a detector of low energy electrons includes a semiconductor detector having a first surface bottom side and an opposing second surface top side. The semiconductor detector includes a high resistivity substrate and. a low resistivity n-doped. first surface bottom side. An insulating layer is disposed on the second surface topside of the high resistivity substrate, a plurality of ohmic contacts are formed at selected, locations on the insulating layer opposite the high resistivity' substrate, and a second, semiconductor layer is disposed on the insulating layer. Electronic circuitry is formed in the second semiconductor layer, electronically conductive channels are formed between the plurality of ohmic contacts and the electronic circuitry, and at least one contact to the electronic circuitry is formed for applying a second voltage to the topside of the semiconductor detector. At least one interlayer dielectric is formed and patterned on the electronic circuitry, and at least one patterned metallic layer is formed on the interlayer dielectric patterned for forming interconnections in the electronic circuitry and for connection to an external signal processor. [0009] An electron microscope for detecting a beam of low energy electrons includes a detector of low energy electrons, as set forth in the preceding paragraph. The electron beam enters the detector from the first surface bottom side.
[00010] According to another embodiment, a method of detecting low energy electrons in an electron beam microscope is provided which includes an electron microscope and a direct electron detector at a back focal plane of an objective lens of the electron beam microscope. The direct electron detector, described, above, is a semiconductor detector having a first surface bottom side and. an opposing second, surface top side, where the low energy electron beam is incident on the first surface bottom side. The semiconductor detector includes a high resistivity substrate, a low resistivity n-doped first surface bottom side, an insulating layer on the second surface topside of the high resistivity substrate, a plurality of ohmic contacts formed at selected locations on the insulating layer opposite the high resistivity substrate, a second semiconductor layer on the insulating layer, electronic components formed in the second semiconductor layer, electronically conductive channels formed between the plurality of ohmic contacts and the electronic components, at least one contact to the electronic circuitry for applying a second voltage to the topside of the semiconductor detector, at least one interlayer dielectric formed and patterned on the electronic circuitry; and at least one metallic layer formed on the interlayer dielectric patterned for forming interconnections in the electronic circuitry and for connection to an external signal processor.
[00011 ] The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the embodiments that follow may be better understood. Additional features and advantages of the embodiments will be described hereinafter which form the subject of the claims of the present invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should, also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention as set forth in the appended claims. The novel features which are believed to be characteristic of the present invention, both as to its organization and method of operation, together with further objects and. advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present embodiments of the present in vention.
BRIEF DESCRIPTION OF THE DRAWINGS
[00012] For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings.
[00013] FIGURE 1 shows a transmission electron microscope according to an embodiment of the present invention.
[00014] FIGURE 2 shows a silicon-on-insulator direct electron detector according to an embodiment of the present invention,
[00015] FIGURE 3 shows a portion of a silicon-on-insulator direct electron detector with electron-hole pairs produced in response to an incident high energy electron according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION [00016] Direct detection of ionized charge (in a semiconductor detector) produced, by incident high energy electrons offers a way of circumventing the above mentioned limitations of the prior art by avoiding the double conversion process, A direct electron detector, formed from an array of detector elements (e.g., pixels) may be used in an electron microscope, to obtain high resolution and fast image readout, with a high signal-to-noise ratio. In the following description, reference is made to a transmission electron microscope; however, other electron microscopes may be implemented with the disclosed detector without loss of generality.
[00017] Silicon-on-Insuiator (SOI) is a well established technique for electronics manufacturing, in which the CMOS electronic circuitry is formed in and/or on a semiconductor layer separated from the substrate by an insulating layer. With non-standard processing, the substrate can be made from high-resistivity silicon, and conductive implants and contact vias through the insulating oxide are possible. Such a detector is advantageous for low energy electron beams (e.g., <40 keV) as the electron beam enters the back side (substrate side) of the SOI detector, and deposits all of its charge in a small distance. By comparison, CMOS Active Pixel Sensors (APS) cannot work for such low energy electrons because they do not penetrate the top electronic layer. Further, because the electronic layer Si film is dielecirically separated from the substrate, complementary electronics is possible (i.e., N and P MOS transistors) unlike CMOS APS, where only one transistor polarity is possible. Further, since a CMOS APS detects only a fraction of the total higher energy electrons, the energy collected follows a Landau distribution - which is Gaussian below the peak and. has a broad high-side tail. This limits the linearity of such a detector. In the SOI case, where all charge is collected, the energy distribution is Gaussian, so that it is easy to distinguish between one or two electrons detected in a pixel. [00018] FIG. 1 shows an embodiment of a transmission electron microscope (TEM) 100 in accordance with the present invention. The TEM 100 includes an electron beam generator 102 which produces a diverging beam 114 of electrons. The beam 1 14 is focused by a first electromagnetic focusing lens 110 to focus the beam 1 14 onto a sample 108 placed at the back field plane of the beam 114. The sample 108 is supported by a sample holder 104.
[00019] The beam passes through an objective electromagnetic lens 1 12 for imaging on a direct electron detector 106, which has two-dimensional array pixel-type circuitry (not shown). The pixel elements of the detector 106 may be read, for example, in a scanned raster or other mode to a signal processor 1 16, for processing and/or storage of the image. Methods and structures for reading an image from an imaging array to a signal processor 116 are wreli known in the art, and are not an aspect of the present invention.
[00020] As shown in FIG. 2, the detector 106 is a chip that includes a relatively thick substrate 202, which is also referred to as the handle wafer. The thickness of the substrate 202 may be approximately 20-400 μηι, depending on the energy of the electron beam. The thickness of the substrate 202 may be selected so that it is sufficiently thick to generate electron-hole pairs, but not so thick that scattering of electrons dominate the measurements by adversely increasing the PSF.
[00021] Substrate 202 is preferably high-resistivity silicon, but other materials, such as insulating germanium, and the like, may be used.. The substrate 202 may be preferably lightly doped n-type silicon, since ionizing radiation applied to p-type silicon changes the p- type to n-type. Therefore, maintaining n-type behavior throughout is preferred. In operation, the substrate 202 is fully depleted, and therefore insulating, allowing more ionization induced charge to be collected, which increases the signal-to-noise-ratio, reduces or eliminates lateral diffusion, which beneficially reduces the observed PSF.
[00022] The detector includes, in addition to the substrate 202, at least a layer of insulator 204 (e.g., an oxide such as Si02), and an electronic layer 206 (e.g., fabricated in Si) for forming signal processing and/or conditioning circuitry (not shown, but conventionally recognized in the art) for responding to the ionized electrons produced by an incident electron for imaging in a two dimensional array. The electronic layer 206 may also include various interlayer dielectrics and metalizations (also not shown) for interconnecting the circuitry in the electronic layer 206 and. to enable providing signal information off-chip to the signal processor 1 16 for further signal processing.
[00023] The order in which one or more of the following fabrication steps proceeds may be subject to variation, as the process dictates. A process generally applicable to fabrication of the detector 106 has been developed, by KEK, High Energy Accelerator Research Organization, Tsukuba, japan and OKI Electric Industry Co. Ltd., Japan, as described, in T. Tsuboyarna et ai "R&D of a pixel sensor based on 0: 15 mm fully depleted SOI technology," Nuclear Instruments and Methods in Physics Research A 582 (2007) 861-865. The process described therein is notable for producing very low power consumption devices, and having low capacitance due to isolation from each other and the substrate 202 resulting from an insulating layer 204, as described below, which enables higher speeds than are found in conventional CCD devices fabricated using CMOS. A variety of devices may be designed and fabricated in this way, including analog and digital. Circuitry formed using the process described therein are well known in the art and. do not form an aspect of the invention. [00024] An insulating layer 204 is formed (by one of several growth processes) on one side of the substrate 202, referred herein as the top side. Typically the insulating layer 204 is an oxide SiO2, SiO, or a combination, but other insulating materials known in the art may be formed, on the substrate 202. In further discussion, for convenience, the insulating layer will be assumed to be SiO2 without loss of generality. The insulating layer 204 may be on the order of approximately 200 nm, but may be thinner or thicker. The opposite, or bottom side of the substrate 202 is heavily n-doped to form a thin conductive layer 208 to which a voltage V1 may be applied.
[00025] In one embodiment, selected areas of the oxide insulating layer 204 are implanted to form implants in the silicon substrate 202. Both p+ implanted contacts 212 and n+ impianted. contacts 213, penetrate the oxide layer 204 at an interface 214. The n+ implanted contacts 213 may be formed to encircle the periphery of the chip forming the detector 106, to which a voltage V2 may be applied. This allows a voltage difference V1 - V2 to be applied between the conductive layer 208 on the bottom side of the substrate 202 and n+ implanted contacts 213 in electrical connection with an electronic layer 206 (described below) via an n+ implanted via 217 in the insulating layer 204 above the top side of the substrate 202 to generate an electric field that is relatively normal to the top side and conductive layer 208. Consequently, ionized electrons and holes drift along the field direction, and do not spread to contribute to broadening of the PSF.
[00026] The electronic layer 206 of the detector 106 is typically a second silicon wafer that is joined to the insulating layer 204 of the substrate 202. A glass layer (e.g., oxide, such as SiO2) may be grown on one side, and this glass layer side is then bonded, to the insulating layer 204 of the substrate 202. The glass layer on the second wafer may be approximately 50-200 nm thick. Anodic bonding is one method well known in the semiconductor industry. p+ ion implanted vias 216 through the glass layer (as described above) provides conduction paths from the p÷ implanted contacts 212 to component circuitry formed in the silicon electronic layer 206 of the second wafer. The silicon wafer may be typically thinned (to obtain the low power/low junction capacitance characteristics), and circuit formation processing on the exposed silicon second wafer surface then proceeds. Control of the electronic layer 206 thickness is an important aspect of the process.
[00027] In another embodiment, Separation by Implanted Oxygen (SIMOX) is commonly used to manufacture low-cost SOI wafers for CMOS circuits. An example of SIMOX fabrication is described in U.S. Patent 6,740,565. The SIMOX process uses a high-current oxygen-ion impianter to implant ions in the wafer surface at energies in the range of 50-200 keV. This step is followed by a high-temperature (>1300°C) anneal in an inert ambient containing some oxygen over an extended period, of several hours. The wafers produced have a high-quality thin (e.g.. approximately 200-nm) silicon layer (where the devices of the electronic layer 206 are built), which is isolated from the supporting bulk silicon substrate by a relatively thin (50-400-nm) insulating layer 204, and which is also referred to as a buried oxide (BOX) layer 204. Varying the dose and energy of the implantation and the high- temperature annealing parameters can produce different silicon and BOX layer 204 thicknesses.
[00028] Because of the thinness of the top side silicon electronic layer 206 and insulating BOX layer 204, it is possible to ion implant conductive channels through the BOX layer to connect circuitry in the electronic layer 206 to the p+ implanted contacts 212 and. n÷ implanted contacts 213 of the high resistivity detector substrate 202. [00029] Various electronic devices, such as transistors, diodes, and the like, may be formed, in the electronic layer of the second wafer 206, where excess silicon is removed to leave the devices electrically isolated from one another, reducing leakage, and power consumption. Finally, one or more layers of metal may be formed and patterned to make interconnections to devices, apply the bias field across the substrate 202, and read the states of the circuitry under the effect of charge accumulated at the p+ implanted contacts 212 due to high energy electrons penetrating and ionizing the substrate 202.
[00030] FIGURE 3 shows a portion 300 of a sificon-on-insulator direct electron detector with a plurality of ionization pairs of holes 304 and. electrons 306 produced in response to an incident electron beam 302 passing into the substrate 202 of the detector 106 from the first bottom side. Conventionally, in an electron microscope, as shown in FIGURE 1 , the electron beam is incident from above. For convenience of description, the detector is illustrated in an upside down representation, so that the electron beam is shown incident from below. Depending on the polarity of the voltage difference V1 - V2., ionized electrons will be swept toward the relative positive electrode(s) and hole will be swept in the opposite direction. The liberated charges of the pertinent polarity are accumulated at one or more of the p+ implanted contacts 212, depending on the trajectory of the incident electron, whereupon it is conditioned by circuitry in the electronic layer 206 for readout to the signal processor 1 16. Thus, a single low energy electron is detected as a cascade of liberated holes and pairs with spatial resolution determined primarily by the pitch an array of the p+ implanted contacts 212 connected to corresponding component circuitry of the electronic layer.
[00031] It can be readily appreciated that a key advantage over prior art silicon detectors is that the detector medium (the high resistivity silicon of the substrate 202) faces the incident electron beam, while the electronic layer is on the opposite side of the substrate 202. This separation of the readout circuitry of the electronic layer 206 from the detection medium (i.e., the substrate 202) enables significant flexibility in the design and fanction of the circuitry in the electronic layer. For example the circuitry may provide analog and/or digital on-chip capability. Because detector is based on SOI technology, the individual circuit elements can be electrically isolated from each other (reducing leakage currents and inter-device capacitive coupling), enhancing speed, reducing power consumption and relative noise. This, and the fact that the drift field potential is applied across the detecting insulating silicon, reduces spreading of the PSF. Furthermore, placing the electronic layer 206 behind the detector substrate 202 (which faces and substantially absorbs the electron beam) and BOX layer 204 improves radiation hardness.
[00032] Additionally, the fiber optic and the phosphor are eliminated, further improving signal-to-noise and reducing backscatter increase in the PSF.
[00033] In low energy electron microscopy, the thickness of the detector 106 substrate 202, may be selected so that the incident electron is substantially stopped, and all such electrons are absorbed in the substrate 202. However, as lower electron energies, there is a larger relative variation in electron energy, so a means is needed to discriminate between one relatively higher energy electron and two lower energy electrons. A higher energy electron may cause neighboring pixel elements to detect the same electron simultaneously, whereas two lower energy electrons may be discriminated on a time-of-arrival basis. The ability to build high-speed circuitry in SOI makes this discrimination possible. Furthermore, by separating the detector medium (substrate 202) from the electronic layer 206, more space is available for denser circuitry with higher spatial resolution, and with more sophisticated capability (e.g., complementary CMOS transistors) than conventional CMOS active pixel sensors (APS), such as analog and digital functionality on-chip.
[00034] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the present invention as defined by the appended claims. Moreover, the scope of the present invention is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the embodiments of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

What is claimed is:
1. A detector of high energy electrons comprising:
a semiconductor detector having a first surface bottom side and an opposing second surface top side, the semiconductor detector comprising
a high resistivity substrate,
a low resistivity n-doped first surface bottom side,
an insulating layer disposed on the second surface topside of the high resistivity substrate,
a plurality of ohmic contacts formed at selected locations in the insulating layer opposite the high resistivity substrate,
a second semiconductor layer disposed on the insulating layer, electronic circuitry associated with the second semiconductor layer, and interconnections in the electronic circuitry for connection to an external signal processor,
2. The detector of claim 1 , wherein the high resistivity substrate is at least one of silicon and germanium.
3. The detector of claim 1 , wherein the high resistivity substrate is lightly doped, n-type.
4. The detector of claim i , wherein the high energy electrons are approximately from 10 keV to 400 kev
5. An electron microscope comprising a detector of low energy electrons, the detector comprising:
a semiconductor detector having a first surface bottom side and an opposing second surface top side, the semiconductor detector comprising
a high resistivity substrate,
a low resistivity n-doped first surface bottom side,
an insulating layer disposed on the second surface topside of the high resistivity substrate,
a plurality of ohmic contacts formed at selected locations on the insulating layer opposite the high resistivity substrate,
a second semiconductor layer disposed on the insulating layer, electronic circuity formed in the second semiconductor layer. electronically conductive channels formed between the plurality of ohmic contacts and the electronic circuitry,
at least one contact to the electronic circuitry for applying a second voltage to the topside of the semiconductor detector,
at least one interlayer dielectric formed and patterned on the electronic circuitry, and
at least one metallic layer formed on the interlayer dielectric patterned for forming interconnections in the electronic circuitry and for connection to an external signal processor,
5. A method of detecting high energy electrons in an electron beam microscope comprising:
providing an electron microscope; and
providing a direct electron detector at a back focal plane of an objective lens of the electron beam microscope, wherein providing the direct electron detector comprises
providing a semiconductor detector having a first surface bottom side and an opposing second surface top side, the semiconductor detector comprising
a high resistivity substrate,
a low resistivity n -doped first surface bottom side,
an insulating layer disposed on the second surface topside of the high resistivity substrate,
a plurality of ohmic contacts formed at selected locations on the insulating layer opposite the high resistivity substrate,
a second semiconductor layer disposed on the insulating layer, electronic circuitry formed in the second semiconductor layer, electronically conductive channels formed between the plurality of ohmic contacts and the electronic circuitry, at least one contact to the electronic circuitry for applying a second voltage to the topside of the semi conductor detector,
at least one interiayer dielectric formed and patterned on the electronic circuitry, and
at least one metallic layer formed on the interiayer dielectric patterned for forming interconnections in the electronic circuitry and for connection to an external signal processor.
PCT/US2011/026730 2010-03-01 2011-03-01 Silicon-on-insulator direct electron detector for low voltage electron microscopy WO2011109425A1 (en)

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