TWI694292B - Display panel - Google Patents

Abstract

A display panel includes a substrate and a plurality of pixel units. The pixel units are disposed on the substrate. Each of the pixel units includes a channel layer, an insulator layer, a first patterned metal layer, and a pixel electrode. The channel layer is disposed on the substrate. The channel layer includes a main body portion and at least one branch portion connected to the main body portion. The main body portion extends along a first direction. The main body portion and the branch portion define a first angle. The insulator layer covers the channel layer. The first patterned metal layer is disposed on the insulator layer and includes a scan line and a first gate connected to the scan line. The scan line extends along a second direction. The first gate and the scan line define a second angle. An orthogonal projection of the first gate on the substrate is between an orthogonal projection of the scan line on the substrate and an orthogonal projection of the branch portion on the substrate. The first direction is perpendicular to the second direction. The pixel electrode is electrically connected to the channel layer.

Description

Display panel

This disclosure is about a display panel.

The liquid crystal display has become the most common display on the market due to its advantages of small size and low radiation. Excluding the opaque areas blocked by the black matrix, the transparent area of each pixel area is the aperture ratio of the display panel. The larger the aperture ratio, the better the light transmittance of the display panel and the brighter the overall picture. The lower the consumption.

In the pixel structure, when the pixel electrode and the data line are too close, the stray capacitance Cpd (capacitance between pixel and data line) between the pixel electrode and the data line will increase, resulting in the voltage of the pixel electrode in the polysilicon film When the transistor is turned off, it will be affected by the signal transmitted by the data line, and a so-called cross talk will be generated, which will affect the display quality of the liquid crystal display panel. In order to reduce the crosstalk effect of the above pixel structure and maintain the aperture ratio of the pixel structure to a certain degree, many pixel structures have been proposed one after another.

The embodiment of the present disclosure provides a display panel The track layer has a main body portion and a branch portion and the first gate is designed to have a first portion and a second portion, so that the vertical projection of the shielding metal on the first substrate overlaps the vertical projection of the shading pattern on the first substrate without additional configuration The shading pattern to shield the shielding metal, and improve the aperture ratio.

In one embodiment, a display panel includes a first substrate and a plurality of pixel units. The pixel unit is disposed on the first substrate, and each pixel unit includes a channel layer, an insulating layer, a first patterned metal layer, and a pixel electrode. The channel layer is disposed on the first substrate. The channel layer has a body portion and at least one branch portion connecting the body portion. The body portion extends along the first direction, and the body portion and the branch portion are at a first angle. The insulating layer covers the channel layer. The first patterned metal layer is disposed on the insulating layer and includes a scan line and a first gate electrode connected to the scan line. The scan line extends along the second direction. The first gate electrode and the scan line are at two angles. The vertical projection of the first substrate is between the vertical projection of the scan line on the first substrate and the vertical projection of the branch portion on the first substrate, and the first direction is perpendicular to the second direction. The pixel electrode is electrically connected to the channel layer.

10.10a‧‧‧Display panel

100‧‧‧The first substrate

102‧‧‧Pixel unit

104, 104A‧‧‧channel layer

1040‧‧‧Main part

1042‧‧‧ Branch

106‧‧‧Pixel electrode

108‧‧‧Insulation

110‧‧‧scan line

112‧‧‧ First gate

1120‧‧‧Part 1

1122‧‧‧Part 2

114、114a‧‧‧Second gate

1140‧‧‧Part III

1142‧‧‧Part 4

116‧‧‧Data cable

118‧‧‧Source

120‧‧‧ Jiji

122‧‧‧Second substrate

124‧‧‧shading pattern

126‧‧‧The first protective layer

128‧‧‧Color filter unit

130‧‧‧Display medium layer

132‧‧‧flat layer

134‧‧‧Second protective layer

136‧‧‧Common electrode

138‧‧‧The third protective layer

140, 140a‧‧‧shield metal

D1‧‧‧First direction

D2‧‧‧Second direction

M1‧‧‧ First patterned metal layer

M2‧‧‧Second patterned metal layer

S1, S2‧‧‧Distance

TH1, TH2, TH3 ‧‧‧ contact hole

α1‧‧‧First angle

α2‧‧‧Second Angle

α3‧‧‧ Third angle

α4‧‧‧The fourth angle

α5‧‧‧The fifth angle

A-A’‧‧‧ line

Read the following detailed description and the corresponding diagrams to understand the various aspects of this disclosure. It should be noted that many features in the drawings are not drawn according to the standard practice in the industry. In fact, the size of the features described can be arbitrarily increased or decreased to facilitate clarity of the discussion.

Figure 1 is a top view of a display panel according to an embodiment; Figure 2 is an enlarged view of the area R of Figure 1; Figure 3 is a schematic cross-sectional view taken along line A-A' of Figure 2; and FIG. 4 is an enlarged plan view of a display panel according to another embodiment.

The spirit of the present disclosure will be clearly explained in the following figures and detailed descriptions. Any person with ordinary knowledge in the technical field who understands the embodiments of the present disclosure may be changed and modified by the techniques taught in the present disclosure. Depart from the spirit and scope of this disclosure. For example, describing "the first feature is formed on or above the second feature", in the embodiment will include the first feature and the second feature have direct contact; and will also include the first feature and the second feature are indirect Contact, with additional features formed between the first feature and the second feature. In addition, in the present disclosure, element labels and/or words will be reused in multiple examples. The purpose of repetition is to simplify and clarify, and it does not itself determine the relationship between multiple embodiments and/or the configurations in question.

In addition, relative words such as "below", "below", "below", "above" or "upper" or similar words are used in this text to facilitate description and are shown in the drawings The relationship from one element or feature to another. In addition to describing the orientation of the device in the drawings, the relative term of orientation includes the different orientation of the device under use or operation. When the device is set separately (rotated 90 degrees or other facing orientation), the relative vocabulary of orientation used in this article can also be interpreted accordingly.

FIG. 1 is a top view of a display panel 10 according to an embodiment. Referring to FIG. 1, the display panel 10 includes a first substrate 100 and a plurality of pixel units 102. The pixel unit 102 is disposed on the first substrate 100. For convenience of description, the first direction D1 and the second direction D2 are shown in FIG. 1, and the first direction D1 and the second direction The two directions D2 are different. For example, the first direction D1 and the second direction D2 are the longitudinal direction and the lateral direction of FIG. 1, respectively, and they are orthogonal to each other. The first substrate 100 may be a light-transmitting substrate, such as a glass substrate, for example. The pixel unit 102 includes a channel layer 104, a first patterned metal layer M1, a second patterned metal layer M2, and a pixel electrode 106.

Figure 2 is an enlarged view of the area R of Figure 1. Fig. 3 is a schematic cross-sectional view taken along line A-A' of Fig. 2. For convenience of explanation, the pixel electrode 106 is omitted in FIG. 2. 2 and 3, the pixel unit 102 further includes an insulating layer 108. The channel layer 104, the insulating layer 108, the first patterned metal layer M1, the second patterned metal layer M2, and the pixel electrode 106 are disposed on the first substrate 100. The insulating layer 108 covers the channel layer 104. The first patterned metal layer M1 is disposed on the insulating layer 108. The channel layer 104 has a body portion 1040 and at least one branch portion 1042 connected to the body portion 1040. The body portion 1040 extends in the first direction D1, and the body portion 1040 and the branch portion 1042 include a first angle α1. In this embodiment, the first angle α1 is a right angle, in other words, the body portion 1040 is substantially perpendicular to the branch portion 1042. In other embodiments, the first angle α1 may be an acute angle or an obtuse angle, that is, the body portion 1040 is not perpendicular to the branch portion 1042. In this embodiment, the number of branch portions 1042 of the channel layer 104 is one. In other embodiments, the number of branch portions 1042 may be greater than one. The material of the channel layer 104 may include polycrystalline material, such as polysilicon material, or metal oxide or the like, and the channel layer 104 may be changed by diffusion, ion implantation, plasma treatment, or other suitable processes The conductivity of some areas defines the conductor area and the semiconductor area. The material of the insulating layer 108 may include inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof).

The first patterned metal layer M1 includes a scan line 110 and a first gate 112 connected to the scan line 110. The scan line 110 extends along the second direction D2. The first gate 112 includes a first portion 1120 and a second portion 1122. The portion 1122 is connected to the first portion 1120. The first portion 1120 extends along the first direction D1, the second portion 1122 extends along the second direction D2, and the distance S1 between the second portion 1122 and the scan line 110 along the first direction D1 is between about 1 micron Between about 10 microns, the first portion 1120 of the first gate 112 and the scan line 110 are at a second angle α2. The vertical projection of the first gate 112 on the first substrate 100 is located perpendicular to the scan line 110 on the first substrate 100 The projection and the branch portion 1042 of the channel layer 104 are between the vertical projections of the first substrate 100. In this embodiment, the second angle α2 is a right angle. In other words, the scan line 110 is substantially perpendicular to the first portion 1120 of the first gate 112. In other embodiments, the second angle α2 may be an acute angle or an obtuse angle, that is, the scan line 110 is not perpendicular to the first gate 112.

The second portion 1122 and the first portion 1120 include a third angle α3. In this embodiment, the third angle α3 is a right angle. In other words, the first portion 1120 is substantially perpendicular to the second portion 1122. In other embodiments, the third angle α3 may be an acute angle or an obtuse angle, that is, the first portion 1120 is not perpendicular to the second portion 1122.

The first patterned metal layer M1 further includes a second gate 114 that is electrically connected to the channel layer 104A of another adjacent pixel unit. The second gate 114 includes a third portion 1140 and a fourth portion 1142. The fourth portion 1142 is connected to the third portion 1140. The third portion 1140 extends along the first direction D1, and the fourth portion 1142 extends along the second direction D2. The distance S2 between the four portions 1142 and the scan line 110 along the first direction D1 is between about 1 micrometer and about 10 micrometers. Second gate 114 The third portion 1140 and the scan line 110 are at a fourth angle α4. In this embodiment, the fourth angle α4 is a right angle. In other words, the third portion 1140 of the second gate 114 is substantially perpendicular to the scan line 110. In other embodiments, the fourth angle α4 may be an acute angle or an obtuse angle, that is, the third portion 1140 of the second gate 114 is not perpendicular to the scan line 110. In this embodiment, the first gate 112 and the second gate 114 are located on different sides of the scan line 110. In other words, the scan line 110 is located between the first gate 112 and the second gate 114. In this embodiment, the first gate 112 and the second gate 114 are located on a diagonal line of the scan line 110.

The fourth portion 1142 and the third portion 1140 sandwich a fifth angle α5. In this embodiment, the fifth angle α5 is a right angle. In other words, the third portion 1140 is substantially perpendicular to the fourth portion 1142. In other embodiments, the fifth angle α5 may be an acute angle or an obtuse angle, that is, the third portion 1140 is not perpendicular to the fourth portion 1142. In an embodiment, the first portion 1120 and the second portion 1122 of the first gate 112 are parallel to the third portion 1140 and the fourth portion 1142 of the second gate 114, respectively.

The second patterned metal layer M2 is disposed above the first patterned metal layer M1 and includes a data line 116, a source 118 and a drain 120. The source 118 and the drain 120 are electrically connected to the channel layer 104, respectively The pole 120 and the data line 116 and the source 118 are spaced apart in the second direction D2, and the drain 120 and the source 118 are also spaced apart in the first direction D1.

The display panel 10 further includes a second substrate 122, a light-shielding pattern 124, a first protective layer 126, a color filter unit 128, and a display medium layer 130. The second substrate 122 is disposed opposite to the first substrate 100. The display medium layer 130 is located between the first substrate 100 and the second substrate 122. The light shielding pattern 124 is disposed on the second substrate On 122, and between the second substrate 122 and the display medium layer 130. The second patterned metal layer M2 is disposed above the first protective layer 126. The light shielding pattern 124 covers the gaps between the pixel electrodes 106 of the adjacent pixel units 102. For example, the light shielding pattern 124 can shield the scan line 110, the first gate 112, the drain 120 and the data line 116. In other embodiments, the display panel 10 may further include other light-shielding patterns to shield the source 118. Moreover, the light-shielding pattern 124 disposed on the other pixel unit 102 can shield the second gate 114. The first protective layer 126 is disposed on the first patterned metal layer M1. Specifically, the first protective layer 126 is located between the first patterned metal layer M1 and the second patterned metal layer M2 to make the two electrically insulation. The material of the first protective layer 126 may be an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials. The organic material is, for example, a polymer material such as polyimide-based resin, epoxy-based resin, or acrylic-based resin.

In this embodiment, the display medium layer 130 is, for example, liquid crystal. However, the disclosure is not limited to this. In other embodiments, the display medium layer 130 may also be an organic light-emitting diode (OLED) or other suitable materials. In this embodiment, the material of the light-shielding pattern 124 may be a light-shielding material, such as black resin or metal. It is worth noting that the first substrate 100 further includes an alignment film (not shown), and the second substrate 122 also includes an alignment film (not shown) and other necessary elements of the liquid crystal display panel 10, which are known to those skilled in the art. It is well known, so I will not repeat its function and production method here.

In this embodiment, in order to enable the display medium layer 130 to be formed on a surface with good flatness, the display panel 10 may further include a flat layer 132 disposed between the color filter unit 128 and the display medium layer 130. Flat layer 132 The material may be an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials. The organic material is, for example, a polymer material such as polyimide-based resin, epoxy-based resin, or acrylic-based resin.

The pixel unit 102 further includes a second protective layer 134, a common electrode 136, and a third protective layer 138. The second protective layer 134 is located on the second patterned metal layer M2, the contact hole TH1 penetrates the second protective layer 134, the common electrode 136 is disposed on the second protective layer 134, and the third protective layer 138 is disposed on the second protective layer 134 and On the common electrode 136, the contact hole TH2 penetrates the third protective layer 138, the pixel electrode 106 is disposed on the third protective layer 138, and is electrically connected to the drain 120 through the contact hole TH2. The source electrode 118 is electrically connected to the channel layer 104 (for example, the body portion 1040) through the contact hole TH3.

The second protection layer 134 can provide the function of protecting and planarizing the underlying stack. For example, the second protection layer 134 can protect and planarize the second patterned metal layer M2 (such as the source 118, the drain 120, and the data line 116), the third protective layer 138 can protect and planarize the common electrode 136. The materials of the second and third protective layers 134 and 138 may be inorganic materials, organic materials, or a combination thereof. The inorganic materials are, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two materials. The organic material is, for example, a polymer material such as polyimide-based resin, epoxy-based resin, or acrylic-based resin.

The potential difference between the common electrode 136 and the pixel electrode 106 can drive the liquid crystal molecules of the display medium layer 130 to further cause the display panel 10 to display a screen. In this embodiment, the common electrode 136 and the pixel electrode 106 are disposed on the same substrate (ie, the first substrate 100).

The display panel 10 further includes a shielding metal (SM) 140. The shielding metal 140 is disposed on the first substrate 100 and formed in a region corresponding to the channel layer 104. Specifically, the shielding metal 140 is located between the first substrate 100 and the channel Between the layers 104, in other words, the vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the body portion 1040 of the channel layer 104 on the first substrate 100, and also overlaps the data line 116 on the first substrate 100 In vertical projection, the shielding metal 140 is opaque, and its role is to shield light. For example, the light from below the first substrate 100 (for example: a backlight module) and the reflected light from the side and above can be blocked from entering the body portion 1040 of the channel layer 104 formed below the data line 116 to avoid the channel layer 104 The light leakage caused by the illumination of the main body portion 1040 effectively improves the device stability and picture display quality of the transistor.

The vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the light shielding pattern 124 on the first substrate 100. In one embodiment, the vertical projection area of the shielding metal 140 on the first substrate 100 completely falls within the vertical projection area of the light shielding pattern 124 on the first substrate 100. Since the light shielding pattern 124 is an opaque area, the shielding metal 140 is designed directly under the light shielding pattern 124 (for example, the vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the light shielding pattern 124 on the first substrate 100), Therefore, it will not affect the aperture ratio. In detail, by designing the channel layer 104 to have a body portion 1040 and a branch portion 1042, and the first gate 112 to have a first portion 1120 and a second portion 1122, the position of the shielding metal 140 can be placed directly under the light shielding pattern 124, In other words, the vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the light-shielding pattern 124 on the first substrate 100. In this way, since the shielding electrode can be shielded by the existing light-shielding pattern 124, there is no need to design Additional shading pattern 124 on the shield electrode On the other hand, the aperture ratio of the display panel 10 is not limited by the shielding electrode. In other words, the shielding electrode can be used to protect the body portion 1040 of the channel layer 104 from exposure without reducing the aperture ratio of the display panel 10 Light leakage is caused, which effectively improves the device stability and picture display quality of the transistor. It can also be said that since there is no need to design an additional light-shielding pattern 124 on the shield electrode, the aperture ratio of the display panel 10 can be increased.

Since the second gate 114 and the first gate 112 are respectively located on different sides of the scan line 110, the shield electrode of the pixel unit 102 and the shield electrode disposed adjacent to another pixel unit 102 are also located on the scan line 110 The different side.

FIG. 4 is an enlarged plan view of a display panel 10a according to another embodiment. For convenience of explanation, the pixel electrode 106 is omitted in FIG. 4. The difference between FIG. 4 and FIG. 2 is the position of the second gate 114a relative to the first gate 112. Specifically, the first gate 112 and the second gate 114a are located on the same side of the scan line 110. The light-shielding pattern 124a simultaneously shields the first gate 112 and the second gate 114.

The above summarizes the features of several embodiments or examples, so that those with ordinary knowledge in the art can understand the disclosure from various aspects. Those with ordinary knowledge in this technical field should understand and can easily design or modify other processes and structures based on this disclosure to achieve the same purpose and/or to achieve the embodiments or examples described herein The same advantages. Those of ordinary skill in the art should also understand that these equivalent structures do not deviate from the disclosure spirit and scope of this disclosure. It is possible to make various changes, replacements or modifications to this disclosure without departing from the spirit and scope of this disclosure.

10‧‧‧Display panel

102‧‧‧Pixel unit

104, 104A‧‧‧channel layer

1040‧‧‧Main part

1042‧‧‧ Branch

110‧‧‧scan line

112‧‧‧ First gate

1120‧‧‧Part 1

1122‧‧‧Part 2

114‧‧‧The second gate

1140‧‧‧Part III

1142‧‧‧Part 4

116‧‧‧Data cable

118‧‧‧Source

120‧‧‧ Jiji

124‧‧‧shading pattern

140‧‧‧shield metal

D1‧‧‧First direction

D2‧‧‧Second direction

M1‧‧‧ First patterned metal layer

M2‧‧‧Second patterned metal layer

R‧‧‧Region

S1, S2‧‧‧Distance

TH2, TH3‧‧‧contact hole

α1‧‧‧First angle

α2‧‧‧Second Angle

α3‧‧‧ Third angle

α4‧‧‧The fourth angle

α5‧‧‧The fifth angle

A-A’‧‧‧ line

Claims (17)

A display panel includes: a first substrate; and a plurality of pixel units disposed on the first substrate, each pixel unit includes: a channel layer disposed on the first substrate, the channel layer has a main body The body portion is connected to the body portion with at least one branch portion. The body portion extends in a first direction. The body portion and the branch portion are at a first angle; an insulating layer covers the channel layer; and a first patterned metal layer , Disposed on the insulating layer, and includes a scan line connected to the scan line with a first gate, the scan line extends in a second direction, the first gate and the scan line are at a second angle, the The vertical projection of the first gate electrode on the first substrate is between the vertical projection of the scan line on the first substrate and the vertical projection of the branch portion on the first substrate, the first direction is perpendicular to the second direction; A pixel electrode is electrically connected to the channel layer; and a shielding metal is disposed between the first substrate and the channel layer. The display panel according to claim 1, wherein the channel layer includes a polycrystalline material. The display panel according to claim 1, wherein the first gate includes a first part and a second part, and the second part is connected to the first part at a third angle. The display panel according to claim 3, wherein the third angle is a right angle. The display panel of claim 3, wherein the first portion extends along the first direction, the second portion extends along the second direction, and the distance between the second portion and the scan line along the first direction is between about Between 1 micron and about 10 microns. The display panel according to claim 1, wherein the first patterned metal layer further includes a second gate, and the second gate and the scan line are at a fourth angle. The display panel according to claim 6, wherein the second gate is electrically connected to a channel layer adjacent to another pixel unit. The display panel according to claim 5, wherein the first gate and the second gate are located on the same side of the scan line. The display panel according to claim 5, wherein the first gate and the second gate are located on different sides of the scan line. The display panel according to claim 9, wherein the first gate and the second gate are located on a diagonal line of the scan line. The display panel according to claim 5, wherein the second gate includes a third part and a fourth part, and the fourth part is connected to the third part and a fifth angle is included. The display panel according to claim 11, wherein the fifth angle is a right angle. The display panel according to claim 1, wherein the number of the branch portions of the channel layer is one. The display panel according to claim 1, further comprising: a second substrate disposed opposite to the first substrate; and a light shielding pattern disposed on the second substrate, wherein the light shielding pattern is on the first substrate The vertical projection of is overlapped with the vertical projection of the shielding metal on the first substrate. The display panel according to claim 14, further comprising: a protective layer disposed on the first patterned metal layer; and a second patterned metal layer disposed on the protective layer and including a data line, A source electrode and a drain electrode, the source electrode and the drain electrode are electrically connected to the channel layer respectively, and the drain electrode is spaced apart from the data line and the source electrode along the second direction. The display panel according to claim 15, wherein the vertical projection of the data line on the first substrate overlaps the vertical projection of the shielding metal on the first substrate. The display panel according to claim 14, wherein the vertical projection area of the shielding metal on the first substrate falls completely within the vertical projection area of the shading pattern on the first substrate.

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