TW202034047A - Display panel - Google Patents

Abstract

A display panel includes a substrate and a plurality of pixel units. The pixel units are disposed on the substrate. Each of the pixel units includes a channel layer, an insulator layer, a first patterned metal layer, and a pixel electrode. The channel layer is disposed on the substrate. The channel layer includes a main body portion and at least one branch portion connected to the main body portion. The main body portion extends along a first direction. The main body portion and the branch portion define a first angle. The insulator layer covers the channel layer. The first patterned metal layer is disposed on the insulator layer and includes a scan line and a first gate connected to the scan line. The scan line extends along a second direction. The first gate and the scan line define a second angle. An orthogonal projection of the first gate on the substrate is between an orthogonal projection of the scan line on the substrate and an orthogonal projection of the branch portion on the substrate. The first direction is perpendicular to the second direction. The pixel electrode is electrically connected to the channel layer.

Description

Display panel

This disclosure is about a display panel.

Since liquid crystal displays have the advantages of small size and low radiation, liquid crystal displays have become the most common displays on the market. Excluding the opaque area shielded by the black matrix, the light-transmitting area of each pixel area is the aperture ratio of the display panel. The larger the aperture ratio, the better the light transmittance of the display panel and the brighter the overall picture. The lower the consumption.

In the pixel structure, when the pixel electrode and the data line are too close, the stray capacitance between the pixel electrode and the data line Cpd (capacitance between pixel and data line) will increase, resulting in the pixel electrode voltage on the polysilicon film During the period when the transistor is turned off, it will be affected by the signal transmitted by the data line, resulting in a so-called cross talk effect, which further affects the display quality of the liquid crystal display panel. In order to reduce the crosstalk effect of the above-mentioned pixel structure and maintain the aperture ratio of the pixel structure to a certain extent, many pixel structures have been proposed one after another.

The embodiment of the disclosure provides a display panel, which is designed to The track layer has a main part and a branch part, and the first gate is designed to have a first part and a second part, so that the vertical projection of the shielding metal on the first substrate can overlap with the vertical projection of the shading pattern on the first substrate, without additional configuration The light shielding pattern to shield the shielding metal, and improve the aperture ratio.

In one embodiment, a display panel includes a first substrate and a plurality of pixel units. The pixel units are disposed on the first substrate, and each pixel unit includes a channel layer, an insulating layer, a first patterned metal layer, and a pixel electrode. The channel layer is disposed on the first substrate. The channel layer has a main body and at least one branch connecting the main body. The main body extends in a first direction and the main body and the branch have a first angle. The insulating layer covers the channel layer. The first patterned metal layer is disposed on the insulating layer and includes a scan line and a first gate connected to the scan line. The scan line extends along the second direction. The first gate and the scan line are at two angles. The vertical projection of the first substrate is located between the vertical projection of the scan line on the first substrate and the vertical projection of the branch on the first substrate, and the first direction is perpendicular to the second direction. The pixel electrode is electrically connected to the channel layer.

10, 10a‧‧‧Display panel

100‧‧‧First substrate

102‧‧‧Pixel unit

104, 104A‧‧‧Passage layer

1040‧‧‧Main body

1042‧‧‧Branch

106‧‧‧Pixel electrode

108‧‧‧Insulation layer

110‧‧‧Scan line

112‧‧‧First Gate

1120‧‧‧Part One

1122‧‧‧Part Two

114, 114a‧‧‧Second gate

1140‧‧‧Part Three

1142‧‧‧Part Four

116‧‧‧Data line

118‧‧‧Source

120‧‧‧Dip pole

122‧‧‧Second substrate

124‧‧‧Shading pattern

126‧‧‧First protective layer

128‧‧‧Color filter unit

130‧‧‧Display medium layer

132‧‧‧flat layer

134‧‧‧Second protection layer

136‧‧‧Common electrode

138‧‧‧The third protective layer

140, 140a‧‧‧shielding metal

D1‧‧‧First direction

D2‧‧‧Second direction

M1‧‧‧The first patterned metal layer

M2‧‧‧Second patterned metal layer

S1, S2‧‧‧Distance

TH1, TH2, TH3‧‧‧Contact hole

α1‧‧‧First angle

α2‧‧‧Second angle

α3‧‧‧The third angle

α4‧‧‧The fourth angle

α5‧‧‧Fifth angle

A-A’‧‧‧ line segment

Read the following detailed description and match the corresponding drawings to understand many aspects of this disclosure. It should be noted that many of the features in the drawing are not drawn in actual proportions according to the standard practice in the industry. In fact, the size of the feature can be increased or decreased arbitrarily to facilitate the clarity of the discussion.

Figure 1 is a top view of a display panel according to an embodiment; Figure 2 is an enlarged view of area R in Figure 1; Figure 3 is a schematic cross-sectional view along the line A-A' of Figure 2; and FIG. 4 is an enlarged top view of a display panel according to another embodiment.

The following will clearly illustrate the spirit of the present disclosure with drawings and detailed descriptions. Anyone with ordinary knowledge in the relevant technical field can change and modify the techniques taught in the present disclosure after understanding the embodiments of the present disclosure. Depart from the spirit and scope of this disclosure. For example, the statement that "the first feature is formed on or on the second feature" will include the first feature and the second feature having direct contact; and will also include the first feature and the second feature being indirect The contact has an additional feature formed between the first feature and the second feature. In addition, the present disclosure will reuse component numbers and/or text in multiple examples. The purpose of repetition is to simplify and clarify, and it does not determine the relationship between multiple embodiments and/or the discussed configurations.

In addition, relative terms such as "below", "below", "below", "above" or "up" or similar terms are used in this article to facilitate the description of the words shown in the diagram The relationship of one element or feature to another element or feature. In addition to describing the position of the device in the diagram, the relative position vocabulary includes the different positions of the device under use or operation. When the device is additionally set (rotated by 90 degrees or other facing orientation), the relative terms of the orientation used in this article can also be explained accordingly.

FIG. 1 is a top view of a display panel 10 according to an embodiment. Referring to FIG. 1, the display panel 10 includes a first substrate 100 and a plurality of pixel units 102. The pixel unit 102 is disposed on the first substrate 100. For the convenience of description, the first direction D1 and the second direction D2 are shown in FIG. 1, and the first direction D1 and the second direction D1 are shown in FIG. The two directions D2 are different. For example, the first direction D1 and the second direction D2 are the longitudinal direction and the lateral direction in Figure 1, respectively, and they are orthogonal to each other. The first substrate 100 may be a light-transmitting substrate, such as a glass substrate. The pixel unit 102 includes a channel layer 104, a first patterned metal layer M1, a second patterned metal layer M2, and a pixel electrode 106.

Figure 2 is an enlarged view of area R in Figure 1. Figure 3 is a schematic cross-sectional view taken along the line A-A' in Figure 2. For convenience of description, the pixel electrode 106 is omitted in FIG. 2. Referring to FIGS. 2 and 3, the pixel unit 102 further includes an insulating layer 108. The channel layer 104, the insulating layer 108, the first patterned metal layer M1, the second patterned metal layer M2 and the pixel electrode 106 are disposed on the first substrate 100. The insulating layer 108 covers the channel layer 104. The first patterned metal layer M1 is disposed on the insulating layer 108. The channel layer 104 has a main body portion 1040 and at least one branch portion 1042 connecting the main body portion 1040. The main body portion 1040 extends along the first direction D1, and the main body portion 1040 and the branch portion 1042 sandwich a first angle α1. In this embodiment, the first angle α1 is a right angle, in other words, the main body portion 1040 is substantially perpendicular to the branch portion 1042. In other embodiments, the first angle α1 may be an acute angle or an obtuse angle, that is, the main portion 1040 is not perpendicular to the branch portion 1042. In this embodiment, the number of branch portions 1042 of the channel layer 104 is one. In other embodiments, the number of branch portions 1042 may be greater than one. The material of the channel layer 104 may include polycrystalline materials, such as polysilicon materials, or metal oxides or the like, and the channel layer 104 may be changed by diffusion, ion implantation, plasma treatment or other suitable processes. The conductivity of a part of the area defines the conductor area and the semiconductor area. The material of the insulating layer 108 may include inorganic materials (for example, silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof).

The first patterned metal layer M1 includes a scan line 110 and a first gate 112 connected to the scan line 110. The scan line 110 extends along a second direction D2. The first gate 112 includes a first portion 1120 and a second portion 1122. The portion 1122 is connected to the first portion 1120, the first portion 1120 extends along the first direction D1, the second portion 1122 extends along the second direction D2, and the distance S1 between the second portion 1122 and the scan line 110 along the first direction D1 is about 1 micron To about 10 microns, the first portion 1120 of the first gate 112 and the scan line 110 have a second angle α2, and the vertical projection of the first gate 112 on the first substrate 100 is at the vertical of the scan line 110 on the first substrate 100 The projection and the branch portion 1042 of the channel layer 104 are between the vertical projection of the first substrate 100. In this embodiment, the second angle α2 is a right angle. In other words, the scan line 110 is substantially perpendicular to the first portion 1120 of the first gate 112. In other embodiments, the second angle α2 may be an acute angle or an obtuse angle, that is, the scan line 110 is not perpendicular to the first gate 112.

The second portion 1122 and the first portion 1120 form a third angle α3. In this embodiment, the third angle α3 is a right angle, in other words, the first portion 1120 is substantially perpendicular to the second portion 1122. In other embodiments, the third angle α3 may be an acute angle or an obtuse angle, that is, the first portion 1120 is not perpendicular to the second portion 1122.

The first patterned metal layer M1 further includes a second gate 114, and the second gate 114 is electrically connected to the channel layer 104A adjacent to another pixel unit. The second gate 114 includes a third portion 1140 and a fourth portion 1142, the fourth portion 1142 is connected to the third portion 1140, the third portion 1140 extends along the first direction D1, and the fourth portion 1142 extends along the second direction D2. The distance S2 between the fourth portion 1142 and the scan line 110 along the first direction D1 is between about 1 micrometer and about 10 micrometers. Second gate 114 The third portion 1140 and the scan line 110 form a fourth angle α4. In this embodiment, the fourth angle α4 is a right angle. In other words, the third portion 1140 of the second gate 114 is substantially perpendicular to the scan line 110. In other embodiments, the fourth angle α4 may be an acute angle or an obtuse angle, that is, the third portion 1140 of the second gate 114 is not perpendicular to the scan line 110. In this embodiment, the first gate 112 and the second gate 114 are located on different sides of the scan line 110. In other words, the scan line 110 is located between the first gate 112 and the second gate 114. In this embodiment, the first gate 112 and the second gate 114 are located on a diagonal of the scan line 110.

The fourth part 1142 and the third part 1140 form a fifth angle α5. In this embodiment, the fifth angle α5 is a right angle, in other words, the third portion 1140 is substantially perpendicular to the fourth portion 1142. In other embodiments, the fifth angle α5 may be an acute angle or an obtuse angle, that is, the third portion 1140 is not perpendicular to the fourth portion 1142. In one embodiment, the first portion 1120 and the second portion 1122 of the first gate 112 are parallel to the third portion 1140 and the fourth portion 1142 of the second gate 114, respectively.

The second patterned metal layer M2 is disposed above the first patterned metal layer M1 and includes a data line 116, a source 118 and a drain 120. The source 118 and the drain 120 are electrically connected to the channel layer 104, and the drain The electrode 120 and the data line 116 are spaced apart from the source electrode 118 along the second direction D2, and the drain electrode 120 and the source electrode 118 are also spaced apart along the first direction D1.

The display panel 10 further includes a second substrate 122, a light shielding pattern 124, a first protection layer 126, a color filter unit 128 and a display medium layer 130, and the second substrate 122 is disposed opposite to the first substrate 100. The display medium layer 130 is located between the first substrate 100 and the second substrate 122. The shading pattern 124 is disposed on the second substrate 122 and located between the second substrate 122 and the display medium layer 130. The second patterned metal layer M2 is disposed above the first protection layer 126. The light shielding pattern 124 shields the gaps between the pixel electrodes 106 of the adjacent pixel units 102. For example, the light shielding pattern 124 can shield the scan line 110, the first gate 112, the drain 120 and the data line 116. In other embodiments, the display panel 10 may further include other light shielding patterns to shield the source electrode 118. In addition, the light shielding pattern 124 disposed on the other pixel unit 102 can shield the second gate 114. The first protective layer 126 is disposed on the first patterned metal layer M1. Specifically, the first protective layer 126 is located between the first patterned metal layer M1 and the second patterned metal layer M2 to make the two electrically conductive. insulation. The material of the first protection layer 126 can be an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials. The organic material is, for example, a polymer material such as polyimide resin, epoxy resin, or acrylic resin.

In this embodiment, the display medium layer 130 is, for example, liquid crystal. However, the present disclosure is not limited thereto. In other embodiments, the display medium layer 130 may also be an organic light-emitting diode (OLED) or other suitable materials. In this embodiment, the material of the light shielding pattern 124 can be a light shielding material, such as black resin or metal. It is worth noting that the first substrate 100 further includes an alignment film (not shown), and the second substrate 122 also includes an alignment film (not shown) and other necessary elements of the liquid crystal display panel 10, which are required by those with ordinary knowledge in the art. It's well known, so I won't repeat its function and production method here.

In this embodiment, in order to enable the display medium layer 130 to be formed on a surface with good flatness, the display panel 10 may further include a flat layer 132 disposed between the color filter unit 128 and the display medium layer 130. Flat layer 132 The material can be an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials. The organic material is, for example, a polymer material such as polyimide resin, epoxy resin, or acrylic resin.

The pixel unit 102 further includes a second protection layer 134, a common electrode 136, and a third protection layer 138. The second protection layer 134 is located on the second patterned metal layer M2, the contact hole TH1 penetrates the second protection layer 134, the common electrode 136 is configured on the second protection layer 134, and the third protection layer 138 is configured on the second protection layer 134 and On the common electrode 136, the contact hole TH2 penetrates the third protection layer 138, and the pixel electrode 106 is disposed on the third protection layer 138, and is electrically connected to the drain 120 through the contact hole TH2. The source electrode 118 is electrically connected to the channel layer 104 (for example, the main body portion 1040) through the contact hole TH3.

The second protection layer 134 can provide the functions of protecting and planarizing the underlying stack. For example, the second protection layer 134 can protect and planarize the second patterned metal layer M2 (such as the source 118, the drain 120 and the data line). 116) The third protection layer 138 can protect and planarize the common electrode 136. The material of the second and third protection layers 134 and 138 may be inorganic materials, organic materials or a combination thereof. The inorganic materials may be silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the foregoing materials. The organic material is, for example, a polymer material such as polyimide resin, epoxy resin, or acrylic resin.

The potential difference between the common electrode 136 and the pixel electrode 106 can drive the liquid crystal molecules of the display medium layer 130, thereby enabling the display panel 10 to display images. In this embodiment, the common electrode 136 and the pixel electrode 106 are disposed on the same substrate (ie, the first substrate 100).

The display panel 10 further includes a shielding metal (SM) 140. The shielding metal 140 is disposed on the first substrate 100 and formed in an area corresponding to the channel layer 104. Specifically, the shielding metal 140 is located between the first substrate 100 and the channel layer 104. Between the layers 104, in other words, the vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the main body 1040 of the channel layer 104 on the first substrate 100, and also overlaps the vertical projection of the data line 116 on the first substrate 100 For vertical projection, the shielding metal 140 is opaque, and its function is to shield light. For example, light from below the first substrate 100 (such as a backlight module) and reflected light from the side and above can be blocked from being incident on the main body portion 1040 of the channel layer 104 formed under the data line 116 to avoid the channel layer 104 The light leakage caused by the main body portion 1040 of the light source can effectively improve the stability of the transistor and the display quality of the picture.

The vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the light shielding pattern 124 on the first substrate 100. In one embodiment, the vertical projection area of the shielding metal 140 on the first substrate 100 completely falls within the vertical projection area of the light shielding pattern 124 on the first substrate 100. Since the light shielding pattern 124 is an opaque area, the shielding metal 140 is designed directly below the light shielding pattern 124 (for example, the vertical projection of the shielding metal 140 on the first substrate 100 overlaps the vertical projection of the light shielding pattern 124 on the first substrate 100), Therefore, the aperture ratio will not be affected. In detail, by designing the channel layer 104 to have a main portion 1040 and a branch portion 1042, and the first gate 112 to have a first portion 1120 and a second portion 1122, the position of the shielding metal 140 can be located directly under the light shielding pattern 124, In other words, the vertical projection of the shielding metal 140 on the first substrate 100 is overlapped with the vertical projection of the light shielding pattern 124 on the first substrate 100. In this way, since the shielding electrode can be shielded by the existing light shielding pattern 124, no design is required. Additional shading pattern 124 on the shielding electrode Above, the aperture ratio of the display panel 10 is not restricted by the shield electrode. In other words, the shield electrode can be used to protect the main body portion 1040 of the channel layer 104 from being exposed to light without reducing the aperture ratio of the display panel 10. Causes light leakage, and effectively improves the stability of the transistor and the display quality of the picture. It can also be said that because there is no need to design additional light shielding patterns 124 on the shielding electrodes, the aperture ratio of the display panel 10 can be increased.

Since the second gate electrode 114 and the first gate electrode 112 are respectively located on different sides of the scan line 110, the shielding electrode of the pixel unit 102 and the shielding electrode disposed on another adjacent pixel unit 102 are also located on the scan line 110 The opposite side.

FIG. 4 is an enlarged top view of a display panel 10a according to another embodiment. For convenience of description, the pixel electrode 106 is omitted in FIG. 4. The difference between FIG. 4 and FIG. 2 is the position of the second gate 114 a relative to the first gate 112. Specifically, the first gate 112 and the second gate 114 a are located on the same side of the scan line 110. The light shielding pattern 124a shields the first gate 112 and the second gate 114 at the same time.

The above summarizes the characteristics of several implementations or embodiments, so that those with ordinary knowledge in the field can better understand the present disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on this disclosure, so as to achieve the same purpose and/or to achieve the implementation modes or embodiments introduced herein The same advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the disclosure. Without departing from the spirit and scope of this disclosure, various changes, substitutions or modifications can be made to this disclosure.

10‧‧‧Display Panel

102‧‧‧Pixel unit

104, 104A‧‧‧Passage layer

1040‧‧‧Main body

1042‧‧‧Branch

110‧‧‧Scan line

112‧‧‧First Gate

1120‧‧‧Part One

1122‧‧‧Part Two

114‧‧‧Second Gate

1140‧‧‧Part Three

1142‧‧‧Part Four

116‧‧‧Data line

118‧‧‧Source

120‧‧‧Dip pole

124‧‧‧Shading pattern

140‧‧‧Shielding metal

D1‧‧‧First direction

D2‧‧‧Second direction

M1‧‧‧The first patterned metal layer

M2‧‧‧Second patterned metal layer

R‧‧‧Region

S1, S2‧‧‧Distance

TH2, TH3‧‧‧Contact hole

α1‧‧‧First angle

α2‧‧‧Second angle

α3‧‧‧The third angle

α4‧‧‧The fourth angle

α5‧‧‧Fifth angle

A-A’‧‧‧ line segment

Claims (18)

A display panel includes: a first substrate; and a plurality of pixel units disposed on the first substrate, each pixel unit includes: a channel layer disposed on the first substrate, the channel layer having a main body Portion and at least one branch portion are connected to the main body portion, the main body portion extends along a first direction, the main body and the branch portion form a first angle; an insulating layer covering the channel layer; a first patterned metal layer , Disposed on the insulating layer, and including a scan line and a first gate connected to the scan line, the scan line extends along a second direction, the first gate and the scan line at a second angle, the The vertical projection of the first gate on the first substrate is located between the vertical projection of the scan line on the first substrate and the vertical projection of the branch on the first substrate, and the first direction is perpendicular to the second direction; And a pixel electrode is electrically connected with the channel layer. The display panel according to claim 1, wherein the channel layer comprises polycrystalline material. The display panel according to claim 1, wherein the first gate includes a first part and a second part, and the second part is connected to the first part at a third angle. The display panel according to claim 3, wherein the third angle is a right angle. The display panel according to claim 3, wherein the first part extends along the first direction, the second part extends along the second direction, and the distance between the second part and the scan line along the first direction is about Between 1 micron and about 10 microns. The display panel according to claim 1, wherein the first patterned metal layer further includes a second gate electrode, and the second gate electrode and the scan line sandwich a fourth angle. The display panel according to claim 6, wherein the second gate is electrically connected to a channel layer adjacent to another pixel unit. The display panel according to claim 5, wherein the first gate and the second gate are located on the same side of the scan line. The display panel according to claim 5, wherein the first gate and the second gate are located on different sides of the scan line. The display panel according to claim 9, wherein the first gate and the second gate are located on a diagonal of the scan line. The display panel according to claim 5, wherein the second gate includes a third part and a fourth part, and the fourth part is connected to the third part and forms a fifth angle. The display panel according to claim 11, wherein the fifth angle is a right angle. The display panel according to claim 1, wherein the number of the branch portions of the channel layer is one. The display panel according to claim 1, further comprising: a shielding metal disposed between the first substrate and the channel layer. The display panel according to claim 14, further comprising: a second substrate disposed on the opposite side of the first substrate; and a light-shielding pattern disposed on the second substrate, wherein the light-shielding pattern is on the first substrate The vertical projection of is overlapped with the vertical projection of the shielding metal on the first substrate. The display panel according to claim 15, further comprising: a protective layer disposed on the first patterned metal layer; and a second patterned metal layer disposed on the protective layer and including a data line, A source and a drain, the source and the drain are respectively electrically connected to the channel layer, and the drain is respectively connected to the data line and the source along the second direction Separate. The display panel according to claim 16, wherein the vertical projection of the data line on the first substrate overlaps the vertical projection of the shielding metal on the first substrate. The display panel according to claim 15, wherein the vertical projection area of the shielding metal on the first substrate completely falls within the vertical projection area of the shading pattern on the first substrate.

Images